Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22033

1

T1

2

T2

6

T4

22

auto[1]

21178

1

T2

4

T4

12

T5

10

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21973

1

T1

2

T2

4

T4

20

auto[1]

21238

1

T2

6

T4

14

T5

20

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21335

1

T2

8

T4

24

T5

20

auto[1]

21876

1

T1

2

T2

2

T4

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24276

1

T1

1

T2

5

T4

17

auto[1]

18935

1

T1

1

T2

5

T4

17

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21159

1

T2

6

T4

14

T5

18

auto[1]

22052

1

T1

2

T2

4

T4

20

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21983

1

T1

2

T2

4

T4

12

auto[1]

21228

1

T2

6

T4

22

T5

16

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

712

1

T2

1

T4

1

T5

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

550

1

T2

1

T4

1

T5

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

742

1

T23

1

T14

2

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

582

1

T23

1

T14

2

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

724

1

T4

2

T8

2

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

578

1

T4

2

T14

1

T59

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1147

1

T1

1

T8

1

T41

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

976

1

T1

1

T41

1

T14

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

802

1

T10

1

T14

2

T37

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

634

1

T14

2

T37

2

T31

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

719

1

T10

2

T14

1

T59

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

572

1

T10

2

T14

1

T59

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

760

1

T4

2

T5

1

T31

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

578

1

T4

2

T5

1

T31

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

745

1

T4

1

T8

1

T23

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

559

1

T4

1

T23

1

T14

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

779

1

T2

1

T5

1

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

627

1

T2

1

T5

1

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

701

1

T5

1

T8

1

T33

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

532

1

T5

1

T33

1

T39

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

754

1

T4

1

T5

1

T10

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

595

1

T4

1

T5

1

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

757

1

T8

1

T59

1

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

559

1

T59

1

T37

1

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

775

1

T4

1

T5

1

T59

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

615

1

T4

1

T5

1

T59

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

716

1

T4

1

T5

1

T14

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

553

1

T4

1

T5

1

T14

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

767

1

T2

1

T4

2

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

604

1

T2

1

T4

2

T14

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

757

1

T5

1

T8

1

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

562

1

T5

1

T14

2

T37

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

712

1

T4

1

T8

1

T14

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

576

1

T4

1

T14

2

T37

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

770

1

T10

1

T39

1

T16

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

602

1

T10

1

T39

1

T16

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

732

1

T10

1

T14

2

T59

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

565

1

T14

2

T59

1

T37

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

749

1

T4

1

T8

1

T14

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

585

1

T4

1

T14

3

T37

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

748

1

T4

1

T8

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

583

1

T4

1

T10

1

T14

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

731

1

T4

1

T14

2

T31

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

576

1

T4

1

T14

2

T31

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

734

1

T5

1

T10

1

T37

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

592

1

T5

1

T10

1

T37

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

756

1

T2

1

T23

1

T14

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

582

1

T2

1

T14

6

T37

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

763

1

T14

3

T59

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

609

1

T14

3

T59

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

744

1

T14

2

T59

1

T37

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

573

1

T14

2

T59

1

T37

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

748

1

T23

1

T37

3

T39

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

554

1

T37

3

T39

1

T55

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

779

1

T5

1

T8

1

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

607

1

T5

1

T14

1

T59

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

734

1

T2

1

T5

3

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

548

1

T2

1

T5

3

T37

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

725

1

T4

1

T14

1

T59

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

554

1

T4

1

T14

1

T59

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

724

1

T4

1

T8

1

T37

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

559

1

T4

1

T37

1

T39

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

770

1

T8

1

T10

2

T14

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

594

1

T14

1

T37

2

T39

2