Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18736

1

T1

2

T3

8

T4

6

auto[1]

17563

1

T3

2

T4

8

T5

6

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18447

1

T1

2

T3

8

T5

10

auto[1]

17852

1

T3

2

T4

14

T5

14

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17771

1

T3

4

T4

8

T5

10

auto[1]

18528

1

T1

2

T3

6

T4

6

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20332

1

T1

1

T3

5

T4

7

auto[1]

15967

1

T1

1

T3

5

T4

7

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17724

1

T3

4

T4

2

T5

14

auto[1]

18575

1

T1

2

T3

6

T4

12

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18712

1

T1

2

T3

8

T4

10

auto[1]

17587

1

T3

2

T4

4

T5

12

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

642

1

T3

1

T9

1

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

490

1

T3

1

T9

1

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

574

1

T5

2

T9

1

T10

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

464

1

T5

2

T9

1

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

610

1

T9

2

T10

2

T36

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

482

1

T9

2

T10

2

T36

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1034

1

T1

1

T3

2

T6

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

892

1

T1

1

T3

2

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

618

1

T6

1

T9

3

T36

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

471

1

T9

3

T36

2

T34

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

638

1

T10

2

T36

1

T64

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

495

1

T10

1

T36

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

644

1

T10

1

T16

2

T37

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

516

1

T10

1

T37

2

T77

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

619

1

T5

2

T6

1

T9

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

491

1

T5

2

T9

2

T37

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

628

1

T5

2

T6

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

486

1

T5

2

T9

1

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

681

1

T4

1

T5

1

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

531

1

T4

1

T5

1

T9

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

645

1

T6

1

T10

1

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

509

1

T10

1

T36

1

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

697

1

T4

1

T6

1

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

530

1

T4

1

T36

2

T34

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

629

1

T9

2

T16

1

T17

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

509

1

T9

2

T24

5

T131

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

601

1

T9

3

T10

2

T36

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

450

1

T9

3

T36

1

T35

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

630

1

T4

1

T5

1

T36

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

485

1

T4

1

T5

1

T36

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

590

1

T3

1

T5

1

T6

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

455

1

T3

1

T5

1

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

625

1

T3

1

T6

2

T10

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

495

1

T3

1

T10

1

T36

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

598

1

T9

4

T36

5

T16

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

469

1

T9

4

T36

5

T64

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

602

1

T5

1

T6

1

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

460

1

T5

1

T9

1

T10

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

632

1

T9

2

T10

1

T16

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

481

1

T9

2

T10

1

T64

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

592

1

T6

1

T9

3

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

456

1

T9

3

T10

1

T36

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

626

1

T6

1

T9

3

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

514

1

T9

3

T10

1

T36

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

627

1

T9

4

T10

2

T36

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

487

1

T9

4

T36

3

T35

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

614

1

T9

2

T10

1

T16

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

489

1

T9

2

T10

1

T37

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

626

1

T9

1

T10

1

T34

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

490

1

T9

1

T34

1

T35

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

636

1

T6

1

T9

2

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

495

1

T9

2

T36

2

T42

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

626

1

T4

3

T9

2

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

492

1

T4

3

T9

2

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

617

1

T6

1

T9

1

T42

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

473

1

T9

1

T42

1

T37

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

625

1

T5

1

T9

1

T32

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

496

1

T5

1

T9

1

T32

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

610

1

T5

1

T9

3

T36

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

464

1

T5

1

T9

3

T36

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

597

1

T9

2

T36

2

T46

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

481

1

T9

2

T36

2

T46

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

599

1

T4

1

T9

1

T10

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

469

1

T4

1

T9

1

T36

4