| Name |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.204310995 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.1205527422 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1250997320 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.726979031 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.5569197 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.2927923243 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2539032393 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.454783759 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3722841290 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.918317629 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.4154928856 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2611845308 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.2284702691 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.4156796298 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1869675090 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.128335639 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.4206186106 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.512358577 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.215686413 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2579187289 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3548108496 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3178314607 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.4179137526 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.3433359578 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1862129392 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1992384806 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.561430000 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1534105378 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3302320125 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.971826249 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.1672786268 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2919963808 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1286951349 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.866552940 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.877661704 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3806065961 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.1304323737 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1872645788 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.4189814161 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.4007953718 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.507309962 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.3075270769 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.2795248532 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2330662944 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1580724048 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.729551279 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.628181209 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1837919553 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.1767104177 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3197793873 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.1812843138 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2400516722 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2101904512 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.242541147 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.86100119 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.48740914 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1332549180 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1718837438 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1076265010 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1740411535 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.57638282 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2715450221 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.11232650 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3784113469 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.4287475554 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2187925011 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.69881500 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.2199634760 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.1636632497 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.601863060 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1480184329 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3347309248 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.238501986 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.413849624 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.12566695 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3565674582 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.2811473860 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.3182891348 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.3025076321 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.1350907547 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.3178512538 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.3271119166 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.2821962522 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.881918381 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.693904640 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3958606523 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1801479584 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.2815594363 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.3641068236 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.2721818405 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.4144813425 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.2148817636 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.1288164158 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.1465113451 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3781930834 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3685244793 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2322672183 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1554653644 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.1131395278 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1462923744 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2181333960 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.4082370168 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3748860468 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.3323974554 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.474382252 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.1083515070 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.1727950526 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.1940953396 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.1692426869 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.1522973717 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.3450377241 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4193397155 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.2394617185 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.3815432892 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.770119837 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.2237559981 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2891165594 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3199549712 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.888676394 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.1090094115 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.1293562790 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3035448019 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.2235553663 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2016363862 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.3402948098 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.94504811 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.2262720208 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2910427294 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.403984239 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.112935828 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3106314827 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.3716705304 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.3963923284 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1811392705 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.1752097020 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.531802321 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1687193075 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.3879110952 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.2036804484 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.1801114661 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.3714270072 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.1760539658 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.3377555399 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.2750658940 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.616787212 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3031904696 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3732293842 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2044371310 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.4136769088 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.1631210582 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1988469144 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.3809669103 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.646421280 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3287462443 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.678896003 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.1247619849 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2824605380 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.283184211 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.2980734321 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.3270024440 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.2625747889 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1083676800 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.208120894 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2098623874 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1405973742 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1371468137 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2569071179 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3144301657 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.746664782 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.2960286120 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2859177535 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.2927166140 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.3192159524 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3857845132 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2941587926 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3503081342 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2362092406 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.221024276 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2527422856 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.2029129632 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.1072186789 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.834269056 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2469619399 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1446458196 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4019095960 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1359528342 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1537110264 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1274854743 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.1588951419 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.926074155 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.3982016569 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3138106760 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.125676100 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.4061313167 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1319596447 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3234421314 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.3245909928 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.4034775804 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2925997135 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.3127901808 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.2081252578 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3542010142 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3367500748 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.282732132 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.183661683 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.4118564119 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.3851963709 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2016702083 |
| /workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.1198729708 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.3331768884 |
|
|
Oct 09 09:04:06 PM UTC 24 |
Oct 09 09:04:08 PM UTC 24 |
60630632 ps |
| T2 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.58259100 |
|
|
Oct 09 09:04:06 PM UTC 24 |
Oct 09 09:04:08 PM UTC 24 |
56039852 ps |
| T3 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1328389758 |
|
|
Oct 09 09:04:07 PM UTC 24 |
Oct 09 09:04:09 PM UTC 24 |
78034118 ps |
| T4 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.1138145670 |
|
|
Oct 09 09:04:07 PM UTC 24 |
Oct 09 09:04:09 PM UTC 24 |
235144193 ps |
| T5 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.1704755038 |
|
|
Oct 09 09:04:07 PM UTC 24 |
Oct 09 09:04:10 PM UTC 24 |
228799096 ps |
| T6 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.460627093 |
|
|
Oct 09 09:04:07 PM UTC 24 |
Oct 09 09:04:10 PM UTC 24 |
50212351 ps |
| T7 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2493304685 |
|
|
Oct 09 09:04:09 PM UTC 24 |
Oct 09 09:04:11 PM UTC 24 |
41198856 ps |
| T8 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3062062994 |
|
|
Oct 09 09:04:09 PM UTC 24 |
Oct 09 09:04:11 PM UTC 24 |
214687828 ps |
| T9 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4255175891 |
|
|
Oct 09 09:04:07 PM UTC 24 |
Oct 09 09:04:11 PM UTC 24 |
1151808618 ps |
| T10 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1387939361 |
|
|
Oct 09 09:04:09 PM UTC 24 |
Oct 09 09:04:11 PM UTC 24 |
261015547 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.1606869855 |
|
|
Oct 09 09:04:10 PM UTC 24 |
Oct 09 09:04:12 PM UTC 24 |
40924072 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.2067817217 |
|
|
Oct 09 09:04:10 PM UTC 24 |
Oct 09 09:04:12 PM UTC 24 |
58189673 ps |
| T11 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3979825019 |
|
|
Oct 09 09:04:10 PM UTC 24 |
Oct 09 09:04:12 PM UTC 24 |
506927249 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.1233397465 |
|
|
Oct 09 09:04:10 PM UTC 24 |
Oct 09 09:04:12 PM UTC 24 |
67746184 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.301850129 |
|
|
Oct 09 09:04:10 PM UTC 24 |
Oct 09 09:04:12 PM UTC 24 |
207260935 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2603852188 |
|
|
Oct 09 09:04:09 PM UTC 24 |
Oct 09 09:04:13 PM UTC 24 |
1081826484 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1260331896 |
|
|
Oct 09 09:04:11 PM UTC 24 |
Oct 09 09:04:13 PM UTC 24 |
77308407 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2532091976 |
|
|
Oct 09 09:04:20 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
56431715 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.502036135 |
|
|
Oct 09 09:04:11 PM UTC 24 |
Oct 09 09:04:14 PM UTC 24 |
858074118 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.775409209 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:14 PM UTC 24 |
42155467 ps |
| T31 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.246388883 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:15 PM UTC 24 |
87184124 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.3781472658 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:15 PM UTC 24 |
112566755 ps |
| T33 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.424050837 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:15 PM UTC 24 |
61814014 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.2466250668 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:15 PM UTC 24 |
165990578 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.3636366684 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:15 PM UTC 24 |
237302633 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.575623188 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:15 PM UTC 24 |
36094865 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1988358907 |
|
|
Oct 09 09:04:14 PM UTC 24 |
Oct 09 09:04:16 PM UTC 24 |
33917828 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.793198849 |
|
|
Oct 09 09:04:14 PM UTC 24 |
Oct 09 09:04:16 PM UTC 24 |
49456396 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.156845041 |
|
|
Oct 09 09:04:14 PM UTC 24 |
Oct 09 09:04:16 PM UTC 24 |
115677202 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.3573231103 |
|
|
Oct 09 09:04:14 PM UTC 24 |
Oct 09 09:04:16 PM UTC 24 |
38505485 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.234606607 |
|
|
Oct 09 09:04:14 PM UTC 24 |
Oct 09 09:04:16 PM UTC 24 |
67883629 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.2234174034 |
|
|
Oct 09 09:04:14 PM UTC 24 |
Oct 09 09:04:17 PM UTC 24 |
397680744 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1129080690 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:17 PM UTC 24 |
791442475 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.1116579048 |
|
|
Oct 09 09:04:14 PM UTC 24 |
Oct 09 09:04:17 PM UTC 24 |
100326551 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3626567918 |
|
|
Oct 09 09:04:13 PM UTC 24 |
Oct 09 09:04:17 PM UTC 24 |
1060952285 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.4118961776 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:18 PM UTC 24 |
75556064 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.801096618 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
672882311 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.989057327 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:18 PM UTC 24 |
27120335 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.2791375715 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:18 PM UTC 24 |
116535555 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.1659869093 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:18 PM UTC 24 |
97668157 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.37637530 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:18 PM UTC 24 |
34491700 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.1456021004 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:18 PM UTC 24 |
37124940 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.1179381712 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:18 PM UTC 24 |
497523972 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3298007685 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:18 PM UTC 24 |
161438232 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.543049944 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:19 PM UTC 24 |
333193234 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.3866527901 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:19 PM UTC 24 |
270086563 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.1674924603 |
|
|
Oct 09 09:04:11 PM UTC 24 |
Oct 09 09:04:19 PM UTC 24 |
1722157510 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.8593799 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:19 PM UTC 24 |
52702757 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3153408 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:19 PM UTC 24 |
1915005639 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.686989343 |
|
|
Oct 09 09:04:17 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
130083524 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.4018915926 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
50928239 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.2067455854 |
|
|
Oct 09 09:04:12 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
2231259053 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.3427517008 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
48097107 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.1000914764 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
66980776 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.426067076 |
|
|
Oct 09 09:04:20 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
382527605 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2714999321 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
438671164 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.2879389876 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
48637258 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.1435311542 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
174881993 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.722740312 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
218660366 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.194680613 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
189038927 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.151269900 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
64117968 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.1882011315 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:20 PM UTC 24 |
125302863 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.84189183 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:21 PM UTC 24 |
1939303918 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.359758026 |
|
|
Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:21 PM UTC 24 |
855883397 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.1621494435 |
|
|
Oct 09 09:04:19 PM UTC 24 |
Oct 09 09:04:21 PM UTC 24 |
21381513 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3438582656 |
|
|
Oct 09 09:04:19 PM UTC 24 |
Oct 09 09:04:21 PM UTC 24 |
52907881 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.95337835 |
|
|
Oct 09 09:04:20 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
66310593 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3125645166 |
|
|
Oct 09 09:04:19 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
61704081 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.3733982998 |
|
|
Oct 09 09:04:20 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
70833168 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.1569721803 |
|
|
Oct 09 09:04:20 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
156820107 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.694113248 |
|
|
Oct 09 09:04:20 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
48321201 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.121636925 |
|
|
Oct 09 09:04:19 PM UTC 24 |
Oct 09 09:04:22 PM UTC 24 |
74336481 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.2412311065 |
|
|
Oct 09 09:04:20 PM UTC 24 |
Oct 09 09:04:23 PM UTC 24 |
338198967 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.772746339 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:23 PM UTC 24 |
37941732 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.2463515171 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:23 PM UTC 24 |
98394032 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2348062436 |
|
|
Oct 09 09:04:19 PM UTC 24 |
Oct 09 09:04:23 PM UTC 24 |
1048988120 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.403386574 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:23 PM UTC 24 |
57126710 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1859010821 |
|
|
Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:23 PM UTC 24 |
2743922233 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.1588951419 |
|
|
Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
114765414 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.789230470 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
94849941 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.2059345990 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
28345980 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.1047235952 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
133552149 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.2423241311 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
47208853 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.3418645728 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
316038045 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.1734272522 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
56128946 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.630192848 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
110899248 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1461201876 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
42043835 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3389883781 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
68176969 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.3288281318 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
229541684 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.4244783158 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
385491652 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.3925576706 |
|
|
Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
44711743 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3072795115 |
|
|
Oct 09 09:04:19 PM UTC 24 |
Oct 09 09:04:24 PM UTC 24 |
841411381 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1849273517 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:25 PM UTC 24 |
1171996732 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1927560409 |
|
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Oct 09 09:04:22 PM UTC 24 |
Oct 09 09:04:25 PM UTC 24 |
1436732197 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3106314827 |
|
|
Oct 09 09:04:23 PM UTC 24 |
Oct 09 09:04:25 PM UTC 24 |
60016155 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.3963923284 |
|
|
Oct 09 09:04:23 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
43251594 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2891165594 |
|
|
Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
59460773 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.2029129632 |
|
|
Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
84892618 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.3402948098 |
|
|
Oct 09 09:04:23 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
166774550 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.756216921 |
|
|
Oct 09 09:04:23 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
393194846 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.888676394 |
|
|
Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
33188656 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3035448019 |
|
|
Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
82707811 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.1293562790 |
|
|
Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
59040692 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.2016363862 |
|
|
Oct 09 09:04:23 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
243089606 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.112935828 |
|
|
Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
65555116 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.1090094115 |
|
|
Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
207669694 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.2262720208 |
|
|
Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
138595020 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1811392705 |
|
|
Oct 09 09:04:23 PM UTC 24 |
Oct 09 09:04:26 PM UTC 24 |
291851130 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3199549712 |
|
|
Oct 09 09:04:25 PM UTC 24 |
Oct 09 09:04:27 PM UTC 24 |
83554150 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.2235553663 |
|
|
Oct 09 09:04:25 PM UTC 24 |
Oct 09 09:04:27 PM UTC 24 |
41927829 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2910427294 |
|
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Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:27 PM UTC 24 |
865715888 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.4136769088 |
|
|
Oct 09 09:04:25 PM UTC 24 |
Oct 09 09:04:27 PM UTC 24 |
49053487 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.94504811 |
|
|
Oct 09 09:04:25 PM UTC 24 |
Oct 09 09:04:27 PM UTC 24 |
110523518 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.1760539658 |
|
|
Oct 09 09:04:25 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
228394786 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.3377555399 |
|
|
Oct 09 09:04:25 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
113588930 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.1752097020 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
19363543 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3287462443 |
|
|
Oct 09 09:04:29 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
85273765 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.1801114661 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
98437194 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1687193075 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
39148124 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.3809669103 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
316409181 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.2036804484 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
44606381 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2044371310 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
74654463 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.3378537718 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
1317350493 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1988469144 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
230661850 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.616787212 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
213385706 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.3714270072 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
81185456 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.3879110952 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
204488203 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.531802321 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
52321939 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.2750658940 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
120813218 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.403984239 |
|
|
Oct 09 09:04:24 PM UTC 24 |
Oct 09 09:04:28 PM UTC 24 |
903957650 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.4258737473 |
|
|
Oct 09 09:04:23 PM UTC 24 |
Oct 09 09:04:29 PM UTC 24 |
993060476 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3031904696 |
|
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Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:29 PM UTC 24 |
2801480876 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3732293842 |
|
|
Oct 09 09:04:26 PM UTC 24 |
Oct 09 09:04:29 PM UTC 24 |
1079229044 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.2527890053 |
|
|
Oct 09 09:04:21 PM UTC 24 |
Oct 09 09:04:29 PM UTC 24 |
2389180407 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2569071179 |
|
|
Oct 09 09:04:27 PM UTC 24 |
Oct 09 09:04:29 PM UTC 24 |
67487622 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.3270024440 |
|
|
Oct 09 09:04:27 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
91143123 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.2927166140 |
|
|
Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
78517206 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.2625747889 |
|
|
Oct 09 09:04:27 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
50999608 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.283184211 |
|
|
Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
36563711 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.678896003 |
|
|
Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
38548226 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.646421280 |
|
|
Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
87239350 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.2824605380 |
|
|
Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
55696204 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.2960286120 |
|
|
Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
303356755 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.208120894 |
|
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Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
244366171 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1371468137 |
|
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Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
106535350 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.1247619849 |
|
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Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
155994789 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.416066948 |
|
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Oct 09 09:04:18 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
3183301372 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2859177535 |
|
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Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:30 PM UTC 24 |
307752056 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.3716705304 |
|
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Oct 09 09:04:25 PM UTC 24 |
Oct 09 09:04:31 PM UTC 24 |
957477153 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1405973742 |
|
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Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:31 PM UTC 24 |
2076172461 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1083676800 |
|
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Oct 09 09:04:29 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
99716369 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1359528342 |
|
|
Oct 09 09:04:29 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
83983034 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.2980734321 |
|
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Oct 09 09:04:29 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
47377003 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3857845132 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
39602907 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2098623874 |
|
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Oct 09 09:04:28 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
755795515 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3503081342 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
51515650 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2527422856 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
390765066 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4019095960 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
171648149 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.86373019 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
560649950 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.926074155 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
226942538 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.3192159524 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
92377218 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2362092406 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
56274050 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.834269056 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
195429433 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.1803782188 |
|
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Oct 09 09:04:37 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
159982283 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.221024276 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:32 PM UTC 24 |
47474447 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2941587926 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:33 PM UTC 24 |
112225768 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.1072186789 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:33 PM UTC 24 |
113961471 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2469619399 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:33 PM UTC 24 |
1325814812 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3144301657 |
|
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Oct 09 09:04:29 PM UTC 24 |
Oct 09 09:04:33 PM UTC 24 |
945447396 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.183661683 |
|
|
Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
30032864 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.3982016569 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
26426606 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2016702083 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
148991214 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2925997135 |
|
|
Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
97323696 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.4034775804 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
165404284 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1537110264 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
470293792 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.125676100 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
30427759 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1446458196 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
792691068 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.1198729708 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
424339345 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3234421314 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
83816201 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1474330545 |
|
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Oct 09 09:04:16 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
47396256053 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1319596447 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
51570241 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.282732132 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:34 PM UTC 24 |
93739765 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.3127901808 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:35 PM UTC 24 |
170154616 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.4061313167 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:35 PM UTC 24 |
363463868 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.3245909928 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:35 PM UTC 24 |
65054501 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.2081252578 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:35 PM UTC 24 |
294329590 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3211635178 |
|
|
Oct 09 09:04:23 PM UTC 24 |
Oct 09 09:04:35 PM UTC 24 |
7801127584 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3138106760 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:35 PM UTC 24 |
68515418 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1274854743 |
|
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Oct 09 09:04:30 PM UTC 24 |
Oct 09 09:04:35 PM UTC 24 |
972156359 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3542010142 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
1259576268 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.2154328330 |
|
|
Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
44346952 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.941057119 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
236549976 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.95613360 |
|
|
Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
95473588 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.3685130093 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
108033973 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1494057245 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
30510691 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.215474807 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
58702283 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.35548096 |
|
|
Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
29293853 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.1850273895 |
|
|
Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
221016095 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.161614928 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
83951480 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.961610718 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
49955324 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.913386093 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:36 PM UTC 24 |
294804205 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.1678091140 |
|
|
Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:37 PM UTC 24 |
168850192 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1911388839 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:37 PM UTC 24 |
85459127 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3367500748 |
|
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Oct 09 09:04:32 PM UTC 24 |
Oct 09 09:04:37 PM UTC 24 |
863373446 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.1449563674 |
|
|
Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:37 PM UTC 24 |
62475940 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.807719040 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:37 PM UTC 24 |
624072857 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.1631210582 |
|
|
Oct 09 09:04:27 PM UTC 24 |
Oct 09 09:04:37 PM UTC 24 |
2281333026 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2715655247 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:38 PM UTC 24 |
1200817591 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.3403017105 |
|
|
Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:38 PM UTC 24 |
36007110 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1429787643 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:38 PM UTC 24 |
80868686 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2580827696 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
266532886 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1389734207 |
|
|
Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:38 PM UTC 24 |
40887199 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3626320665 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:38 PM UTC 24 |
804760192 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.498678019 |
|
|
Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
56798547 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.2774716944 |
|
|
Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
284539550 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3114276993 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
30557451 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.3538454179 |
|
|
Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
215817777 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.2027137148 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
55750380 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.2203098274 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
51648924 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3521219935 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
53400661 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.2472212043 |
|
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Oct 09 09:04:38 PM UTC 24 |
Oct 09 09:04:40 PM UTC 24 |
40392956 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.1830483161 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
115342102 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.2504176667 |
|
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Oct 09 09:04:37 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
61062735 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3261830491 |
|
|
Oct 09 09:04:37 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
37926383 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.3964641097 |
|
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Oct 09 09:04:37 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
72015678 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.2947012735 |
|
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Oct 09 09:04:37 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
48456654 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.3775484161 |
|
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Oct 09 09:04:37 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
182323022 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.4118564119 |
|
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Oct 09 09:04:34 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
910604807 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.3837376481 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:39 PM UTC 24 |
259154830 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2570278821 |
|
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Oct 09 09:04:38 PM UTC 24 |
Oct 09 09:04:40 PM UTC 24 |
87972088 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.246527653 |
|
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Oct 09 09:04:38 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
32991135 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1855354708 |
|
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Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
29751964 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.1709886648 |
|
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Oct 09 09:04:38 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
31880203 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.1102430411 |
|
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Oct 09 09:04:45 PM UTC 24 |
Oct 09 09:04:47 PM UTC 24 |
40910430 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.12585674 |
|
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Oct 09 09:04:45 PM UTC 24 |
Oct 09 09:04:47 PM UTC 24 |
241544087 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.4019488869 |
|
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Oct 09 09:04:38 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
167915553 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.353033163 |
|
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Oct 09 09:04:38 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
65948164 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.898908968 |
|
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Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
49349384 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.3236854046 |
|
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Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
72646754 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.4108251523 |
|
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Oct 09 09:04:38 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
489757941 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2082240432 |
|
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Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
401024669 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.2002909208 |
|
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Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
168310078 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.1483426250 |
|
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Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
127526956 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.48443980 |
|
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Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
44367412 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.4064684058 |
|
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Oct 09 09:04:39 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
74099882 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.60011689 |
|
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
861711451 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1037464131 |
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Oct 09 09:04:36 PM UTC 24 |
Oct 09 09:04:41 PM UTC 24 |
848742134 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.356452020 |
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Oct 09 09:04:38 PM UTC 24 |
Oct 09 09:04:42 PM UTC 24 |
777666240 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.2143141342 |
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Oct 09 09:04:40 PM UTC 24 |
Oct 09 09:04:42 PM UTC 24 |
215374900 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_08/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.1244227455 |
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Oct 09 09:04:40 PM UTC 24 |
Oct 09 09:04:43 PM UTC 24 |
310194585 ps |