Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21994

1

T1

2

T4

22

T5

14

auto[1]

20908

1

T3

14

T4

14

T5

10

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22013

1

T1

2

T3

2

T4

20

auto[1]

20889

1

T3

12

T4

16

T5

14

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20861

1

T3

8

T4

20

T5

10

auto[1]

22041

1

T1

2

T3

6

T4

16

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23973

1

T1

1

T3

7

T4

18

auto[1]

18929

1

T1

1

T3

7

T4

18

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20839

1

T3

8

T4

14

T5

8

auto[1]

22063

1

T1

2

T3

6

T4

22

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21847

1

T1

2

T3

6

T4

20

auto[1]

21055

1

T3

8

T4

16

T5

20

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

727

1

T4

1

T6

1

T26

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

572

1

T4

1

T26

1

T31

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

711

1

T10

1

T40

1

T32

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

549

1

T10

1

T32

3

T34

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

768

1

T4

2

T26

4

T33

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

611

1

T4

2

T26

4

T33

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1199

1

T1

1

T4

1

T10

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1042

1

T1

1

T4

1

T10

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

735

1

T4

2

T10

2

T26

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

588

1

T4

2

T10

2

T26

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

709

1

T6

1

T26

2

T15

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

560

1

T26

2

T16

2

T60

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

762

1

T26

2

T32

1

T34

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

608

1

T26

2

T32

1

T34

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

745

1

T5

1

T10

1

T26

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

585

1

T5

1

T26

2

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

692

1

T4

1

T6

1

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

559

1

T4

1

T26

4

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

738

1

T6

1

T10

2

T26

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

576

1

T10

1

T26

1

T31

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

729

1

T4

1

T5

1

T32

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

573

1

T4

1

T5

1

T32

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

751

1

T4

1

T10

1

T33

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

584

1

T4

1

T33

1

T16

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

725

1

T6

1

T26

2

T16

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

565

1

T26

2

T16

3

T74

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

748

1

T6

1

T10

1

T26

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

586

1

T26

3

T32

2

T33

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

735

1

T4

1

T5

3

T14

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

586

1

T4

1

T5

3

T14

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

779

1

T4

1

T5

2

T10

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

597

1

T4

1

T5

2

T26

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

721

1

T32

2

T33

2

T16

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

566

1

T32

2

T33

2

T16

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

734

1

T26

1

T15

1

T32

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

573

1

T26

1

T32

2

T16

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

711

1

T26

2

T16

3

T74

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

564

1

T26

2

T16

2

T74

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

725

1

T4

1

T5

1

T26

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

568

1

T4

1

T5

1

T26

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

734

1

T4

1

T5

1

T31

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

576

1

T4

1

T5

1

T31

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

791

1

T5

2

T6

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

636

1

T5

2

T10

1

T26

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

728

1

T3

1

T6

1

T26

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

567

1

T3

1

T26

2

T32

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

750

1

T4

2

T33

1

T34

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

598

1

T4

2

T33

1

T34

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

733

1

T6

1

T10

2

T14

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

576

1

T14

1

T26

3

T32

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

763

1

T3

1

T4

1

T32

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

575

1

T3

1

T4

1

T32

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

744

1

T3

1

T4

1

T40

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

566

1

T3

1

T4

1

T40

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

756

1

T3

1

T26

1

T32

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

591

1

T3

1

T26

1

T32

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

699

1

T3

2

T10

1

T26

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

553

1

T3

2

T10

1

T26

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

712

1

T3

1

T4

1

T5

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

557

1

T3

1

T4

1

T5

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

717

1

T6

1

T26

1

T15

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

571

1

T26

1

T32

2

T16

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

702

1

T6

1

T26

4

T32

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

551

1

T26

4

T32

2

T34

1