Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.96 98.21 96.58 99.62 96.00 96.32 100.00 99.02


Total tests in report: 1117
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
76.47 76.47 93.98 93.98 81.60 81.60 79.00 79.00 52.00 52.00 89.36 89.36 88.42 88.42 50.90 50.90 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.333794178
83.15 6.68 95.12 1.14 85.73 4.14 84.65 5.65 56.00 4.00 92.46 3.09 91.32 2.89 76.76 25.86 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.642112186
87.60 4.45 95.53 0.41 86.02 0.29 87.95 3.30 78.00 22.00 93.04 0.58 92.63 1.32 80.03 3.27 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1323752184
89.80 2.20 95.69 0.16 87.16 1.14 97.55 9.60 80.00 2.00 93.81 0.77 93.68 1.05 80.69 0.65 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.242409576
91.52 1.72 96.42 0.73 89.02 1.85 98.59 1.04 84.00 4.00 94.20 0.39 93.95 0.26 84.45 3.76 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2128160536
93.12 1.60 97.24 0.81 92.44 3.42 98.78 0.19 84.00 0.00 94.97 0.77 94.74 0.79 89.69 5.24 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.723269920
94.31 1.19 97.24 0.00 92.44 0.00 98.78 0.00 92.00 8.00 94.97 0.00 94.74 0.00 90.02 0.33 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.2373168365
95.37 1.06 97.97 0.73 93.01 0.57 99.25 0.47 96.00 4.00 95.94 0.97 95.26 0.53 90.18 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.622042584
96.05 0.68 97.97 0.00 93.30 0.29 99.62 0.38 96.00 0.00 96.13 0.19 96.84 1.58 92.47 2.29 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.3763288635
96.41 0.37 98.21 0.24 95.29 2.00 99.62 0.00 96.00 0.00 96.13 0.00 96.84 0.00 92.80 0.33 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.4219412429
96.74 0.32 98.21 0.00 95.44 0.14 99.62 0.00 96.00 0.00 96.13 0.00 96.84 0.00 94.93 2.13 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3657197911
97.04 0.30 98.21 0.00 95.58 0.14 99.62 0.00 96.00 0.00 96.13 0.00 96.84 0.00 96.89 1.96 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.299914989
97.33 0.29 98.21 0.00 95.58 0.00 99.62 0.00 96.00 0.00 96.13 0.00 98.68 1.84 97.05 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.2307896788
97.51 0.18 98.21 0.00 95.58 0.00 99.62 0.00 96.00 0.00 96.32 0.19 98.95 0.26 97.87 0.82 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.3975897528
97.62 0.12 98.21 0.00 95.86 0.29 99.62 0.00 96.00 0.00 96.32 0.00 99.47 0.53 97.87 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.2983563775
97.69 0.07 98.21 0.00 96.01 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.47 0.00 98.20 0.33 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.616933680
97.74 0.05 98.21 0.00 96.01 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.47 0.00 98.53 0.33 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.955006989
97.78 0.04 98.21 0.00 96.29 0.29 99.62 0.00 96.00 0.00 96.32 0.00 99.47 0.00 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.2314000131
97.82 0.04 98.21 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.26 98.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.3204341819
97.84 0.02 98.21 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 98.69 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.398476145
97.86 0.02 98.21 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 98.85 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.321862404
97.89 0.02 98.21 0.00 96.29 0.00 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 99.02 0.16 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1006369934
97.91 0.02 98.21 0.00 96.43 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3112902244
97.93 0.02 98.21 0.00 96.58 0.14 99.62 0.00 96.00 0.00 96.32 0.00 99.74 0.00 99.02 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.152156781

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.2161511461
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3200319352
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1992045119
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2361094502
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.4239166103
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2888351201
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.3280218098
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.947336169
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1361378269
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1481938658
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.4151672296
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.3595370711
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2264748355
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3825808987
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2386819407
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.790669714
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1187903711
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.1466377453
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.875751576
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2809153435
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.216379510
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.208719768
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.981423737
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1212786575
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1122173491
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3963049890
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.2993022979
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.382632725
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3642269744
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.896129974
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2653380447
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.4118165578
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1425280948
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1308902480
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2265588520
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.4091125998
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1459956249
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1919877173
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.322921070
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3722751061
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.3418757739
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1404959119
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.1813174074
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.1141340745
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.4047447252
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.4148726133
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3842473133
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2365892630
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.146881913
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.3543690557
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.115466659
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3738769211
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1867305009
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.2459320781
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.583032137
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.959664865
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1137342358
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.214276112
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2318993305
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2483852234
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.278570671
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.3159863007
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.102995615
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.1284555318
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3869938566
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.481461912
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.3382009219
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.474259055
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3057225342
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.1965274322
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2555259125
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.524547425
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.587059681
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2510437911
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.257357039
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.3786184785
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.3872124296
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1149758688
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.4160045400
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1229668232
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.128510653
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2255753911
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.2132200569
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.3963746487
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.362613422
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.2253212047
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.2002483953
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.4004943192
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3302012981
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.3037602185
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2823588542
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2010437750
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2591326823
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/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2896109982
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/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3283624230
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/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3613618913
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.2348229831
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/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.1696802944
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3510208765
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2690779482
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.3447532451
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2843053632
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.4098293575
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/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.411675728
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/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1956414025
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.174932583
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1892801140
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/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.3939149955
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/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3520526116
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1791172222
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.2591631133
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3914645265
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1908309768
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.967062108
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3209223987
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.1548463848
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2594249188
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.1402072297
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.2379084931
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.375415164
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1917490481
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.424904945
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2258250103
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2635181323
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.634835504
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2020554014
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3867882507
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.685119171
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1295496139
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2195017284
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1769877636
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.821308392
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2485358802
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.968448130
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1620651579
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2387791875
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.899046991
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.1710077347
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.966272915
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.1720798874
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.2365614782
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.458922860
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2475595426
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3210307343
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.3423699915
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.2421978130
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.4174467103
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.460180105
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.906066520
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.886379760
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.198198667
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3686934222
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.2316853831
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1858963511
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.533844931
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2084148310
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.2988944621
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2200947563
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.176179210
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.704511692
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4276836886
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1225467255
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2854787646
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.35284899
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1662132417
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.2256928512
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2135344317
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.3857462736



Total test records in report: 1117
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.435947660 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 29681128 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.564327505 Oct 12 12:38:44 AM UTC 24 Oct 12 12:38:46 AM UTC 24 23275739 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.3376300593 Oct 12 12:38:44 AM UTC 24 Oct 12 12:38:46 AM UTC 24 157465319 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.333794178 Oct 12 12:38:44 AM UTC 24 Oct 12 12:38:46 AM UTC 24 324000814 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.2532724317 Oct 12 12:38:44 AM UTC 24 Oct 12 12:38:46 AM UTC 24 234502670 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.2983563775 Oct 12 12:38:45 AM UTC 24 Oct 12 12:38:47 AM UTC 24 36063013 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1496491947 Oct 12 12:38:45 AM UTC 24 Oct 12 12:38:47 AM UTC 24 105130601 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.1507596443 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:48 AM UTC 24 41996761 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2060992324 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:48 AM UTC 24 28613292 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3211809299 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:48 AM UTC 24 217051010 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.2232722170 Oct 12 12:39:03 AM UTC 24 Oct 12 12:39:05 AM UTC 24 120217486 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.152156781 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:48 AM UTC 24 61785220 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.622042584 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:48 AM UTC 24 378003460 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.3154626706 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:48 AM UTC 24 92868991 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.3826821334 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:49 AM UTC 24 52335627 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.509595512 Oct 12 12:38:47 AM UTC 24 Oct 12 12:38:49 AM UTC 24 73832645 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.642112186 Oct 12 12:38:45 AM UTC 24 Oct 12 12:38:49 AM UTC 24 817981396 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1323752184 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:49 AM UTC 24 112663125 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.1587590414 Oct 12 12:38:48 AM UTC 24 Oct 12 12:38:50 AM UTC 24 47838477 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.1941780330 Oct 12 12:38:46 AM UTC 24 Oct 12 12:38:50 AM UTC 24 371108254 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.387135827 Oct 12 12:38:48 AM UTC 24 Oct 12 12:38:50 AM UTC 24 108897458 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.3204341819 Oct 12 12:38:48 AM UTC 24 Oct 12 12:38:50 AM UTC 24 42169458 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2251190983 Oct 12 12:38:45 AM UTC 24 Oct 12 12:38:50 AM UTC 24 951127523 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.4108393439 Oct 12 12:38:48 AM UTC 24 Oct 12 12:38:50 AM UTC 24 198252295 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.1043483294 Oct 12 12:38:48 AM UTC 24 Oct 12 12:38:51 AM UTC 24 273155596 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3994012473 Oct 12 12:38:47 AM UTC 24 Oct 12 12:38:51 AM UTC 24 2497959919 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.3885976644 Oct 12 12:38:49 AM UTC 24 Oct 12 12:38:51 AM UTC 24 50176615 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3705576667 Oct 12 12:38:49 AM UTC 24 Oct 12 12:38:51 AM UTC 24 30953503 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.473629978 Oct 12 12:38:50 AM UTC 24 Oct 12 12:38:51 AM UTC 24 34770026 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.4226557589 Oct 12 12:38:49 AM UTC 24 Oct 12 12:38:51 AM UTC 24 68939388 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.15371755 Oct 12 12:38:50 AM UTC 24 Oct 12 12:38:52 AM UTC 24 134864775 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.1302061405 Oct 12 12:38:50 AM UTC 24 Oct 12 12:38:52 AM UTC 24 107596239 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.768032621 Oct 12 12:38:49 AM UTC 24 Oct 12 12:38:52 AM UTC 24 264266610 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1896568539 Oct 12 12:38:49 AM UTC 24 Oct 12 12:38:54 AM UTC 24 814671982 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.973888124 Oct 12 12:38:49 AM UTC 24 Oct 12 12:38:54 AM UTC 24 805942812 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3527057432 Oct 12 12:38:53 AM UTC 24 Oct 12 12:38:56 AM UTC 24 38738217 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1871037437 Oct 12 12:38:54 AM UTC 24 Oct 12 12:38:56 AM UTC 24 32464154 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.589252466 Oct 12 12:38:54 AM UTC 24 Oct 12 12:38:56 AM UTC 24 88651349 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.3842769207 Oct 12 12:38:54 AM UTC 24 Oct 12 12:38:56 AM UTC 24 197629172 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.436471874 Oct 12 12:38:53 AM UTC 24 Oct 12 12:38:56 AM UTC 24 99351233 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.242409576 Oct 12 12:38:53 AM UTC 24 Oct 12 12:38:57 AM UTC 24 589145117 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.1765776097 Oct 12 12:38:55 AM UTC 24 Oct 12 12:38:57 AM UTC 24 129667882 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3698551692 Oct 12 12:38:55 AM UTC 24 Oct 12 12:38:57 AM UTC 24 40795206 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.1175523997 Oct 12 12:38:56 AM UTC 24 Oct 12 12:38:57 AM UTC 24 57725633 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.3991582460 Oct 12 12:38:55 AM UTC 24 Oct 12 12:38:57 AM UTC 24 260569723 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.2200771079 Oct 12 12:38:55 AM UTC 24 Oct 12 12:38:57 AM UTC 24 346716050 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.289083418 Oct 12 12:38:55 AM UTC 24 Oct 12 12:38:58 AM UTC 24 338240807 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.3295236581 Oct 12 12:38:56 AM UTC 24 Oct 12 12:38:58 AM UTC 24 78861369 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.865021480 Oct 12 12:38:56 AM UTC 24 Oct 12 12:38:58 AM UTC 24 1058990788 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3657197911 Oct 12 12:38:55 AM UTC 24 Oct 12 12:38:58 AM UTC 24 256612653 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2358316181 Oct 12 12:38:55 AM UTC 24 Oct 12 12:38:59 AM UTC 24 1011972063 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4260277727 Oct 12 12:38:55 AM UTC 24 Oct 12 12:38:59 AM UTC 24 1226865476 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.1822186009 Oct 12 12:38:54 AM UTC 24 Oct 12 12:39:00 AM UTC 24 1051793878 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2128160536 Oct 12 12:38:47 AM UTC 24 Oct 12 12:39:00 AM UTC 24 5600008189 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.3975897528 Oct 12 12:38:58 AM UTC 24 Oct 12 12:39:00 AM UTC 24 84313188 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.1103497789 Oct 12 12:38:58 AM UTC 24 Oct 12 12:39:00 AM UTC 24 160992008 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.1263624761 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 35065431 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.2373168365 Oct 12 12:38:58 AM UTC 24 Oct 12 12:39:00 AM UTC 24 46071767 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.4219251904 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 36861370 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.3310061100 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 63425351 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.4008698883 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 501102201 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.142477568 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 29803359 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.273135516 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 77131378 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.1934864425 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 385670859 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3146498196 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 66373609 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.1109859936 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:01 AM UTC 24 331084106 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2233185605 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:02 AM UTC 24 971535464 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.1003184891 Oct 12 12:39:00 AM UTC 24 Oct 12 12:39:02 AM UTC 24 40089015 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.2693697752 Oct 12 12:39:01 AM UTC 24 Oct 12 12:39:03 AM UTC 24 108996776 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.160021588 Oct 12 12:39:00 AM UTC 24 Oct 12 12:39:03 AM UTC 24 253763147 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1322195844 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:04 AM UTC 24 811730752 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2222361842 Oct 12 12:39:02 AM UTC 24 Oct 12 12:39:04 AM UTC 24 75971662 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.1641742815 Oct 12 12:39:02 AM UTC 24 Oct 12 12:39:04 AM UTC 24 76859170 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.825104466 Oct 12 12:39:03 AM UTC 24 Oct 12 12:39:05 AM UTC 24 46148193 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.2431276694 Oct 12 12:39:02 AM UTC 24 Oct 12 12:39:04 AM UTC 24 64730571 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3096200396 Oct 12 12:39:02 AM UTC 24 Oct 12 12:39:04 AM UTC 24 117305391 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.528267631 Oct 12 12:39:02 AM UTC 24 Oct 12 12:39:05 AM UTC 24 27554108 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.2766359076 Oct 12 12:39:03 AM UTC 24 Oct 12 12:39:05 AM UTC 24 60975776 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.3743711967 Oct 12 12:39:02 AM UTC 24 Oct 12 12:39:05 AM UTC 24 1497948717 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3079629466 Oct 12 12:39:03 AM UTC 24 Oct 12 12:39:05 AM UTC 24 207880652 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1923588015 Oct 12 12:38:59 AM UTC 24 Oct 12 12:39:05 AM UTC 24 3779193649 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.21369095 Oct 12 12:39:03 AM UTC 24 Oct 12 12:39:05 AM UTC 24 143492083 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.2409985775 Oct 12 12:39:02 AM UTC 24 Oct 12 12:39:05 AM UTC 24 355947981 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.4115120511 Oct 12 12:39:04 AM UTC 24 Oct 12 12:39:06 AM UTC 24 30234548 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1178230743 Oct 12 12:39:04 AM UTC 24 Oct 12 12:39:06 AM UTC 24 50888818 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1997500132 Oct 12 12:38:54 AM UTC 24 Oct 12 12:39:07 AM UTC 24 6629492348 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.2698080194 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:08 AM UTC 24 56342427 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.2434832686 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:08 AM UTC 24 61578051 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.2433444041 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:08 AM UTC 24 240625609 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.2348229831 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:08 AM UTC 24 50595420 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3618175702 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:08 AM UTC 24 60357656 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.2299693146 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:08 AM UTC 24 387349773 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.1369486241 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:08 AM UTC 24 188045775 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.3903679499 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:08 AM UTC 24 42331633 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1847881915 Oct 12 12:39:04 AM UTC 24 Oct 12 12:39:09 AM UTC 24 843741588 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.3654381513 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:09 AM UTC 24 696161187 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3630993784 Oct 12 12:39:04 AM UTC 24 Oct 12 12:39:09 AM UTC 24 801326255 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.859707408 Oct 12 12:39:08 AM UTC 24 Oct 12 12:39:10 AM UTC 24 55429989 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.3184436765 Oct 12 12:39:08 AM UTC 24 Oct 12 12:39:10 AM UTC 24 376964725 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2896109982 Oct 12 12:39:08 AM UTC 24 Oct 12 12:39:10 AM UTC 24 85837734 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3510208765 Oct 12 12:39:08 AM UTC 24 Oct 12 12:39:10 AM UTC 24 429306484 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.1696802944 Oct 12 12:39:08 AM UTC 24 Oct 12 12:39:11 AM UTC 24 333761373 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3283624230 Oct 12 12:39:08 AM UTC 24 Oct 12 12:39:12 AM UTC 24 1101793275 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.2795711324 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:12 AM UTC 24 48981772 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1750480253 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:12 AM UTC 24 28754092 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.2159423807 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:12 AM UTC 24 36965522 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1200807974 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:13 AM UTC 24 95748627 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3613618913 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:13 AM UTC 24 77297808 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.2808278283 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:13 AM UTC 24 137053191 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3827709180 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:13 AM UTC 24 117352364 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.4196869509 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:13 AM UTC 24 75555611 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.669857614 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:13 AM UTC 24 213361278 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1288653871 Oct 12 12:39:08 AM UTC 24 Oct 12 12:39:13 AM UTC 24 839936159 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.3939149955 Oct 12 12:39:12 AM UTC 24 Oct 12 12:39:14 AM UTC 24 57473440 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.2973200043 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:14 AM UTC 24 2798465817 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.3539126081 Oct 12 12:39:12 AM UTC 24 Oct 12 12:39:14 AM UTC 24 56295182 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.411675728 Oct 12 12:39:12 AM UTC 24 Oct 12 12:39:14 AM UTC 24 163641086 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1791172222 Oct 12 12:39:12 AM UTC 24 Oct 12 12:39:14 AM UTC 24 245101032 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.1484255422 Oct 12 12:39:12 AM UTC 24 Oct 12 12:39:15 AM UTC 24 458663770 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.2591631133 Oct 12 12:39:12 AM UTC 24 Oct 12 12:39:15 AM UTC 24 308272270 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.1926085095 Oct 12 12:39:06 AM UTC 24 Oct 12 12:39:16 AM UTC 24 2043015757 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2690779482 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:16 AM UTC 24 37109395 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.966272915 Oct 12 12:39:21 AM UTC 24 Oct 12 12:39:23 AM UTC 24 82523431 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.270381262 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:16 AM UTC 24 69790126 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2843053632 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:16 AM UTC 24 30906121 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.304045987 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:16 AM UTC 24 68994658 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.3447532451 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:16 AM UTC 24 74153027 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1956414025 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:16 AM UTC 24 168073518 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.4098293575 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:17 AM UTC 24 110561326 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2663863512 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:17 AM UTC 24 109624409 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.174932583 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:17 AM UTC 24 1133376295 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1892801140 Oct 12 12:39:14 AM UTC 24 Oct 12 12:39:18 AM UTC 24 856690792 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.2020554014 Oct 12 12:39:16 AM UTC 24 Oct 12 12:39:18 AM UTC 24 60486710 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.2088114366 Oct 12 12:39:16 AM UTC 24 Oct 12 12:39:18 AM UTC 24 85459593 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.2379084931 Oct 12 12:39:16 AM UTC 24 Oct 12 12:39:19 AM UTC 24 185811557 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.3092263974 Oct 12 12:39:16 AM UTC 24 Oct 12 12:39:19 AM UTC 24 111236866 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.375415164 Oct 12 12:39:16 AM UTC 24 Oct 12 12:39:19 AM UTC 24 100421860 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1295496139 Oct 12 12:39:16 AM UTC 24 Oct 12 12:39:19 AM UTC 24 184551830 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.2966535144 Oct 12 12:39:02 AM UTC 24 Oct 12 12:39:20 AM UTC 24 6019527991 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.967062108 Oct 12 12:39:18 AM UTC 24 Oct 12 12:39:20 AM UTC 24 31014498 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2195017284 Oct 12 12:39:18 AM UTC 24 Oct 12 12:39:20 AM UTC 24 194768000 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2594249188 Oct 12 12:39:18 AM UTC 24 Oct 12 12:39:20 AM UTC 24 34203561 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3914645265 Oct 12 12:39:18 AM UTC 24 Oct 12 12:39:20 AM UTC 24 39785422 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.634835504 Oct 12 12:39:18 AM UTC 24 Oct 12 12:39:21 AM UTC 24 138547053 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.1548463848 Oct 12 12:39:19 AM UTC 24 Oct 12 12:39:21 AM UTC 24 73395721 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3209223987 Oct 12 12:39:19 AM UTC 24 Oct 12 12:39:21 AM UTC 24 392863155 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.424904945 Oct 12 12:39:18 AM UTC 24 Oct 12 12:39:21 AM UTC 24 239122755 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.3058816421 Oct 12 12:39:16 AM UTC 24 Oct 12 12:39:21 AM UTC 24 1971329952 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3520526116 Oct 12 12:39:16 AM UTC 24 Oct 12 12:39:21 AM UTC 24 6498733462 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.412008207 Oct 12 12:39:10 AM UTC 24 Oct 12 12:39:22 AM UTC 24 3078895468 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2258250103 Oct 12 12:39:18 AM UTC 24 Oct 12 12:39:22 AM UTC 24 1006100382 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.3423699915 Oct 12 12:39:21 AM UTC 24 Oct 12 12:39:22 AM UTC 24 54670958 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.1402072297 Oct 12 12:39:20 AM UTC 24 Oct 12 12:39:23 AM UTC 24 50450933 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.460180105 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:24 AM UTC 24 73095038 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1917490481 Oct 12 12:39:20 AM UTC 24 Oct 12 12:39:23 AM UTC 24 595239928 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1908309768 Oct 12 12:39:20 AM UTC 24 Oct 12 12:39:23 AM UTC 24 64061521 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2635181323 Oct 12 12:39:18 AM UTC 24 Oct 12 12:39:23 AM UTC 24 816196968 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1769877636 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:25 AM UTC 24 117657364 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2485358802 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:25 AM UTC 24 108309504 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2387791875 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:25 AM UTC 24 52287890 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.968448130 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:25 AM UTC 24 203619953 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.1710077347 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:25 AM UTC 24 131390181 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.3210307343 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:25 AM UTC 24 65590838 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.906066520 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:25 AM UTC 24 310002978 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.2365614782 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:26 AM UTC 24 152187937 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.458922860 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:27 AM UTC 24 894150633 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2475595426 Oct 12 12:39:23 AM UTC 24 Oct 12 12:39:28 AM UTC 24 1020537740 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3867882507 Oct 12 12:39:20 AM UTC 24 Oct 12 12:39:28 AM UTC 24 1442955637 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.2349507222 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 38122871 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.1620651579 Oct 12 12:39:27 AM UTC 24 Oct 12 12:39:29 AM UTC 24 50313131 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.410927333 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 35026956 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.35284899 Oct 12 12:39:27 AM UTC 24 Oct 12 12:39:29 AM UTC 24 30218183 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.821308392 Oct 12 12:39:27 AM UTC 24 Oct 12 12:39:29 AM UTC 24 88025133 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.899046991 Oct 12 12:39:27 AM UTC 24 Oct 12 12:39:29 AM UTC 24 71233469 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3686934222 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 37128147 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.2988944621 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 98769421 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.1720798874 Oct 12 12:39:27 AM UTC 24 Oct 12 12:39:30 AM UTC 24 112276650 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.533844931 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 43736021 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.886379760 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 63066349 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2200947563 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 61408962 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2854787646 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 69394832 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.2421978130 Oct 12 12:39:27 AM UTC 24 Oct 12 12:39:30 AM UTC 24 1452922487 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.3857462736 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 530038312 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.704511692 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 291678417 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2135344317 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:30 AM UTC 24 289170561 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1225467255 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:32 AM UTC 24 1145535515 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4276836886 Oct 12 12:39:28 AM UTC 24 Oct 12 12:39:32 AM UTC 24 809390605 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.685119171 Oct 12 12:39:20 AM UTC 24 Oct 12 12:39:35 AM UTC 24 4543810186 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1858963511 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:36 AM UTC 24 41924019 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2084148310 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:36 AM UTC 24 56735871 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.198198667 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:36 AM UTC 24 110947686 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.2316853831 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:36 AM UTC 24 212597472 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.176179210 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:36 AM UTC 24 117482042 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.1720816486 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:37 AM UTC 24 32464332 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.2054727521 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:37 AM UTC 24 30703689 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.4036289951 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:37 AM UTC 24 41781931 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.4279979234 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 79194853 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.2397977327 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:37 AM UTC 24 212065225 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.164320936 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:37 AM UTC 24 126378204 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.2859699714 Oct 12 12:39:35 AM UTC 24 Oct 12 12:39:37 AM UTC 24 65092435 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.2445868982 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:37 AM UTC 24 64837887 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.259362203 Oct 12 12:39:35 AM UTC 24 Oct 12 12:39:37 AM UTC 24 175072998 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.2831185469 Oct 12 12:39:35 AM UTC 24 Oct 12 12:39:37 AM UTC 24 59367720 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.535122492 Oct 12 12:39:35 AM UTC 24 Oct 12 12:39:37 AM UTC 24 114259954 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.167750926 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:37 AM UTC 24 71501154 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.4181958009 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:37 AM UTC 24 276557130 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.762629589 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:39 AM UTC 24 992625570 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.4174467103 Oct 12 12:39:27 AM UTC 24 Oct 12 12:39:39 AM UTC 24 7186365900 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1883901952 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:39 AM UTC 24 844325576 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1662132417 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:40 AM UTC 24 3023795278 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.2036069630 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:41 AM UTC 24 43545378 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.2356161919 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:41 AM UTC 24 55502358 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3917349669 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:41 AM UTC 24 109573806 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.1606717165 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:41 AM UTC 24 64981921 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.4019360330 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:41 AM UTC 24 48596936 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.1950780111 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:41 AM UTC 24 142230696 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.2388599185 Oct 12 12:39:40 AM UTC 24 Oct 12 12:39:42 AM UTC 24 37353253 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.3916256820 Oct 12 12:39:40 AM UTC 24 Oct 12 12:39:42 AM UTC 24 109248034 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.2281565273 Oct 12 12:39:40 AM UTC 24 Oct 12 12:39:42 AM UTC 24 110613572 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.36772864 Oct 12 12:39:40 AM UTC 24 Oct 12 12:39:42 AM UTC 24 110578122 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1411140063 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:42 AM UTC 24 69156705 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3552317915 Oct 12 12:39:40 AM UTC 24 Oct 12 12:39:42 AM UTC 24 64299800 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.2657375343 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:42 AM UTC 24 223677367 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.2149234198 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:42 AM UTC 24 284423365 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.3119579039 Oct 12 12:39:40 AM UTC 24 Oct 12 12:39:42 AM UTC 24 403062315 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.2256928512 Oct 12 12:39:34 AM UTC 24 Oct 12 12:39:43 AM UTC 24 4693485551 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2932785884 Oct 12 12:39:40 AM UTC 24 Oct 12 12:39:44 AM UTC 24 854580754 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1279511032 Oct 12 12:39:40 AM UTC 24 Oct 12 12:39:44 AM UTC 24 870227435 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.889067666 Oct 12 12:39:39 AM UTC 24 Oct 12 12:39:44 AM UTC 24 1034049490 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.133928049 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 82421445 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.1611787046 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 94917082 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.254233543 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 49727125 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.1821258035 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 106454590 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.233625060 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 29282193 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.745572874 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:46 AM UTC 24 342707587 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.3927099017 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:47 AM UTC 24 55513516 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.3445116863 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:47 AM UTC 24 58098786 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3876032220 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:47 AM UTC 24 72063876 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2109306582 Oct 12 12:39:45 AM UTC 24 Oct 12 12:39:47 AM UTC 24 388760032 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.4022463229 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:47 AM UTC 24 177076330 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2479635241 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:48 AM UTC 24 1422349942 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1407337391 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:48 AM UTC 24 909540241 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.2606134828 Oct 12 12:39:48 AM UTC 24 Oct 12 12:39:50 AM UTC 24 54711832 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.647960286 Oct 12 12:40:00 AM UTC 24 Oct 12 12:40:02 AM UTC 24 43691233 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.1995908145 Oct 12 12:39:48 AM UTC 24 Oct 12 12:39:50 AM UTC 24 79760814 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.1087962088 Oct 12 12:39:48 AM UTC 24 Oct 12 12:39:50 AM UTC 24 38927731 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.544359170 Oct 12 12:39:48 AM UTC 24 Oct 12 12:39:50 AM UTC 24 173135450 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.1702160838 Oct 12 12:40:00 AM UTC 24 Oct 12 12:40:03 AM UTC 24 201393771 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.1470736975 Oct 12 12:39:44 AM UTC 24 Oct 12 12:39:50 AM UTC 24 2352739995 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.3646455081 Oct 12 12:40:01 AM UTC 24 Oct 12 12:40:03 AM UTC 24 64317852 ps
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