Group : pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 3 0 3 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
main_power_reset_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::main_power_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
reset_cross 3 0 3 100.00 100 1 1 0


Summary for Variable main_power_reset_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_power_reset_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 27007 1 T1 2 T2 2 T3 9
auto[1] 4751 1 T2 1 T3 3 T14 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 12955 1 T1 1 T2 3 T3 5
auto[1] 18803 1 T1 1 T3 7 T4 18


Summary for Cross reset_cross

Samples crossed: main_power_reset_cp sleep_cp
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 3 0 3 100.00
Automatically Generated Cross Bins 3 0 3 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for reset_cross

Bins
main_power_reset_cp   sleep_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 8204 1 T1 1 T2 2 T3 2
auto[0] auto[1] 18803 1 T1 1 T3 7 T4 18
auto[1] auto[0] 4751 1 T2 1 T3 3 T14 2


User Defined Cross Bins for reset_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal