4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rstmgr_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | rstmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rstmgr_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rstmgr_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rstmgr_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rstmgr_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rstmgr_csr_rw | 0 | 20 | 0.00 | ||
| rstmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | reset_stretcher | rstmgr_por_stretcher | 0 | 50 | 0.00 | ||
| V2 | sw_rst | rstmgr_sw_rst | 0 | 50 | 0.00 | ||
| V2 | sw_rst_reset_race | rstmgr_sw_rst_reset_race | 0 | 50 | 0.00 | ||
| V2 | reset_info | rstmgr_reset | 0 | 50 | 0.00 | ||
| V2 | cpu_info | rstmgr_reset | 0 | 50 | 0.00 | ||
| V2 | alert_info | rstmgr_reset | 0 | 50 | 0.00 | ||
| V2 | reset_info_capture | rstmgr_reset | 0 | 50 | 0.00 | ||
| V2 | stress_all | rstmgr_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | rstmgr_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rstmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rstmgr_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rstmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| rstmgr_csr_rw | 0 | 20 | 0.00 | ||||
| rstmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| rstmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rstmgr_csr_hw_reset | 0 | 5 | 0.00 | ||
| rstmgr_csr_rw | 0 | 20 | 0.00 | ||||
| rstmgr_csr_aliasing | 0 | 5 | 0.00 | ||||
| rstmgr_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 340 | 0.00 | |||
| V2S | tl_intg_err | rstmgr_sec_cm | 0 | 5 | 0.00 | ||
| rstmgr_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_count_check | rstmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | rstmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | rstmgr_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_scan_intersig_mubi | rstmgr_sec_cm_scan_intersig_mubi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_leaf_rst_bkgn_chk | rstmgr_leaf_rst_cnsty | 0 | 50 | 0.00 | ||
| V2S | sec_cm_leaf_rst_shadow | rstmgr_leaf_rst_shadow_attack | 0 | 50 | 0.00 | ||
| V2S | sec_cm_leaf_fsm_sparse | rstmgr_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_sw_rst_config_regwen | rstmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_dump_ctrl_config_regwen | rstmgr_csr_rw | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 175 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rstmgr_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 0 | 620 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 8 | 8 | 0 | 0.00 |
| V2S | 5 | 5 | 0 | 0.00 |
| V3 | 1 | 0 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 622 failures:
0.rstmgr_smoke.67173139610321015834336244801859889663556196558421475022252040945829081185419
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_smoke/latest/run.log
1.rstmgr_smoke.113371597827182348209487638245006284551467411954147345327025799580610779008809
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_smoke/latest/run.log
... and 48 more failures.
0.rstmgr_por_stretcher.94569538645858626732133686032793126067975590473100243099802685025964360230059
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest/run.log
1.rstmgr_por_stretcher.66670453524498807646992742654071451181356336350457757492494388301578330212814
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest/run.log
... and 48 more failures.
0.rstmgr_reset.113549616489463361956612199373246893218251394539059770859304968602226922830432
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_reset/latest/run.log
1.rstmgr_reset.65084840856351089588383064122696233223221976278929991261021349705906896289567
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_reset/latest/run.log
... and 48 more failures.
0.rstmgr_sw_rst_reset_race.16969335259929653700422854553119177258187399594610030938837577612149847291302
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest/run.log
1.rstmgr_sw_rst_reset_race.62070257263726714871587683049408288848999223824597697406231080419445771239372
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest/run.log
... and 48 more failures.
0.rstmgr_sw_rst.28502058388087444295072113059307284809491970366812232739980017920999420283586
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest/run.log
1.rstmgr_sw_rst.51915460850118710728764458092233185564119976905303645423983249849946601532954
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.