RSTMGR Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	2.470s	255.859us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.290s	112.695us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	1.140s	67.204us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	4.180s	820.797us	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.860s	160.242us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.730s	205.905us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	1.140s	67.204us	20	20	100.00
		rstmgr_csr_aliasing	1.860s	160.242us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.740s	214.483us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	4.210s	534.824us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	2.530s	284.082us	50	50	100.00
V2	reset_info	rstmgr_reset	12.340s	2.109ms	50	50	100.00
V2	cpu_info	rstmgr_reset	12.340s	2.109ms	50	50	100.00
V2	alert_info	rstmgr_reset	12.340s	2.109ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	12.340s	2.109ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	52.490s	16.642ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	1.320s	77.657us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	2.910s	211.818us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	2.910s	211.818us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.290s	112.695us	5	5	100.00
		rstmgr_csr_rw	1.140s	67.204us	20	20	100.00
		rstmgr_csr_aliasing	1.860s	160.242us	5	5	100.00
		rstmgr_same_csr_outstanding	1.470s	277.536us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.290s	112.695us	5	5	100.00
		rstmgr_csr_rw	1.140s	67.204us	20	20	100.00
		rstmgr_csr_aliasing	1.860s	160.242us	5	5	100.00
		rstmgr_same_csr_outstanding	1.470s	277.536us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	59.730s	26.368ms	5	5	100.00
		rstmgr_tl_intg_err	5.750s	2.448ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	59.730s	26.368ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	59.730s	26.368ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	5.750s	2.448ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.870s	185.873us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	12.680s	2.168ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.960s	243.660us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	59.730s	26.368ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	1.140s	67.204us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	1.140s	67.204us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.10.16_00.42.43
• 2024.10.13_03.44.45
• 2024.10.10_10.21.07
• 2024.10.04_00.47.57
• 2024.09.25_11.07.04