RSTMGR Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 2.310s 254.248us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.550s 147.564us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.380s 91.791us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 15.850s 2.287ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 3.430s 353.358us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.450s 178.566us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.380s 91.791us 20 20 100.00
rstmgr_csr_aliasing 3.430s 353.358us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.670s 225.040us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.470s 430.544us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 2.330s 273.196us 50 50 100.00
V2 reset_info rstmgr_reset 11.160s 1.968ms 50 50 100.00
V2 cpu_info rstmgr_reset 11.160s 1.968ms 50 50 100.00
V2 alert_info rstmgr_reset 11.160s 1.968ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 11.160s 1.968ms 50 50 100.00
V2 stress_all rstmgr_stress_all 46.040s 14.488ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.750s 368.035us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 4.210s 410.118us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 4.210s 410.118us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.550s 147.564us 5 5 100.00
rstmgr_csr_rw 1.380s 91.791us 20 20 100.00
rstmgr_csr_aliasing 3.430s 353.358us 5 5 100.00
rstmgr_same_csr_outstanding 2.230s 215.205us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.550s 147.564us 5 5 100.00
rstmgr_csr_rw 1.380s 91.791us 20 20 100.00
rstmgr_csr_aliasing 3.430s 353.358us 5 5 100.00
rstmgr_same_csr_outstanding 2.230s 215.205us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 28.880s 16.682ms 5 5 100.00
rstmgr_tl_intg_err 5.340s 1.170ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 28.880s 16.682ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 28.880s 16.682ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 5.340s 1.170ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.890s 179.023us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 11.420s 1.967ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 2.160s 301.530us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 28.880s 16.682ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.380s 91.791us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.380s 91.791us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Past Results