Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	598706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

359598

1

T1

1132

T3

1137

T4

127

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	510147	1			T1	1753		T3	1500		T4	186
values[0x0]	224358	1			T1	615		T3	855		T4	108
values[0x1]	223799	1			T1	653		T3	845		T4	85

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	502012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

456292

1

T1

1458

T3

1456

T4

157

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3793	1			T3	44		T5	7		T10	23
valid_sources[0x01]	3330	1			T4	5		T5	7		T10	3
valid_sources[0x02]	6574	1			T5	12		T10	32		T13	85
valid_sources[0x03]	2985	1			T5	5		T10	50		T13	65
valid_sources[0x04]	4773	1			T4	13		T13	91		T23	8
valid_sources[0x05]	4021	1			T3	44		T5	4		T10	21
valid_sources[0x06]	3494	1			T5	3		T10	1		T11	2
valid_sources[0x07]	3343	1			T5	6		T10	22		T11	3
valid_sources[0x08]	3111	1			T5	1		T10	40		T11	1
valid_sources[0x09]	4500	1			T1	113		T5	1		T10	16
valid_sources[0x0a]	6521	1			T4	9		T5	4		T10	19
valid_sources[0x0b]	3841	1			T5	2		T10	10		T11	1
valid_sources[0x0c]	3283	1			T1	100		T4	10		T5	3
valid_sources[0x0d]	3784	1			T3	2		T4	1		T5	4
valid_sources[0x0e]	2956	1			T5	8		T10	15		T13	59
valid_sources[0x0f]	3174	1			T5	6		T10	7		T11	2
valid_sources[0x10]	3646	1			T3	28		T5	2		T10	9
valid_sources[0x11]	3513	1			T4	19		T5	2		T10	18
valid_sources[0x12]	2884	1			T5	4		T11	2		T13	63
valid_sources[0x13]	3864	1			T5	6		T10	11		T13	74
valid_sources[0x14]	2843	1			T5	2		T10	7		T11	2
valid_sources[0x15]	3025	1			T5	7		T10	3		T11	1
valid_sources[0x16]	3274	1			T5	4		T10	12		T13	58
valid_sources[0x17]	3413	1			T4	2		T5	2		T10	13
valid_sources[0x18]	3218	1			T4	2		T5	2		T7	212
valid_sources[0x19]	3859	1			T5	7		T10	6		T11	2
valid_sources[0x1a]	3414	1			T5	2		T10	1		T11	1
valid_sources[0x1b]	3709	1			T5	7		T10	8		T13	81
valid_sources[0x1c]	3638	1			T3	106		T5	9		T10	2
valid_sources[0x1d]	3387	1			T5	2		T10	17		T11	3
valid_sources[0x1e]	3545	1			T5	5		T10	5		T13	70
valid_sources[0x1f]	3956	1			T5	2		T10	5		T13	78
valid_sources[0x20]	5418	1			T1	154		T5	2		T10	10
valid_sources[0x21]	3851	1			T5	1		T10	28		T13	73
valid_sources[0x22]	3130	1			T3	3		T5	3		T10	30
valid_sources[0x23]	3804	1			T5	3		T10	29		T13	69
valid_sources[0x24]	3550	1			T5	3		T10	5		T11	1
valid_sources[0x25]	3965	1			T5	4		T10	16		T11	1
valid_sources[0x26]	3154	1			T5	3		T10	6		T13	63
valid_sources[0x27]	3213	1			T5	4		T10	20		T13	79
valid_sources[0x28]	2892	1			T5	1		T10	5		T11	1
valid_sources[0x29]	3340	1			T4	1		T5	6		T11	1
valid_sources[0x2a]	4284	1			T1	155		T4	6		T5	2
valid_sources[0x2b]	3703	1			T1	70		T3	73		T5	3
valid_sources[0x2c]	4015	1			T4	3		T5	1		T10	10
valid_sources[0x2d]	2876	1			T5	3		T10	36		T11	1
valid_sources[0x2e]	2857	1			T1	152		T5	3		T10	11
valid_sources[0x2f]	2566	1			T5	6		T11	1		T13	82
valid_sources[0x30]	3434	1			T3	162		T5	4		T10	10
valid_sources[0x31]	3506	1			T3	59		T5	3		T10	14
valid_sources[0x32]	4721	1			T4	3		T5	1		T10	3
valid_sources[0x33]	2819	1			T5	2		T10	1		T11	1
valid_sources[0x34]	6394	1			T3	75		T5	5		T9	3200
valid_sources[0x35]	3951	1			T5	4		T10	20		T13	79
valid_sources[0x36]	3355	1			T5	2		T10	9		T13	78
valid_sources[0x37]	3466	1			T5	9		T10	9		T13	62
valid_sources[0x38]	3327	1			T3	17		T5	3		T10	4
valid_sources[0x39]	7085	1			T5	2		T10	22		T13	68
valid_sources[0x3a]	3818	1			T4	1		T5	3		T13	86
valid_sources[0x3b]	3455	1			T1	241		T5	1		T10	11
valid_sources[0x3c]	3099	1			T3	104		T5	5		T10	4
valid_sources[0x3d]	3831	1			T3	119		T4	1		T5	3
valid_sources[0x3e]	3028	1			T4	8		T5	1		T13	73
valid_sources[0x3f]	3606	1			T3	5		T5	7		T10	16
valid_sources[0x40]	3540	1			T5	3		T10	5		T13	65
valid_sources[0x41]	3052	1			T3	7		T5	7		T10	7
valid_sources[0x42]	4182	1			T3	20		T5	7		T10	21
valid_sources[0x43]	3034	1			T3	6		T5	2		T10	2
valid_sources[0x44]	7249	1			T5	4		T10	18		T13	75
valid_sources[0x45]	3790	1			T5	6		T10	8		T11	1
valid_sources[0x46]	4387	1			T1	112		T4	2		T5	6
valid_sources[0x47]	2959	1			T3	132		T5	5		T11	1
valid_sources[0x48]	3456	1			T3	21		T5	5		T10	25
valid_sources[0x49]	3626	1			T5	4		T10	9		T11	4
valid_sources[0x4a]	3157	1			T5	6		T10	20		T11	1
valid_sources[0x4b]	4404	1			T5	3		T10	29		T13	62
valid_sources[0x4c]	4238	1			T3	10		T4	11		T5	5
valid_sources[0x4d]	3333	1			T5	2		T10	24		T13	57
valid_sources[0x4e]	3686	1			T3	86		T4	4		T5	8
valid_sources[0x4f]	3645	1			T3	100		T5	5		T10	10
valid_sources[0x50]	3501	1			T3	43		T5	5		T10	14
valid_sources[0x51]	4721	1			T5	5		T10	10		T11	1
valid_sources[0x52]	4059	1			T5	6		T10	9		T13	86
valid_sources[0x53]	4374	1			T5	3		T10	18		T11	1
valid_sources[0x54]	2819	1			T3	28		T4	4		T5	6
valid_sources[0x55]	3114	1			T5	2		T11	1		T13	71
valid_sources[0x56]	4002	1			T3	175		T4	1		T5	4
valid_sources[0x57]	3556	1			T5	5		T10	5		T11	1
valid_sources[0x58]	4104	1			T5	3		T10	26		T11	1
valid_sources[0x59]	4732	1			T3	71		T5	6		T10	2
valid_sources[0x5a]	3092	1			T4	7		T5	4		T10	9
valid_sources[0x5b]	3232	1			T4	2		T5	1		T10	13
valid_sources[0x5c]	3358	1			T3	26		T4	2		T5	5
valid_sources[0x5d]	7393	1			T1	70		T5	5		T10	37
valid_sources[0x5e]	7087	1			T3	4		T5	6		T10	3
valid_sources[0x5f]	3501	1			T5	1		T10	4		T11	3
valid_sources[0x60]	3526	1			T5	3		T10	12		T13	82
valid_sources[0x61]	3251	1			T5	1		T10	5		T11	1
valid_sources[0x62]	3533	1			T10	15		T11	2		T13	62
valid_sources[0x63]	3158	1			T4	1		T5	6		T11	3
valid_sources[0x64]	2874	1			T4	6		T5	3		T10	9
valid_sources[0x65]	4574	1			T5	9		T10	24		T11	1
valid_sources[0x66]	3383	1			T5	1		T10	16		T13	80
valid_sources[0x67]	3177	1			T5	2		T10	7		T13	89
valid_sources[0x68]	4298	1			T5	4		T10	24		T13	61
valid_sources[0x69]	3144	1			T5	3		T10	2		T13	60
valid_sources[0x6a]	4562	1			T4	10		T5	5		T10	8
valid_sources[0x6b]	5084	1			T4	3		T5	5		T10	14
valid_sources[0x6c]	3221	1			T3	35		T4	1		T5	12
valid_sources[0x6d]	3313	1			T4	6		T5	2		T10	1
valid_sources[0x6e]	3705	1			T4	12		T5	6		T10	8
valid_sources[0x6f]	3095	1			T5	3		T10	14		T13	61
valid_sources[0x70]	3592	1			T5	4		T10	6		T11	1
valid_sources[0x71]	3813	1			T3	1		T4	5		T5	4
valid_sources[0x72]	3607	1			T4	6		T5	3		T10	14
valid_sources[0x73]	3157	1			T4	1		T5	7		T10	10
valid_sources[0x74]	3857	1			T3	28		T4	11		T5	2
valid_sources[0x75]	4187	1			T1	155		T5	1		T10	3
valid_sources[0x76]	3442	1			T5	2		T10	15		T13	71
valid_sources[0x77]	4258	1			T5	6		T10	15		T11	1
valid_sources[0x78]	4753	1			T5	1		T10	17		T11	1
valid_sources[0x79]	3794	1			T5	3		T10	3		T13	73
valid_sources[0x7a]	3349	1			T5	2		T10	14		T13	102
valid_sources[0x7b]	3722	1			T5	8		T10	15		T13	62
valid_sources[0x7c]	3275	1			T1	156		T5	8		T10	18
valid_sources[0x7d]	3181	1			T5	3		T10	25		T11	1
valid_sources[0x7e]	3760	1			T5	4		T10	4		T13	77
valid_sources[0x7f]	3482	1			T5	4		T10	8		T11	2
valid_sources[0x80]	3424	1			T5	3		T11	1		T13	77

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

239295

1

T1

810

T3

669

T4

82

values[0x0]

all_enables

biggest_size

78469

1

T1

214

T3

300

T4

35

values[0x1]

all_enables

biggest_size

41834

1

T1

108

T3

168

T4

10