Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

12 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_rstmgr_reg_block.alert_info_ctrl.en	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.alert_info_ctrl.index	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.cpu_info_ctrl.en	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.cpu_info_ctrl.index	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_0.val	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_1.val	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_2.val	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_3.val	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_4.val	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_5.val	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_6.val	100.00	1	100	1	64	64
lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_7.val	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.alert_info_ctrl.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.alert_info_ctrl.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.alert_info_ctrl.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.alert_info_ctrl.index

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.alert_info_ctrl.index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.alert_info_ctrl.index

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.cpu_info_ctrl.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.cpu_info_ctrl.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.cpu_info_ctrl.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.cpu_info_ctrl.index

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.cpu_info_ctrl.index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.cpu_info_ctrl.index

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_0.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_0.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_0.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_1.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_1.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_1.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_2.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_2.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_2.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_3.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_3.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_3.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_4.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_4.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_4.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_5.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_5.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_5.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_6.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_6.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_6.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_7.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_7.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_rstmgr_reg_block.sw_rst_ctrl_n_7.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244

1

T51

1

T107

64

T86

2

auto[1]

569

1

T4

1

T5

1

T47

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

243

1

T50

3

T51

1

T107

56

auto[1]

4032

1

T1

22

T10

16

T13

89

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301

1

T50

2

T51

1

T58

2

auto[1]

488

1

T4

1

T5

1

T47

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329

1

T50

2

T51

1

T124

10

auto[1]

3936

1

T1

22

T10

16

T13

92

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T5

32

T48

32

T49

32

auto[1]

3327

1

T5

27

T13

82

T26

70

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1454

1

T5

28

T48

28

T49

28

auto[1]

3494

1

T4

2

T5

32

T13

68

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1278

1

T4

3

T5

24

T48

24

auto[1]

3600

1

T5

35

T13

81

T26

65

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T4

3

T5

20

T48

20

auto[1]

3828

1

T5

40

T13

82

T26

61

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

881

1

T5

16

T48

16

T49

16

auto[1]

4072

1

T4

2

T5

35

T13

82

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678

1

T5

12

T47

3

T48

12

auto[1]

4221

1

T4

2

T5

47

T13

76

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

454

1

T4

3

T5

8

T47

3

auto[1]

4452

1

T5

52

T13

78

T26

64

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266

1

T5

4

T47

3

T48

4

auto[1]

4661

1

T5

53

T13

81

T26

69