Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T26
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12593603	13715	0	0
gen_assertions[0].RstEnOn_A	12593603	1038	0	0
gen_assertions[0].RstNOff_A	12593603	13715	0	0
gen_assertions[0].RstNOn_A	12593603	1038	0	0
gen_assertions[1].RstEnOff_A	50373514	12498	0	0
gen_assertions[1].RstEnOn_A	50373514	1026	0	0
gen_assertions[1].RstNOff_A	50373514	12498	0	0
gen_assertions[1].RstNOn_A	50373514	1026	0	0
gen_assertions[2].RstEnOff_A	25187606	12526	0	0
gen_assertions[2].RstEnOn_A	25187606	1021	0	0
gen_assertions[2].RstNOff_A	25187606	12526	0	0
gen_assertions[2].RstNOn_A	25187606	1021	0	0
gen_assertions[3].RstEnOff_A	25187522	12558	0	0
gen_assertions[3].RstEnOn_A	25187522	1041	0	0
gen_assertions[3].RstNOff_A	25187522	12558	0	0
gen_assertions[3].RstNOn_A	25187522	1041	0	0
gen_assertions[4].RstEnOff_A	1590526	21062	0	0
gen_assertions[4].RstEnOn_A	1590526	1099	0	0
gen_assertions[4].RstNOff_A	1590526	21062	0	0
gen_assertions[4].RstNOn_A	1590526	1099	0	0
gen_assertions[5].RstEnOff_A	12593603	13954	0	0
gen_assertions[5].RstEnOn_A	12593603	1135	0	0
gen_assertions[5].RstNOff_A	12593603	13954	0	0
gen_assertions[5].RstNOn_A	12593603	1135	0	0
gen_assertions[6].RstEnOff_A	12593603	14018	0	0
gen_assertions[6].RstEnOn_A	12593603	1205	0	0
gen_assertions[6].RstNOff_A	12593603	14018	0	0
gen_assertions[6].RstNOn_A	12593603	1205	0	0
gen_assertions[7].RstEnOff_A	12593603	14053	0	0
gen_assertions[7].RstEnOn_A	12593603	1234	0	0
gen_assertions[7].RstNOff_A	12593603	14053	0	0
gen_assertions[7].RstNOn_A	12593603	1234	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	13715	0	0
T1	40729	33	0	0
T2	5836	0	0	0
T3	29291	75	0	0
T4	2915	4	0	0
T5	3431	8	0	0
T6	5827	0	0	0
T7	2502	4	0	0
T8	5799	0	0	0
T9	56504	75	0	0
T10	34747	39	0	0
T11	0	4	0	0
T13	0	255	0	0
T23	0	34	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	1038	0	0
T5	3431	8	0	0
T6	5827	0	0	0
T7	2502	0	0	0
T8	5799	0	0	0
T9	56504	0	0	0
T10	34747	0	0	0
T11	3662	0	0	0
T12	4105	0	0	0
T13	298125	21	0	0
T22	5843	0	0	0
T26	0	17	0	0
T43	0	11	0	0
T47	0	1	0	0
T48	0	9	0	0
T49	0	7	0	0
T76	0	35	0	0
T77	0	26	0	0
T78	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	13715	0	0
T1	40729	33	0	0
T2	5836	0	0	0
T3	29291	75	0	0
T4	2915	4	0	0
T5	3431	8	0	0
T6	5827	0	0	0
T7	2502	4	0	0
T8	5799	0	0	0
T9	56504	75	0	0
T10	34747	39	0	0
T11	0	4	0	0
T13	0	255	0	0
T23	0	34	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	1038	0	0
T5	3431	8	0	0
T6	5827	0	0	0
T7	2502	0	0	0
T8	5799	0	0	0
T9	56504	0	0	0
T10	34747	0	0	0
T11	3662	0	0	0
T12	4105	0	0	0
T13	298125	21	0	0
T22	5843	0	0	0
T26	0	17	0	0
T43	0	11	0	0
T47	0	1	0	0
T48	0	9	0	0
T49	0	7	0	0
T76	0	35	0	0
T77	0	26	0	0
T78	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50373514	12498	0	0
T1	162896	30	0	0
T2	23353	0	0	0
T3	117125	64	0	0
T4	11654	2	0	0
T5	13725	8	0	0
T6	23332	0	0	0
T7	10013	3	0	0
T8	23198	0	0	0
T9	225997	65	0	0
T10	138972	32	0	0
T11	0	4	0	0
T13	0	234	0	0
T23	0	32	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50373514	1026	0	0
T4	11654	1	0	0
T5	13725	8	0	0
T6	23332	0	0	0
T7	10013	0	0	0
T8	23198	0	0	0
T9	225997	0	0	0
T10	138972	0	0	0
T11	14656	0	0	0
T12	16422	0	0	0
T13	0	23	0	0
T22	23345	0	0	0
T26	0	14	0	0
T43	0	11	0	0
T47	0	1	0	0
T48	0	6	0	0
T49	0	7	0	0
T76	0	41	0	0
T77	0	23	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50373514	12498	0	0
T1	162896	30	0	0
T2	23353	0	0	0
T3	117125	64	0	0
T4	11654	2	0	0
T5	13725	8	0	0
T6	23332	0	0	0
T7	10013	3	0	0
T8	23198	0	0	0
T9	225997	65	0	0
T10	138972	32	0	0
T11	0	4	0	0
T13	0	234	0	0
T23	0	32	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50373514	1026	0	0
T4	11654	1	0	0
T5	13725	8	0	0
T6	23332	0	0	0
T7	10013	0	0	0
T8	23198	0	0	0
T9	225997	0	0	0
T10	138972	0	0	0
T11	14656	0	0	0
T12	16422	0	0	0
T13	0	23	0	0
T22	23345	0	0	0
T26	0	14	0	0
T43	0	11	0	0
T47	0	1	0	0
T48	0	6	0	0
T49	0	7	0	0
T76	0	41	0	0
T77	0	23	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187606	12526	0	0
T1	81454	30	0	0
T2	11672	0	0	0
T3	58576	64	0	0
T4	5825	1	0	0
T5	6862	10	0	0
T6	11660	0	0	0
T7	5005	3	0	0
T8	11599	0	0	0
T9	113000	65	0	0
T10	69481	32	0	0
T11	0	4	0	0
T13	0	232	0	0
T23	0	32	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187606	1021	0	0
T5	6862	10	0	0
T6	11660	0	0	0
T7	5005	0	0	0
T8	11599	0	0	0
T9	113000	0	0	0
T10	69481	0	0	0
T11	7328	0	0	0
T12	8211	0	0	0
T13	596263	21	0	0
T22	11677	0	0	0
T26	0	19	0	0
T43	0	11	0	0
T48	0	10	0	0
T49	0	7	0	0
T71	0	30	0	0
T72	0	4	0	0
T76	0	42	0	0
T77	0	26	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187606	12526	0	0
T1	81454	30	0	0
T2	11672	0	0	0
T3	58576	64	0	0
T4	5825	1	0	0
T5	6862	10	0	0
T6	11660	0	0	0
T7	5005	3	0	0
T8	11599	0	0	0
T9	113000	65	0	0
T10	69481	32	0	0
T11	0	4	0	0
T13	0	232	0	0
T23	0	32	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187606	1021	0	0
T5	6862	10	0	0
T6	11660	0	0	0
T7	5005	0	0	0
T8	11599	0	0	0
T9	113000	0	0	0
T10	69481	0	0	0
T11	7328	0	0	0
T12	8211	0	0	0
T13	596263	21	0	0
T22	11677	0	0	0
T26	0	19	0	0
T43	0	11	0	0
T48	0	10	0	0
T49	0	7	0	0
T71	0	30	0	0
T72	0	4	0	0
T76	0	42	0	0
T77	0	26	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187522	12558	0	0
T1	81465	30	0	0
T2	11676	0	0	0
T3	58571	64	0	0
T4	5827	1	0	0
T5	6862	10	0	0
T6	11662	0	0	0
T7	5006	3	0	0
T8	11599	0	0	0
T9	113014	65	0	0
T10	69487	32	0	0
T11	0	4	0	0
T13	0	235	0	0
T23	0	32	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187522	1041	0	0
T5	6862	10	0	0
T6	11662	0	0	0
T7	5006	0	0	0
T8	11599	0	0	0
T9	113014	0	0	0
T10	69487	0	0	0
T11	7327	0	0	0
T12	8210	0	0	0
T13	596243	26	0	0
T22	11679	0	0	0
T26	0	19	0	0
T43	0	15	0	0
T47	0	1	0	0
T48	0	9	0	0
T49	0	9	0	0
T71	0	33	0	0
T76	0	37	0	0
T77	0	23	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187522	12558	0	0
T1	81465	30	0	0
T2	11676	0	0	0
T3	58571	64	0	0
T4	5827	1	0	0
T5	6862	10	0	0
T6	11662	0	0	0
T7	5006	3	0	0
T8	11599	0	0	0
T9	113014	65	0	0
T10	69487	32	0	0
T11	0	4	0	0
T13	0	235	0	0
T23	0	32	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187522	1041	0	0
T5	6862	10	0	0
T6	11662	0	0	0
T7	5006	0	0	0
T8	11599	0	0	0
T9	113014	0	0	0
T10	69487	0	0	0
T11	7327	0	0	0
T12	8210	0	0	0
T13	596243	26	0	0
T22	11679	0	0	0
T26	0	19	0	0
T43	0	15	0	0
T47	0	1	0	0
T48	0	9	0	0
T49	0	9	0	0
T71	0	33	0	0
T76	0	37	0	0
T77	0	23	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	21062	0	0
T1	5170	57	0	0
T2	731	3	0	0
T3	3676	76	0	0
T4	362	7	0	0
T5	427	10	0	0
T6	731	3	0	0
T7	312	5	0	0
T8	723	2	0	0
T9	7077	97	0	0
T10	4459	56	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	1099	0	0
T4	362	1	0	0
T5	427	9	0	0
T6	731	0	0	0
T7	312	0	0	0
T8	723	0	0	0
T9	7077	0	0	0
T10	4459	0	0	0
T11	458	0	0	0
T12	511	0	0	0
T13	0	23	0	0
T22	732	0	0	0
T26	0	19	0	0
T43	0	14	0	0
T47	0	1	0	0
T48	0	11	0	0
T49	0	7	0	0
T76	0	41	0	0
T77	0	22	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	21062	0	0
T1	5170	57	0	0
T2	731	3	0	0
T3	3676	76	0	0
T4	362	7	0	0
T5	427	10	0	0
T6	731	3	0	0
T7	312	5	0	0
T8	723	2	0	0
T9	7077	97	0	0
T10	4459	56	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	1099	0	0
T4	362	1	0	0
T5	427	9	0	0
T6	731	0	0	0
T7	312	0	0	0
T8	723	0	0	0
T9	7077	0	0	0
T10	4459	0	0	0
T11	458	0	0	0
T12	511	0	0	0
T13	0	23	0	0
T22	732	0	0	0
T26	0	19	0	0
T43	0	14	0	0
T47	0	1	0	0
T48	0	11	0	0
T49	0	7	0	0
T76	0	41	0	0
T77	0	22	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	13954	0	0
T1	40729	33	0	0
T2	5836	0	0	0
T3	29291	75	0	0
T4	2915	5	0	0
T5	3431	13	0	0
T6	5827	0	0	0
T7	2502	4	0	0
T8	5799	0	0	0
T9	56504	75	0	0
T10	34747	39	0	0
T11	0	4	0	0
T13	0	259	0	0
T23	0	34	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	1135	0	0
T4	2915	1	0	0
T5	3431	13	0	0
T6	5827	0	0	0
T7	2502	0	0	0
T8	5799	0	0	0
T9	56504	0	0	0
T10	34747	0	0	0
T11	3662	0	0	0
T12	4105	0	0	0
T13	0	26	0	0
T22	5843	0	0	0
T26	0	19	0	0
T43	0	10	0	0
T48	0	12	0	0
T49	0	10	0	0
T71	0	31	0	0
T76	0	40	0	0
T77	0	20	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	13954	0	0
T1	40729	33	0	0
T2	5836	0	0	0
T3	29291	75	0	0
T4	2915	5	0	0
T5	3431	13	0	0
T6	5827	0	0	0
T7	2502	4	0	0
T8	5799	0	0	0
T9	56504	75	0	0
T10	34747	39	0	0
T11	0	4	0	0
T13	0	259	0	0
T23	0	34	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	1135	0	0
T4	2915	1	0	0
T5	3431	13	0	0
T6	5827	0	0	0
T7	2502	0	0	0
T8	5799	0	0	0
T9	56504	0	0	0
T10	34747	0	0	0
T11	3662	0	0	0
T12	4105	0	0	0
T13	0	26	0	0
T22	5843	0	0	0
T26	0	19	0	0
T43	0	10	0	0
T48	0	12	0	0
T49	0	10	0	0
T71	0	31	0	0
T76	0	40	0	0
T77	0	20	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	14018	0	0
T1	40729	33	0	0
T2	5836	0	0	0
T3	29291	75	0	0
T4	2915	4	0	0
T5	3431	12	0	0
T6	5827	0	0	0
T7	2502	4	0	0
T8	5799	0	0	0
T9	56504	75	0	0
T10	34747	39	0	0
T11	0	4	0	0
T13	0	253	0	0
T23	0	34	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	1205	0	0
T5	3431	12	0	0
T6	5827	0	0	0
T7	2502	0	0	0
T8	5799	0	0	0
T9	56504	0	0	0
T10	34747	0	0	0
T11	3662	0	0	0
T12	4105	0	0	0
T13	298125	17	0	0
T22	5843	0	0	0
T26	0	20	0	0
T43	0	13	0	0
T48	0	13	0	0
T49	0	12	0	0
T71	0	27	0	0
T76	0	34	0	0
T77	0	24	0	0
T79	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	14018	0	0
T1	40729	33	0	0
T2	5836	0	0	0
T3	29291	75	0	0
T4	2915	4	0	0
T5	3431	12	0	0
T6	5827	0	0	0
T7	2502	4	0	0
T8	5799	0	0	0
T9	56504	75	0	0
T10	34747	39	0	0
T11	0	4	0	0
T13	0	253	0	0
T23	0	34	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	1205	0	0
T5	3431	12	0	0
T6	5827	0	0	0
T7	2502	0	0	0
T8	5799	0	0	0
T9	56504	0	0	0
T10	34747	0	0	0
T11	3662	0	0	0
T12	4105	0	0	0
T13	298125	17	0	0
T22	5843	0	0	0
T26	0	20	0	0
T43	0	13	0	0
T48	0	13	0	0
T49	0	12	0	0
T71	0	27	0	0
T76	0	34	0	0
T77	0	24	0	0
T79	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	14053	0	0
T1	40729	33	0	0
T2	5836	0	0	0
T3	29291	75	0	0
T4	2915	4	0	0
T5	3431	14	0	0
T6	5827	0	0	0
T7	2502	4	0	0
T8	5799	0	0	0
T9	56504	75	0	0
T10	34747	39	0	0
T11	0	4	0	0
T13	0	255	0	0
T23	0	34	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	1234	0	0
T5	3431	14	0	0
T6	5827	0	0	0
T7	2502	0	0	0
T8	5799	0	0	0
T9	56504	0	0	0
T10	34747	0	0	0
T11	3662	0	0	0
T12	4105	0	0	0
T13	298125	21	0	0
T22	5843	0	0	0
T26	0	18	0	0
T43	0	13	0	0
T48	0	13	0	0
T49	0	10	0	0
T71	0	32	0	0
T72	0	8	0	0
T76	0	38	0	0
T77	0	23	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	14053	0	0
T1	40729	33	0	0
T2	5836	0	0	0
T3	29291	75	0	0
T4	2915	4	0	0
T5	3431	14	0	0
T6	5827	0	0	0
T7	2502	4	0	0
T8	5799	0	0	0
T9	56504	75	0	0
T10	34747	39	0	0
T11	0	4	0	0
T13	0	255	0	0
T23	0	34	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	1234	0	0
T5	3431	14	0	0
T6	5827	0	0	0
T7	2502	0	0	0
T8	5799	0	0	0
T9	56504	0	0	0
T10	34747	0	0	0
T11	3662	0	0	0
T12	4105	0	0	0
T13	298125	21	0	0
T22	5843	0	0	0
T26	0	18	0	0
T43	0	13	0	0
T48	0	13	0	0
T49	0	10	0	0
T71	0	32	0	0
T72	0	8	0	0
T76	0	38	0	0
T77	0	23	0	0