Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 87.50 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_err_code_reg_intg_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_reset_consistency_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_err_code_fsm_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_reset_req.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_reset_info_por.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_reset_info_low_power_exit.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_reset_info_sw_reset.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_reset_info_hw_req.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_alert_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cpu_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_0.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_1.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_2.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_3.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_4.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_5.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_6.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_7.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 + DW=1,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_req.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=5,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_info_por.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_info_low_power_exit.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_info_sw_reset.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reset_info_hw_req.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_alert_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cpu_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_7.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_reg_intg_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_reset_consistency_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_err_code_fsm_err.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 0 1
51 unreachable
52 unreachable
53 unreachable

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_info_por.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_info_low_power_exit.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_info_sw_reset.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T2,T3 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=5,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_info_hw_req.wr_en_data_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_reset_req.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_alert_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cpu_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_sw_rst_regwen_7.wr_en_data_arb

TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T5,T47 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT5,T48,T49
10CoveredT5,T48,T49
11CoveredT1,T2,T3 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T47
Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%