Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11995777	8434	0	0
alert_regwen_rd_A	11995777	5416	0	0
cpu_regwen_rd_A	11995777	5488	0	0
sw_rst_ctrl_n_0_rd_A	11995777	9887	0	0
sw_rst_ctrl_n_1_rd_A	11995777	9574	0	0
sw_rst_ctrl_n_2_rd_A	11995777	9698	0	0
sw_rst_ctrl_n_3_rd_A	11995777	9735	0	0
sw_rst_ctrl_n_4_rd_A	11995777	9817	0	0
sw_rst_ctrl_n_5_rd_A	11995777	9728	0	0
sw_rst_ctrl_n_6_rd_A	11995777	9782	0	0
sw_rst_ctrl_n_7_rd_A	11995777	9678	0	0
sw_rst_regwen_0_rd_A	11995777	5915	0	0
sw_rst_regwen_1_rd_A	11995777	5874	0	0
sw_rst_regwen_2_rd_A	11995777	5944	0	0
sw_rst_regwen_3_rd_A	11995777	5863	0	0
sw_rst_regwen_4_rd_A	11995777	5792	0	0
sw_rst_regwen_5_rd_A	11995777	5947	0	0
sw_rst_regwen_6_rd_A	11995777	5866	0	0
sw_rst_regwen_7_rd_A	11995777	5953	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	8434	0	0
T50	11380	2	0	0
T54	8706	408	0	0
T55	2888	1	0	0
T57	2681	262	0	0
T58	18698	3	0	0
T59	3984	29	0	0
T85	1925	0	0	0
T86	11155	3	0	0
T88	0	3	0	0
T117	2733	4	0	0
T118	4131	9	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5416	0	0
T13	268012	340	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	40	0	0
T47	5879	0	0	0
T49	11531	0	0	0
T50	0	32	0	0
T54	0	20	0	0
T76	118496	96	0	0
T77	91374	0	0	0
T96	0	197	0	0
T99	0	100	0	0
T100	0	94	0	0
T119	0	43	0	0
T120	0	32	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5488	0	0
T13	268012	336	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	65	0	0
T47	5879	0	0	0
T49	11531	0	0	0
T50	0	53	0	0
T54	0	11	0	0
T76	118496	107	0	0
T77	91374	0	0	0
T96	0	210	0	0
T99	0	80	0	0
T100	0	81	0	0
T119	0	42	0	0
T120	0	19	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	9887	0	0
T13	268012	728	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	82	0	0
T47	5879	14	0	0
T48	12503	202	0	0
T49	11531	190	0	0
T72	0	100	0	0
T76	118496	402	0	0
T96	0	304	0	0
T100	0	82	0	0
T119	0	43	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	9574	0	0
T13	268012	628	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	43	0	0
T47	5879	19	0	0
T48	12503	188	0	0
T49	11531	191	0	0
T72	0	115	0	0
T76	118496	372	0	0
T96	0	374	0	0
T100	0	106	0	0
T119	0	42	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	9698	0	0
T13	268012	628	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	90	0	0
T47	5879	6	0	0
T48	12503	216	0	0
T49	11531	165	0	0
T72	0	78	0	0
T76	118496	388	0	0
T96	0	342	0	0
T100	0	94	0	0
T119	0	49	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	9735	0	0
T13	268012	660	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	58	0	0
T47	5879	15	0	0
T48	12503	224	0	0
T49	11531	165	0	0
T72	0	99	0	0
T76	118496	328	0	0
T96	0	336	0	0
T100	0	78	0	0
T119	0	43	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	9817	0	0
T13	268012	738	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	41	0	0
T47	5879	23	0	0
T48	12503	201	0	0
T49	11531	171	0	0
T72	0	73	0	0
T76	118496	396	0	0
T96	0	356	0	0
T100	0	101	0	0
T119	0	48	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	9728	0	0
T13	268012	709	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	48	0	0
T47	5879	13	0	0
T48	12503	179	0	0
T49	11531	145	0	0
T72	0	87	0	0
T76	118496	427	0	0
T96	0	382	0	0
T100	0	99	0	0
T119	0	59	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	9782	0	0
T13	268012	675	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	55	0	0
T47	5879	19	0	0
T48	12503	210	0	0
T49	11531	176	0	0
T72	0	34	0	0
T76	118496	366	0	0
T96	0	367	0	0
T100	0	105	0	0
T119	0	35	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	9678	0	0
T13	268012	605	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	57	0	0
T47	5879	7	0	0
T48	12503	242	0	0
T49	11531	154	0	0
T72	0	44	0	0
T76	118496	394	0	0
T96	0	317	0	0
T100	0	85	0	0
T119	0	40	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5915	0	0
T13	268012	388	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	51	0	0
T47	5879	15	0	0
T48	12503	41	0	0
T49	11531	47	0	0
T72	0	23	0	0
T76	118496	79	0	0
T96	0	166	0	0
T100	0	67	0	0
T119	0	36	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5874	0	0
T13	268012	384	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	65	0	0
T47	5879	2	0	0
T48	12503	29	0	0
T49	11531	28	0	0
T72	0	6	0	0
T76	118496	79	0	0
T96	0	193	0	0
T100	0	103	0	0
T119	0	30	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5944	0	0
T13	268012	410	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	45	0	0
T47	5879	4	0	0
T48	12503	28	0	0
T49	11531	30	0	0
T72	0	13	0	0
T76	118496	74	0	0
T96	0	203	0	0
T100	0	81	0	0
T119	0	56	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5863	0	0
T13	268012	335	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	47	0	0
T47	5879	8	0	0
T48	12503	43	0	0
T49	11531	28	0	0
T72	0	10	0	0
T76	118496	93	0	0
T96	0	196	0	0
T100	0	70	0	0
T119	0	43	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5792	0	0
T13	268012	385	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	67	0	0
T47	5879	4	0	0
T48	12503	26	0	0
T49	11531	27	0	0
T72	0	16	0	0
T76	118496	83	0	0
T96	0	192	0	0
T100	0	79	0	0
T119	0	48	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5947	0	0
T13	268012	377	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	33	0	0
T47	5879	1	0	0
T48	12503	15	0	0
T49	11531	35	0	0
T72	0	20	0	0
T76	118496	123	0	0
T96	0	192	0	0
T100	0	66	0	0
T119	0	49	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5866	0	0
T13	268012	390	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	77	0	0
T47	5879	5	0	0
T48	12503	33	0	0
T49	11531	43	0	0
T72	0	17	0	0
T76	118496	74	0	0
T96	0	184	0	0
T100	0	93	0	0
T119	0	60	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11995777	5953	0	0
T13	268012	378	0	0
T23	23818	0	0	0
T24	5112	0	0	0
T25	5494	0	0	0
T26	249962	0	0	0
T42	42972	67	0	0
T47	5879	4	0	0
T48	12503	40	0	0
T49	11531	44	0	0
T72	0	12	0	0
T76	118496	82	0	0
T96	0	206	0	0
T100	0	87	0	0
T119	0	36	0	0