Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T7
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T10,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52474405	8411	0	0
CascadeEffAonToRstPorAboveRise_A	52474405	8411	0	0
CascadeEffAonToRstPorIoAboveFall_A	50373514	8411	0	0
CascadeEffAonToRstPorIoAboveRise_A	50373514	8411	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25187606	8411	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25187606	8411	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12593603	8411	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12593603	8411	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25187522	8411	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25187522	8411	0	0
CascadeLcToLcAboveFall_A	52474405	21265	0	0
CascadeLcToLcAboveRise_A	52474405	21265	0	0
CascadeLcToLcAonAboveFall_A	1590526	21265	0	0
CascadeLcToLcAonAboveRise_A	1590526	21265	0	0
CascadeLcToLcShadowedAboveFall_A	52474405	21265	0	0
CascadeLcToLcShadowedAboveRise_A	52474405	21265	0	0
CascadePorToAonAboveFall_A	1590526	6730	0	0
CascadeSysToSysAboveFall_A	52474405	21265	0	0
CascadeSysToSysAboveRise_A	52474405	21265	0	0
ScanRstToAonRise_A	1590526	194	0	0
StablePorToAonRise_A	1590526	8411	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11214219	21265	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11214219	21265	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11214219	21265	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11214219	21265	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12593603	21265	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12593603	21265	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11214219	21265	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11214219	21265	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11214219	21265	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11214219	21265	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474405	8411	0	0
T1	169706	24	0	0
T2	24327	8	0	0
T3	122045	27	0	0
T4	12139	2	0	0
T5	14298	1	0	0
T6	24297	8	0	0
T7	10433	2	0	0
T8	24165	2	0	0
T9	235428	27	0	0
T10	144775	18	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474405	8411	0	0
T1	169706	24	0	0
T2	24327	8	0	0
T3	122045	27	0	0
T4	12139	2	0	0
T5	14298	1	0	0
T6	24297	8	0	0
T7	10433	2	0	0
T8	24165	2	0	0
T9	235428	27	0	0
T10	144775	18	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50373514	8411	0	0
T1	162896	24	0	0
T2	23353	8	0	0
T3	117125	27	0	0
T4	11654	2	0	0
T5	13725	1	0	0
T6	23332	8	0	0
T7	10013	2	0	0
T8	23198	2	0	0
T9	225997	27	0	0
T10	138972	18	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50373514	8411	0	0
T1	162896	24	0	0
T2	23353	8	0	0
T3	117125	27	0	0
T4	11654	2	0	0
T5	13725	1	0	0
T6	23332	8	0	0
T7	10013	2	0	0
T8	23198	2	0	0
T9	225997	27	0	0
T10	138972	18	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187606	8411	0	0
T1	81454	24	0	0
T2	11672	8	0	0
T3	58576	27	0	0
T4	5825	2	0	0
T5	6862	1	0	0
T6	11660	8	0	0
T7	5005	2	0	0
T8	11599	2	0	0
T9	113000	27	0	0
T10	69481	18	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187606	8411	0	0
T1	81454	24	0	0
T2	11672	8	0	0
T3	58576	27	0	0
T4	5825	2	0	0
T5	6862	1	0	0
T6	11660	8	0	0
T7	5005	2	0	0
T8	11599	2	0	0
T9	113000	27	0	0
T10	69481	18	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	8411	0	0
T1	40729	24	0	0
T2	5836	8	0	0
T3	29291	27	0	0
T4	2915	2	0	0
T5	3431	1	0	0
T6	5827	8	0	0
T7	2502	2	0	0
T8	5799	2	0	0
T9	56504	27	0	0
T10	34747	18	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	8411	0	0
T1	40729	24	0	0
T2	5836	8	0	0
T3	29291	27	0	0
T4	2915	2	0	0
T5	3431	1	0	0
T6	5827	8	0	0
T7	2502	2	0	0
T8	5799	2	0	0
T9	56504	27	0	0
T10	34747	18	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187522	8411	0	0
T1	81465	24	0	0
T2	11676	8	0	0
T3	58571	27	0	0
T4	5827	2	0	0
T5	6862	1	0	0
T6	11662	8	0	0
T7	5006	2	0	0
T8	11599	2	0	0
T9	113014	27	0	0
T10	69487	18	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25187522	8411	0	0
T1	81465	24	0	0
T2	11676	8	0	0
T3	58571	27	0	0
T4	5827	2	0	0
T5	6862	1	0	0
T6	11662	8	0	0
T7	5006	2	0	0
T8	11599	2	0	0
T9	113014	27	0	0
T10	69487	18	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474405	21265	0	0
T1	169706	57	0	0
T2	24327	8	0	0
T3	122045	102	0	0
T4	12139	6	0	0
T5	14298	1	0	0
T6	24297	8	0	0
T7	10433	6	0	0
T8	24165	2	0	0
T9	235428	102	0	0
T10	144775	57	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474405	21265	0	0
T1	169706	57	0	0
T2	24327	8	0	0
T3	122045	102	0	0
T4	12139	6	0	0
T5	14298	1	0	0
T6	24297	8	0	0
T7	10433	6	0	0
T8	24165	2	0	0
T9	235428	102	0	0
T10	144775	57	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	21265	0	0
T1	5170	57	0	0
T2	731	8	0	0
T3	3676	102	0	0
T4	362	6	0	0
T5	427	1	0	0
T6	731	8	0	0
T7	312	6	0	0
T8	723	2	0	0
T9	7077	102	0	0
T10	4459	57	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	21265	0	0
T1	5170	57	0	0
T2	731	8	0	0
T3	3676	102	0	0
T4	362	6	0	0
T5	427	1	0	0
T6	731	8	0	0
T7	312	6	0	0
T8	723	2	0	0
T9	7077	102	0	0
T10	4459	57	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474405	21265	0	0
T1	169706	57	0	0
T2	24327	8	0	0
T3	122045	102	0	0
T4	12139	6	0	0
T5	14298	1	0	0
T6	24297	8	0	0
T7	10433	6	0	0
T8	24165	2	0	0
T9	235428	102	0	0
T10	144775	57	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474405	21265	0	0
T1	169706	57	0	0
T2	24327	8	0	0
T3	122045	102	0	0
T4	12139	6	0	0
T5	14298	1	0	0
T6	24297	8	0	0
T7	10433	6	0	0
T8	24165	2	0	0
T9	235428	102	0	0
T10	144775	57	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	6730	0	0
T1	5170	17	0	0
T2	731	8	0	0
T3	3676	27	0	0
T4	362	1	0	0
T5	427	1	0	0
T6	731	8	0	0
T7	312	1	0	0
T8	723	21	0	0
T9	7077	27	0	0
T10	4459	9	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474405	21265	0	0
T1	169706	57	0	0
T2	24327	8	0	0
T3	122045	102	0	0
T4	12139	6	0	0
T5	14298	1	0	0
T6	24297	8	0	0
T7	10433	6	0	0
T8	24165	2	0	0
T9	235428	102	0	0
T10	144775	57	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52474405	21265	0	0
T1	169706	57	0	0
T2	24327	8	0	0
T3	122045	102	0	0
T4	12139	6	0	0
T5	14298	1	0	0
T6	24297	8	0	0
T7	10433	6	0	0
T8	24165	2	0	0
T9	235428	102	0	0
T10	144775	57	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	194	0	0
T1	5170	2	0	0
T2	731	0	0	0
T3	3676	0	0	0
T4	362	0	0	0
T5	427	0	0	0
T6	731	0	0	0
T7	312	0	0	0
T8	723	0	0	0
T9	7077	0	0	0
T10	4459	0	0	0
T13	0	3	0	0
T23	0	1	0	0
T26	0	7	0	0
T42	0	1	0	0
T43	0	7	0	0
T71	0	1	0	0
T76	0	3	0	0
T77	0	3	0	0
T94	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590526	8411	0	0
T1	5170	24	0	0
T2	731	8	0	0
T3	3676	27	0	0
T4	362	2	0	0
T5	427	1	0	0
T6	731	8	0	0
T7	312	2	0	0
T8	723	2	0	0
T9	7077	27	0	0
T10	4459	18	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11214219	21265	0	0
T1	34699	57	0	0
T2	5676	8	0	0
T3	25825	102	0	0
T4	2623	6	0	0
T5	3388	1	0	0
T6	5092	8	0	0
T7	2263	6	0	0
T8	5636	2	0	0
T9	53144	102	0	0
T10	30644	57	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11214219	21265	0	0
T1	34699	57	0	0
T2	5676	8	0	0
T3	25825	102	0	0
T4	2623	6	0	0
T5	3388	1	0	0
T6	5092	8	0	0
T7	2263	6	0	0
T8	5636	2	0	0
T9	53144	102	0	0
T10	30644	57	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11214219	21265	0	0
T1	34699	57	0	0
T2	5676	8	0	0
T3	25825	102	0	0
T4	2623	6	0	0
T5	3388	1	0	0
T6	5092	8	0	0
T7	2263	6	0	0
T8	5636	2	0	0
T9	53144	102	0	0
T10	30644	57	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11214219	21265	0	0
T1	34699	57	0	0
T2	5676	8	0	0
T3	25825	102	0	0
T4	2623	6	0	0
T5	3388	1	0	0
T6	5092	8	0	0
T7	2263	6	0	0
T8	5636	2	0	0
T9	53144	102	0	0
T10	30644	57	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	21265	0	0
T1	40729	57	0	0
T2	5836	8	0	0
T3	29291	102	0	0
T4	2915	6	0	0
T5	3431	1	0	0
T6	5827	8	0	0
T7	2502	6	0	0
T8	5799	2	0	0
T9	56504	102	0	0
T10	34747	57	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12593603	21265	0	0
T1	40729	57	0	0
T2	5836	8	0	0
T3	29291	102	0	0
T4	2915	6	0	0
T5	3431	1	0	0
T6	5827	8	0	0
T7	2502	6	0	0
T8	5799	2	0	0
T9	56504	102	0	0
T10	34747	57	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11214219	21265	0	0
T1	34699	57	0	0
T2	5676	8	0	0
T3	25825	102	0	0
T4	2623	6	0	0
T5	3388	1	0	0
T6	5092	8	0	0
T7	2263	6	0	0
T8	5636	2	0	0
T9	53144	102	0	0
T10	30644	57	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11214219	21265	0	0
T1	34699	57	0	0
T2	5676	8	0	0
T3	25825	102	0	0
T4	2623	6	0	0
T5	3388	1	0	0
T6	5092	8	0	0
T7	2263	6	0	0
T8	5636	2	0	0
T9	53144	102	0	0
T10	30644	57	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11214219	21265	0	0
T1	34699	57	0	0
T2	5676	8	0	0
T3	25825	102	0	0
T4	2623	6	0	0
T5	3388	1	0	0
T6	5092	8	0	0
T7	2263	6	0	0
T8	5636	2	0	0
T9	53144	102	0	0
T10	30644	57	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11214219	21265	0	0
T1	34699	57	0	0
T2	5676	8	0	0
T3	25825	102	0	0
T4	2623	6	0	0
T5	3388	1	0	0
T6	5092	8	0	0
T7	2263	6	0	0
T8	5636	2	0	0
T9	53144	102	0	0
T10	30644	57	0	0