Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	608590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

364571

1

T1

378

T2

28

T6

1151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	519232	1			T1	547		T2	30		T4	1
values[0x0]	227065	1			T1	264		T2	14		T6	860
values[0x1]	226864	1			T1	237		T2	20		T6	840

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	510240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

462921

1

T1

482

T2

32

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4001	1			T6	13		T12	46		T15	1
valid_sources[0x01]	3249	1			T6	8		T11	1		T12	29
valid_sources[0x02]	3097	1			T6	15		T11	2		T12	40
valid_sources[0x03]	4628	1			T2	1		T6	12		T12	35
valid_sources[0x04]	3223	1			T6	18		T11	1		T12	36
valid_sources[0x05]	3272	1			T6	11		T10	2		T11	1
valid_sources[0x06]	3684	1			T2	2		T6	7		T11	2
valid_sources[0x07]	2896	1			T6	11		T11	1		T12	41
valid_sources[0x08]	3586	1			T6	9		T8	6		T11	1
valid_sources[0x09]	6627	1			T6	20		T12	43		T17	87
valid_sources[0x0a]	3320	1			T6	15		T11	1		T12	41
valid_sources[0x0b]	3045	1			T6	12		T8	7		T11	3
valid_sources[0x0c]	2721	1			T2	1		T6	15		T8	5
valid_sources[0x0d]	4574	1			T6	13		T10	1		T11	2
valid_sources[0x0e]	3804	1			T6	16		T12	23		T17	123
valid_sources[0x0f]	3610	1			T6	13		T11	2		T12	34
valid_sources[0x10]	6657	1			T6	9		T12	25		T17	110
valid_sources[0x11]	3156	1			T2	1		T6	17		T10	1
valid_sources[0x12]	3458	1			T6	20		T12	39		T17	87
valid_sources[0x13]	3690	1			T6	18		T8	6		T11	2
valid_sources[0x14]	3347	1			T6	20		T11	3		T12	36
valid_sources[0x15]	4643	1			T6	15		T10	1		T12	38
valid_sources[0x16]	3350	1			T6	12		T11	1		T12	39
valid_sources[0x17]	3194	1			T6	9		T11	1		T12	34
valid_sources[0x18]	3167	1			T2	1		T6	10		T8	1
valid_sources[0x19]	2963	1			T6	11		T11	1		T12	43
valid_sources[0x1a]	3491	1			T6	11		T11	1		T12	42
valid_sources[0x1b]	3446	1			T6	16		T11	1		T12	32
valid_sources[0x1c]	4348	1			T6	10		T12	43		T15	1
valid_sources[0x1d]	3138	1			T6	7		T12	32		T15	2
valid_sources[0x1e]	7386	1			T6	13		T12	36		T15	1
valid_sources[0x1f]	3362	1			T6	12		T11	1		T12	43
valid_sources[0x20]	3487	1			T2	1		T6	16		T12	41
valid_sources[0x21]	3358	1			T2	1		T6	19		T8	1
valid_sources[0x22]	3144	1			T6	7		T11	3		T12	38
valid_sources[0x23]	5430	1			T6	17		T11	2		T12	33
valid_sources[0x24]	3022	1			T6	13		T11	2		T12	39
valid_sources[0x25]	3267	1			T4	1		T6	13		T11	1
valid_sources[0x26]	3227	1			T6	12		T8	13		T12	48
valid_sources[0x27]	3817	1			T6	11		T11	3		T12	33
valid_sources[0x28]	3095	1			T6	13		T11	4		T12	21
valid_sources[0x29]	4045	1			T6	14		T11	2		T12	19
valid_sources[0x2a]	3831	1			T6	14		T8	3		T11	2
valid_sources[0x2b]	4778	1			T6	16		T12	31		T15	4
valid_sources[0x2c]	7024	1			T6	11		T11	1		T12	32
valid_sources[0x2d]	3423	1			T6	11		T8	2		T11	3
valid_sources[0x2e]	3306	1			T6	15		T8	2		T11	3
valid_sources[0x2f]	3313	1			T6	16		T8	1		T11	1
valid_sources[0x30]	3320	1			T6	17		T11	1		T12	31
valid_sources[0x31]	3473	1			T2	1		T6	15		T11	2
valid_sources[0x32]	3385	1			T2	1		T6	15		T11	2
valid_sources[0x33]	3631	1			T2	1		T6	12		T11	2
valid_sources[0x34]	3492	1			T6	9		T11	1		T12	37
valid_sources[0x35]	3434	1			T2	3		T6	19		T11	3
valid_sources[0x36]	3404	1			T2	2		T6	13		T11	2
valid_sources[0x37]	10430	1			T2	1		T6	12		T11	1
valid_sources[0x38]	3627	1			T6	10		T11	1		T12	37
valid_sources[0x39]	3733	1			T2	1		T6	14		T11	1
valid_sources[0x3a]	3667	1			T6	10		T11	3		T12	35
valid_sources[0x3b]	3697	1			T6	9		T8	1		T10	1
valid_sources[0x3c]	3488	1			T6	11		T8	3		T11	2
valid_sources[0x3d]	2956	1			T2	1		T6	18		T11	4
valid_sources[0x3e]	3874	1			T6	11		T8	1		T12	33
valid_sources[0x3f]	3754	1			T2	1		T6	9		T8	11
valid_sources[0x40]	3999	1			T6	13		T12	39		T17	87
valid_sources[0x41]	3475	1			T6	9		T11	2		T12	45
valid_sources[0x42]	3280	1			T6	14		T11	4		T12	24
valid_sources[0x43]	3128	1			T6	16		T11	1		T12	47
valid_sources[0x44]	3231	1			T6	11		T8	5		T11	2
valid_sources[0x45]	3648	1			T6	6		T11	3		T12	32
valid_sources[0x46]	3458	1			T6	9		T11	1		T12	35
valid_sources[0x47]	3157	1			T6	6		T11	1		T12	32
valid_sources[0x48]	3515	1			T6	11		T11	2		T12	32
valid_sources[0x49]	3263	1			T6	4		T12	34		T17	108
valid_sources[0x4a]	3116	1			T2	1		T6	16		T11	4
valid_sources[0x4b]	3178	1			T6	25		T8	1		T11	2
valid_sources[0x4c]	3904	1			T6	9		T11	2		T12	37
valid_sources[0x4d]	3447	1			T2	2		T6	19		T12	31
valid_sources[0x4e]	3622	1			T6	12		T8	2		T11	1
valid_sources[0x4f]	3272	1			T6	11		T11	1		T12	37
valid_sources[0x50]	3652	1			T2	2		T6	18		T11	1
valid_sources[0x51]	3558	1			T2	2		T6	12		T11	2
valid_sources[0x52]	2879	1			T6	13		T8	2		T11	2
valid_sources[0x53]	3795	1			T2	1		T6	12		T12	25
valid_sources[0x54]	4854	1			T1	1048		T6	12		T11	3
valid_sources[0x55]	3989	1			T6	13		T8	3		T12	45
valid_sources[0x56]	3694	1			T2	1		T6	15		T11	2
valid_sources[0x57]	3357	1			T6	16		T11	2		T12	22
valid_sources[0x58]	3932	1			T6	16		T11	3		T12	32
valid_sources[0x59]	3171	1			T6	20		T11	1		T12	25
valid_sources[0x5a]	3053	1			T6	8		T12	35		T15	1
valid_sources[0x5b]	2899	1			T2	2		T6	10		T11	1
valid_sources[0x5c]	3201	1			T6	10		T12	40		T15	1
valid_sources[0x5d]	3181	1			T6	11		T11	1		T12	22
valid_sources[0x5e]	3134	1			T6	16		T11	1		T12	41
valid_sources[0x5f]	3157	1			T6	13		T11	1		T12	33
valid_sources[0x60]	4085	1			T6	7		T11	1		T12	33
valid_sources[0x61]	3654	1			T6	11		T12	31		T17	91
valid_sources[0x62]	3087	1			T2	1		T6	9		T11	1
valid_sources[0x63]	3245	1			T6	18		T11	1		T12	43
valid_sources[0x64]	7310	1			T6	6		T12	51		T15	2
valid_sources[0x65]	3370	1			T6	14		T11	1		T12	43
valid_sources[0x66]	3353	1			T6	12		T8	1		T11	2
valid_sources[0x67]	3034	1			T2	2		T6	8		T8	8
valid_sources[0x68]	3546	1			T6	15		T11	1		T12	33
valid_sources[0x69]	3446	1			T6	9		T8	7		T12	30
valid_sources[0x6a]	3467	1			T6	7		T11	1		T12	41
valid_sources[0x6b]	3881	1			T6	8		T11	2		T12	40
valid_sources[0x6c]	3255	1			T6	8		T8	1		T10	1
valid_sources[0x6d]	3013	1			T6	13		T8	4		T11	2
valid_sources[0x6e]	6919	1			T6	10		T8	8		T11	1
valid_sources[0x6f]	3459	1			T6	11		T11	1		T12	21
valid_sources[0x70]	3456	1			T6	5		T8	7		T11	1
valid_sources[0x71]	3407	1			T2	2		T6	15		T11	1
valid_sources[0x72]	3132	1			T6	8		T12	38		T15	2
valid_sources[0x73]	3103	1			T6	16		T11	2		T12	37
valid_sources[0x74]	4090	1			T6	20		T12	34		T16	3
valid_sources[0x75]	3774	1			T6	11		T12	36		T15	1
valid_sources[0x76]	3241	1			T6	10		T11	3		T12	52
valid_sources[0x77]	3818	1			T6	13		T11	3		T12	42
valid_sources[0x78]	6546	1			T6	11		T11	2		T12	43
valid_sources[0x79]	3405	1			T6	21		T12	44		T15	1
valid_sources[0x7a]	4706	1			T6	22		T11	1		T12	31
valid_sources[0x7b]	4079	1			T2	1		T6	9		T11	1
valid_sources[0x7c]	4606	1			T6	12		T10	1		T11	1
valid_sources[0x7d]	3661	1			T6	12		T11	1		T12	20
valid_sources[0x7e]	3265	1			T6	10		T11	1		T12	34
valid_sources[0x7f]	5823	1			T6	10		T11	1		T12	31
valid_sources[0x80]	3434	1			T6	10		T10	1		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

243681

1

T1

261

T2

15

T6

689

values[0x0]

all_enables

biggest_size

79044

1

T1

87

T2

5

T6

304

values[0x1]

all_enables

biggest_size

41846

1

T1

30

T2

8

T6

158