Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T11
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T12
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T13
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12460125	13965	0	0
gen_assertions[0].RstEnOn_A	12460125	1063	0	0
gen_assertions[0].RstNOff_A	12460125	13965	0	0
gen_assertions[0].RstNOn_A	12460125	1063	0	0
gen_assertions[1].RstEnOff_A	49840371	12746	0	0
gen_assertions[1].RstEnOn_A	49840371	1000	0	0
gen_assertions[1].RstNOff_A	49840371	12746	0	0
gen_assertions[1].RstNOn_A	49840371	1000	0	0
gen_assertions[2].RstEnOff_A	24920884	12815	0	0
gen_assertions[2].RstEnOn_A	24920884	1029	0	0
gen_assertions[2].RstNOff_A	24920884	12815	0	0
gen_assertions[2].RstNOn_A	24920884	1029	0	0
gen_assertions[3].RstEnOff_A	24920931	12856	0	0
gen_assertions[3].RstEnOn_A	24920931	1053	0	0
gen_assertions[3].RstNOff_A	24920931	12856	0	0
gen_assertions[3].RstNOn_A	24920931	1053	0	0
gen_assertions[4].RstEnOff_A	1573928	21361	0	0
gen_assertions[4].RstEnOn_A	1573928	1118	0	0
gen_assertions[4].RstNOff_A	1573928	21361	0	0
gen_assertions[4].RstNOn_A	1573928	1118	0	0
gen_assertions[5].RstEnOff_A	12460125	14164	0	0
gen_assertions[5].RstEnOn_A	12460125	1120	0	0
gen_assertions[5].RstNOff_A	12460125	14164	0	0
gen_assertions[5].RstNOn_A	12460125	1120	0	0
gen_assertions[6].RstEnOff_A	12460125	14254	0	0
gen_assertions[6].RstEnOn_A	12460125	1214	0	0
gen_assertions[6].RstNOff_A	12460125	14254	0	0
gen_assertions[6].RstNOn_A	12460125	1214	0	0
gen_assertions[7].RstEnOff_A	12460125	14298	0	0
gen_assertions[7].RstEnOn_A	12460125	1259	0	0
gen_assertions[7].RstNOff_A	12460125	14298	0	0
gen_assertions[7].RstNOn_A	12460125	1259	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	13965	0	0
T1	3581	6	0	0
T2	1821	3	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	75	0	0
T7	5828	0	0	0
T8	2510	4	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	5	0	0
T12	0	128	0	0
T13	0	8	0	0
T14	0	5	0	0
T15	0	4	0	0
T16	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	1063	0	0
T1	3581	6	0	0
T2	1821	1	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	0	0	0
T7	5828	0	0	0
T8	2510	0	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	1	0	0
T12	0	19	0	0
T13	0	8	0	0
T14	0	5	0	0
T16	0	1	0	0
T17	0	25	0	0
T28	0	1	0	0
T63	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	13965	0	0
T1	3581	6	0	0
T2	1821	3	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	75	0	0
T7	5828	0	0	0
T8	2510	4	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	5	0	0
T12	0	128	0	0
T13	0	8	0	0
T14	0	5	0	0
T15	0	4	0	0
T16	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	1063	0	0
T1	3581	6	0	0
T2	1821	1	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	0	0	0
T7	5828	0	0	0
T8	2510	0	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	1	0	0
T12	0	19	0	0
T13	0	8	0	0
T14	0	5	0	0
T16	0	1	0	0
T17	0	25	0	0
T28	0	1	0	0
T63	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49840371	12746	0	0
T1	14329	9	0	0
T2	7288	2	0	0
T3	23286	0	0	0
T4	15825	0	0	0
T5	23444	0	0	0
T6	181630	64	0	0
T7	23318	0	0	0
T8	10048	4	0	0
T9	23330	0	0	0
T10	7096	0	0	0
T11	0	2	0	0
T12	0	116	0	0
T13	0	7	0	0
T14	0	5	0	0
T15	0	4	0	0
T16	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49840371	1000	0	0
T1	14329	9	0	0
T2	7288	1	0	0
T3	23286	0	0	0
T4	15825	0	0	0
T5	23444	0	0	0
T6	181630	0	0	0
T7	23318	0	0	0
T8	10048	0	0	0
T9	23330	0	0	0
T10	7096	0	0	0
T12	0	18	0	0
T13	0	7	0	0
T14	0	5	0	0
T17	0	27	0	0
T63	0	5	0	0
T100	0	2	0	0
T103	0	6	0	0
T104	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49840371	12746	0	0
T1	14329	9	0	0
T2	7288	2	0	0
T3	23286	0	0	0
T4	15825	0	0	0
T5	23444	0	0	0
T6	181630	64	0	0
T7	23318	0	0	0
T8	10048	4	0	0
T9	23330	0	0	0
T10	7096	0	0	0
T11	0	2	0	0
T12	0	116	0	0
T13	0	7	0	0
T14	0	5	0	0
T15	0	4	0	0
T16	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49840371	1000	0	0
T1	14329	9	0	0
T2	7288	1	0	0
T3	23286	0	0	0
T4	15825	0	0	0
T5	23444	0	0	0
T6	181630	0	0	0
T7	23318	0	0	0
T8	10048	0	0	0
T9	23330	0	0	0
T10	7096	0	0	0
T12	0	18	0	0
T13	0	7	0	0
T14	0	5	0	0
T17	0	27	0	0
T63	0	5	0	0
T100	0	2	0	0
T103	0	6	0	0
T104	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920884	12815	0	0
T1	7165	8	0	0
T2	3645	2	0	0
T3	11646	0	0	0
T4	7912	0	0	0
T5	11719	0	0	0
T6	90815	64	0	0
T7	11651	0	0	0
T8	5027	4	0	0
T9	11656	0	0	0
T10	3548	0	0	0
T11	0	2	0	0
T12	0	120	0	0
T13	0	8	0	0
T14	0	6	0	0
T15	0	4	0	0
T16	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920884	1029	0	0
T1	7165	8	0	0
T2	3645	0	0	0
T3	11646	0	0	0
T4	7912	0	0	0
T5	11719	0	0	0
T6	90815	0	0	0
T7	11651	0	0	0
T8	5027	0	0	0
T9	11656	0	0	0
T10	3548	0	0	0
T12	0	19	0	0
T13	0	8	0	0
T14	0	6	0	0
T16	0	1	0	0
T17	0	29	0	0
T63	0	5	0	0
T100	0	3	0	0
T101	0	1	0	0
T103	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920884	12815	0	0
T1	7165	8	0	0
T2	3645	2	0	0
T3	11646	0	0	0
T4	7912	0	0	0
T5	11719	0	0	0
T6	90815	64	0	0
T7	11651	0	0	0
T8	5027	4	0	0
T9	11656	0	0	0
T10	3548	0	0	0
T11	0	2	0	0
T12	0	120	0	0
T13	0	8	0	0
T14	0	6	0	0
T15	0	4	0	0
T16	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920884	1029	0	0
T1	7165	8	0	0
T2	3645	0	0	0
T3	11646	0	0	0
T4	7912	0	0	0
T5	11719	0	0	0
T6	90815	0	0	0
T7	11651	0	0	0
T8	5027	0	0	0
T9	11656	0	0	0
T10	3548	0	0	0
T12	0	19	0	0
T13	0	8	0	0
T14	0	6	0	0
T16	0	1	0	0
T17	0	29	0	0
T63	0	5	0	0
T100	0	3	0	0
T101	0	1	0	0
T103	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920931	12856	0	0
T1	7165	11	0	0
T2	3645	2	0	0
T3	11654	0	0	0
T4	7912	0	0	0
T5	11718	0	0	0
T6	90812	64	0	0
T7	11655	0	0	0
T8	5028	4	0	0
T9	11668	0	0	0
T10	3548	0	0	0
T11	0	2	0	0
T12	0	119	0	0
T13	0	10	0	0
T14	0	7	0	0
T15	0	4	0	0
T16	0	3	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920931	1053	0	0
T1	7165	11	0	0
T2	3645	0	0	0
T3	11654	0	0	0
T4	7912	0	0	0
T5	11718	0	0	0
T6	90812	0	0	0
T7	11655	0	0	0
T8	5028	0	0	0
T9	11668	0	0	0
T10	3548	0	0	0
T12	0	20	0	0
T13	0	10	0	0
T14	0	7	0	0
T17	0	28	0	0
T63	0	9	0	0
T100	0	1	0	0
T101	0	1	0	0
T103	0	7	0	0
T105	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920931	12856	0	0
T1	7165	11	0	0
T2	3645	2	0	0
T3	11654	0	0	0
T4	7912	0	0	0
T5	11718	0	0	0
T6	90812	64	0	0
T7	11655	0	0	0
T8	5028	4	0	0
T9	11668	0	0	0
T10	3548	0	0	0
T11	0	2	0	0
T12	0	119	0	0
T13	0	10	0	0
T14	0	7	0	0
T15	0	4	0	0
T16	0	3	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920931	1053	0	0
T1	7165	11	0	0
T2	3645	0	0	0
T3	11654	0	0	0
T4	7912	0	0	0
T5	11718	0	0	0
T6	90812	0	0	0
T7	11655	0	0	0
T8	5028	0	0	0
T9	11668	0	0	0
T10	3548	0	0	0
T12	0	20	0	0
T13	0	10	0	0
T14	0	7	0	0
T17	0	28	0	0
T63	0	9	0	0
T100	0	1	0	0
T101	0	1	0	0
T103	0	7	0	0
T105	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	21361	0	0
T1	447	12	0	0
T2	225	3	0	0
T3	730	3	0	0
T4	494	2	0	0
T5	733	3	0	0
T6	5691	87	0	0
T7	731	3	0	0
T8	313	5	0	0
T9	731	3	0	0
T10	220	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	1118	0	0
T1	447	11	0	0
T2	225	0	0	0
T3	730	0	0	0
T4	494	0	0	0
T5	733	0	0	0
T6	5691	0	0	0
T7	731	0	0	0
T8	313	0	0	0
T9	731	0	0	0
T10	220	0	0	0
T12	0	18	0	0
T13	0	12	0	0
T14	0	9	0	0
T16	0	1	0	0
T17	0	25	0	0
T28	0	1	0	0
T63	0	10	0	0
T100	0	2	0	0
T101	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	21361	0	0
T1	447	12	0	0
T2	225	3	0	0
T3	730	3	0	0
T4	494	2	0	0
T5	733	3	0	0
T6	5691	87	0	0
T7	731	3	0	0
T8	313	5	0	0
T9	731	3	0	0
T10	220	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	1118	0	0
T1	447	11	0	0
T2	225	0	0	0
T3	730	0	0	0
T4	494	0	0	0
T5	733	0	0	0
T6	5691	0	0	0
T7	731	0	0	0
T8	313	0	0	0
T9	731	0	0	0
T10	220	0	0	0
T12	0	18	0	0
T13	0	12	0	0
T14	0	9	0	0
T16	0	1	0	0
T17	0	25	0	0
T28	0	1	0	0
T63	0	10	0	0
T100	0	2	0	0
T101	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	14164	0	0
T1	3581	10	0	0
T2	1821	3	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	75	0	0
T7	5828	0	0	0
T8	2510	4	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	4	0	0
T12	0	129	0	0
T13	0	11	0	0
T14	0	8	0	0
T15	0	4	0	0
T16	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	1120	0	0
T1	3581	10	0	0
T2	1821	0	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	0	0	0
T7	5828	0	0	0
T8	2510	0	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T12	0	19	0	0
T13	0	11	0	0
T14	0	8	0	0
T17	0	20	0	0
T58	0	1	0	0
T63	0	11	0	0
T100	0	1	0	0
T103	0	10	0	0
T104	0	9	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	14164	0	0
T1	3581	10	0	0
T2	1821	3	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	75	0	0
T7	5828	0	0	0
T8	2510	4	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	4	0	0
T12	0	129	0	0
T13	0	11	0	0
T14	0	8	0	0
T15	0	4	0	0
T16	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	1120	0	0
T1	3581	10	0	0
T2	1821	0	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	0	0	0
T7	5828	0	0	0
T8	2510	0	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T12	0	19	0	0
T13	0	11	0	0
T14	0	8	0	0
T17	0	20	0	0
T58	0	1	0	0
T63	0	11	0	0
T100	0	1	0	0
T103	0	10	0	0
T104	0	9	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	14254	0	0
T1	3581	13	0	0
T2	1821	3	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	75	0	0
T7	5828	0	0	0
T8	2510	4	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	4	0	0
T12	0	128	0	0
T13	0	12	0	0
T14	0	10	0	0
T15	0	4	0	0
T16	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	1214	0	0
T1	3581	13	0	0
T2	1821	0	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	0	0	0
T7	5828	0	0	0
T8	2510	0	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T12	0	18	0	0
T13	0	12	0	0
T14	0	10	0	0
T17	0	26	0	0
T28	0	1	0	0
T63	0	11	0	0
T100	0	1	0	0
T103	0	11	0	0
T104	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	14254	0	0
T1	3581	13	0	0
T2	1821	3	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	75	0	0
T7	5828	0	0	0
T8	2510	4	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	4	0	0
T12	0	128	0	0
T13	0	12	0	0
T14	0	10	0	0
T15	0	4	0	0
T16	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	1214	0	0
T1	3581	13	0	0
T2	1821	0	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	0	0	0
T7	5828	0	0	0
T8	2510	0	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T12	0	18	0	0
T13	0	12	0	0
T14	0	10	0	0
T17	0	26	0	0
T28	0	1	0	0
T63	0	11	0	0
T100	0	1	0	0
T103	0	11	0	0
T104	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	14298	0	0
T1	3581	13	0	0
T2	1821	3	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	75	0	0
T7	5828	0	0	0
T8	2510	4	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	4	0	0
T12	0	128	0	0
T13	0	12	0	0
T14	0	11	0	0
T15	0	4	0	0
T16	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	1259	0	0
T1	3581	13	0	0
T2	1821	0	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	0	0	0
T7	5828	0	0	0
T8	2510	0	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T12	0	18	0	0
T13	0	12	0	0
T14	0	11	0	0
T17	0	28	0	0
T63	0	12	0	0
T100	0	1	0	0
T101	0	1	0	0
T103	0	10	0	0
T104	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	14298	0	0
T1	3581	13	0	0
T2	1821	3	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	75	0	0
T7	5828	0	0	0
T8	2510	4	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T11	0	4	0	0
T12	0	128	0	0
T13	0	12	0	0
T14	0	11	0	0
T15	0	4	0	0
T16	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	1259	0	0
T1	3581	13	0	0
T2	1821	0	0	0
T3	5823	0	0	0
T4	3955	0	0	0
T5	5857	0	0	0
T6	45425	0	0	0
T7	5828	0	0	0
T8	2510	0	0	0
T9	5831	0	0	0
T10	1773	0	0	0
T12	0	18	0	0
T13	0	12	0	0
T14	0	11	0	0
T17	0	28	0	0
T63	0	12	0	0
T100	0	1	0	0
T101	0	1	0	0
T103	0	10	0	0
T104	0	10	0	0