Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11748288	7159	0	0
alert_regwen_rd_A	11748288	4733	0	0
cpu_regwen_rd_A	11748288	4400	0	0
sw_rst_ctrl_n_0_rd_A	11748288	8294	0	0
sw_rst_ctrl_n_1_rd_A	11748288	8277	0	0
sw_rst_ctrl_n_2_rd_A	11748288	8078	0	0
sw_rst_ctrl_n_3_rd_A	11748288	7999	0	0
sw_rst_ctrl_n_4_rd_A	11748288	8309	0	0
sw_rst_ctrl_n_5_rd_A	11748288	8120	0	0
sw_rst_ctrl_n_6_rd_A	11748288	8188	0	0
sw_rst_ctrl_n_7_rd_A	11748288	8244	0	0
sw_rst_regwen_0_rd_A	11748288	4806	0	0
sw_rst_regwen_1_rd_A	11748288	5018	0	0
sw_rst_regwen_2_rd_A	11748288	4798	0	0
sw_rst_regwen_3_rd_A	11748288	4842	0	0
sw_rst_regwen_4_rd_A	11748288	4980	0	0
sw_rst_regwen_5_rd_A	11748288	4711	0	0
sw_rst_regwen_6_rd_A	11748288	4877	0	0
sw_rst_regwen_7_rd_A	11748288	4877	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	7159	0	0
T69	3095	28	0	0
T71	9615	2	0	0
T72	2186	154	0	0
T73	2814	295	0	0
T74	21671	3	0	0
T79	2787	122	0	0
T89	10313	491	0	0
T90	2874	247	0	0
T96	12012	374	0	0
T106	0	110	0	0
T107	3377	0	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4733	0	0
T18	40953	77	0	0
T20	4892	0	0	0
T39	0	34	0	0
T47	26287	0	0	0
T70	0	8	0	0
T74	0	94	0	0
T102	5098	0	0	0
T104	2934	0	0	0
T105	2505	0	0	0
T110	41077	54	0	0
T111	32660	0	0	0
T112	0	316	0	0
T113	0	95	0	0
T115	0	110	0	0
T121	0	180	0	0
T127	0	7	0	0
T133	2354	0	0	0
T134	2093	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4400	0	0
T18	40953	51	0	0
T20	4892	0	0	0
T39	0	34	0	0
T47	26287	0	0	0
T70	0	5	0	0
T74	0	70	0	0
T102	5098	0	0	0
T104	2934	0	0	0
T105	2505	0	0	0
T110	41077	74	0	0
T111	32660	0	0	0
T112	0	294	0	0
T113	0	57	0	0
T115	0	112	0	0
T121	0	178	0	0
T127	0	4	0	0
T133	2354	0	0	0
T134	2093	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	8294	0	0
T11	5896	19	0	0
T12	56931	0	0	0
T13	12196	205	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	6	0	0
T17	275670	0	0	0
T18	40953	79	0	0
T55	0	25	0	0
T58	0	23	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	54	0	0
T112	0	536	0	0
T113	0	80	0	0
T135	0	45	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	8277	0	0
T11	5896	17	0	0
T12	56931	0	0	0
T13	12196	209	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	15	0	0
T17	275670	0	0	0
T18	40953	92	0	0
T55	0	9	0	0
T58	0	15	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	70	0	0
T112	0	500	0	0
T113	0	64	0	0
T135	0	81	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	8078	0	0
T11	5896	27	0	0
T12	56931	0	0	0
T13	12196	193	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	5	0	0
T17	275670	0	0	0
T18	40953	65	0	0
T55	0	22	0	0
T58	0	17	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	66	0	0
T112	0	464	0	0
T113	0	56	0	0
T135	0	49	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	7999	0	0
T11	5896	10	0	0
T12	56931	0	0	0
T13	12196	163	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	21	0	0
T17	275670	0	0	0
T18	40953	80	0	0
T55	0	14	0	0
T58	0	13	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	83	0	0
T112	0	466	0	0
T113	0	70	0	0
T135	0	40	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	8309	0	0
T11	5896	16	0	0
T12	56931	0	0	0
T13	12196	189	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	2	0	0
T17	275670	0	0	0
T18	40953	60	0	0
T55	0	16	0	0
T58	0	9	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	57	0	0
T112	0	540	0	0
T113	0	56	0	0
T135	0	55	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	8120	0	0
T11	5896	10	0	0
T12	56931	0	0	0
T13	12196	191	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	0	0	0
T17	275670	0	0	0
T18	40953	58	0	0
T55	0	16	0	0
T58	0	15	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	59	0	0
T112	0	492	0	0
T113	0	84	0	0
T115	0	292	0	0
T135	0	56	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	8188	0	0
T11	5896	20	0	0
T12	56931	0	0	0
T13	12196	198	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	12	0	0
T17	275670	0	0	0
T18	40953	82	0	0
T55	0	5	0	0
T58	0	23	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	59	0	0
T112	0	524	0	0
T113	0	78	0	0
T135	0	68	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	8244	0	0
T11	5896	12	0	0
T12	56931	0	0	0
T13	12196	217	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	10	0	0
T17	275670	0	0	0
T18	40953	59	0	0
T55	0	25	0	0
T58	0	11	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	68	0	0
T112	0	463	0	0
T113	0	80	0	0
T135	0	53	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4806	0	0
T11	5896	15	0	0
T12	56931	0	0	0
T13	12196	37	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	10	0	0
T17	275670	0	0	0
T18	40953	71	0	0
T55	0	2	0	0
T58	0	10	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	64	0	0
T112	0	301	0	0
T113	0	71	0	0
T115	0	105	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	5018	0	0
T11	5896	3	0	0
T12	56931	0	0	0
T13	12196	42	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	0	0	0
T17	275670	0	0	0
T18	40953	73	0	0
T39	0	27	0	0
T55	0	7	0	0
T58	0	6	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	70	0	0
T112	0	301	0	0
T113	0	84	0	0
T115	0	139	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4798	0	0
T11	5896	2	0	0
T12	56931	0	0	0
T13	12196	41	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	5	0	0
T17	275670	0	0	0
T18	40953	64	0	0
T55	0	3	0	0
T58	0	7	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	66	0	0
T112	0	252	0	0
T113	0	58	0	0
T115	0	125	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4842	0	0
T11	5896	6	0	0
T12	56931	0	0	0
T13	12196	33	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	4	0	0
T17	275670	0	0	0
T18	40953	60	0	0
T55	0	1	0	0
T58	0	5	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	70	0	0
T112	0	294	0	0
T113	0	73	0	0
T115	0	130	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4980	0	0
T11	5896	6	0	0
T12	56931	0	0	0
T13	12196	33	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	6	0	0
T17	275670	0	0	0
T18	40953	77	0	0
T39	0	30	0	0
T55	0	2	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	88	0	0
T112	0	285	0	0
T113	0	53	0	0
T115	0	139	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4711	0	0
T11	5896	6	0	0
T12	56931	0	0	0
T13	12196	39	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	0	0	0
T17	275670	0	0	0
T18	40953	75	0	0
T39	0	37	0	0
T55	0	10	0	0
T58	0	5	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	55	0	0
T112	0	271	0	0
T113	0	69	0	0
T115	0	151	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4877	0	0
T11	5896	4	0	0
T12	56931	0	0	0
T13	12196	35	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	2	0	0
T17	275670	0	0	0
T18	40953	80	0	0
T55	0	1	0	0
T58	0	13	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	50	0	0
T112	0	270	0	0
T113	0	68	0	0
T115	0	109	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11748288	4877	0	0
T11	5896	14	0	0
T12	56931	0	0	0
T13	12196	36	0	0
T14	3181	0	0	0
T15	4008	0	0	0
T16	5216	0	0	0
T17	275670	0	0	0
T18	40953	48	0	0
T39	0	40	0	0
T55	0	9	0	0
T58	0	10	0	0
T62	188187	0	0	0
T77	1704	0	0	0
T110	0	54	0	0
T112	0	288	0	0
T113	0	58	0	0
T115	0	113	0	0