Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11012484	13079	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11012484	120374	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11012484	6364807	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11012484	192318	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11012484	13079	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11012484	120374	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11012484	6364807	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11012484	192318	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	13079	0	0
T2	1616	3	0	0
T3	5663	0	0	0
T4	3792	0	0	0
T5	5505	0	0	0
T6	42094	75	0	0
T7	5473	0	0	0
T8	2226	4	0	0
T9	5478	0	0	0
T10	1683	0	0	0
T11	5896	4	0	0
T12	0	111	0	0
T15	0	4	0	0
T16	0	4	0	0
T17	0	319	0	0
T18	0	41	0	0
T28	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	120374	0	0
T2	1616	27	0	0
T3	5663	0	0	0
T4	3792	0	0	0
T5	5505	0	0	0
T6	42094	721	0	0
T7	5473	0	0	0
T8	2226	37	0	0
T9	5478	0	0	0
T10	1683	0	0	0
T11	5896	38	0	0
T12	0	1016	0	0
T15	0	37	0	0
T16	0	37	0	0
T17	0	2875	0	0
T18	0	370	0	0
T28	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	6364807	0	0
T1	3563	2922	0	0
T2	1616	929	0	0
T3	5663	565	0	0
T4	3792	817	0	0
T5	5505	582	0	0
T6	42094	24982	0	0
T7	5473	583	0	0
T8	2226	1255	0	0
T9	5478	573	0	0
T10	1683	1106	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	192318	0	0
T2	1616	35	0	0
T3	5663	0	0	0
T4	3792	0	0	0
T5	5505	0	0	0
T6	42094	1085	0	0
T7	5473	0	0	0
T8	2226	66	0	0
T9	5478	0	0	0
T10	1683	0	0	0
T11	5896	50	0	0
T12	0	1654	0	0
T15	0	48	0	0
T16	0	61	0	0
T17	0	4669	0	0
T18	0	612	0	0
T28	0	63	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	13079	0	0
T2	1616	3	0	0
T3	5663	0	0	0
T4	3792	0	0	0
T5	5505	0	0	0
T6	42094	75	0	0
T7	5473	0	0	0
T8	2226	4	0	0
T9	5478	0	0	0
T10	1683	0	0	0
T11	5896	4	0	0
T12	0	111	0	0
T15	0	4	0	0
T16	0	4	0	0
T17	0	319	0	0
T18	0	41	0	0
T28	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	120374	0	0
T2	1616	27	0	0
T3	5663	0	0	0
T4	3792	0	0	0
T5	5505	0	0	0
T6	42094	721	0	0
T7	5473	0	0	0
T8	2226	37	0	0
T9	5478	0	0	0
T10	1683	0	0	0
T11	5896	38	0	0
T12	0	1016	0	0
T15	0	37	0	0
T16	0	37	0	0
T17	0	2875	0	0
T18	0	370	0	0
T28	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	6364807	0	0
T1	3563	2922	0	0
T2	1616	929	0	0
T3	5663	565	0	0
T4	3792	817	0	0
T5	5505	582	0	0
T6	42094	24982	0	0
T7	5473	583	0	0
T8	2226	1255	0	0
T9	5478	573	0	0
T10	1683	1106	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	192318	0	0
T2	1616	35	0	0
T3	5663	0	0	0
T4	3792	0	0	0
T5	5505	0	0	0
T6	42094	1085	0	0
T7	5473	0	0	0
T8	2226	66	0	0
T9	5478	0	0	0
T10	1683	0	0	0
T11	5896	50	0	0
T12	0	1654	0	0
T15	0	48	0	0
T16	0	61	0	0
T17	0	4669	0	0
T18	0	612	0	0
T28	0	63	0	0