Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T12
0	1	Covered	T12,T17,T18
1	0	Covered	T12,T16,T17

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T8,T11,T12
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51918659	8542	0	0
CascadeEffAonToRstPorAboveRise_A	51918659	8542	0	0
CascadeEffAonToRstPorIoAboveFall_A	49840371	8542	0	0
CascadeEffAonToRstPorIoAboveRise_A	49840371	8542	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24920884	8542	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24920884	8542	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12460125	8542	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12460125	8542	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24920931	8542	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24920931	8542	0	0
CascadeLcToLcAboveFall_A	51918659	21621	0	0
CascadeLcToLcAboveRise_A	51918659	21621	0	0
CascadeLcToLcAonAboveFall_A	1573928	21621	0	0
CascadeLcToLcAonAboveRise_A	1573928	21621	0	0
CascadeLcToLcShadowedAboveFall_A	51918659	21621	0	0
CascadeLcToLcShadowedAboveRise_A	51918659	21621	0	0
CascadePorToAonAboveFall_A	1573928	6779	0	0
CascadeSysToSysAboveFall_A	51918659	21621	0	0
CascadeSysToSysAboveRise_A	51918659	21621	0	0
ScanRstToAonRise_A	1573928	195	0	0
StablePorToAonRise_A	1573928	8542	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11012484	21621	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11012484	21621	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11012484	21621	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11012484	21621	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12460125	21621	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12460125	21621	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11012484	21621	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11012484	21621	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11012484	21621	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11012484	21621	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51918659	8542	0	0
T1	14926	1	0	0
T2	7593	1	0	0
T3	24273	8	0	0
T4	16485	2	0	0
T5	24411	8	0	0
T6	189222	27	0	0
T7	24287	8	0	0
T8	10468	2	0	0
T9	24310	8	0	0
T10	7392	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51918659	8542	0	0
T1	14926	1	0	0
T2	7593	1	0	0
T3	24273	8	0	0
T4	16485	2	0	0
T5	24411	8	0	0
T6	189222	27	0	0
T7	24287	8	0	0
T8	10468	2	0	0
T9	24310	8	0	0
T10	7392	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49840371	8542	0	0
T1	14329	1	0	0
T2	7288	1	0	0
T3	23286	8	0	0
T4	15825	2	0	0
T5	23444	8	0	0
T6	181630	27	0	0
T7	23318	8	0	0
T8	10048	2	0	0
T9	23330	8	0	0
T10	7096	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49840371	8542	0	0
T1	14329	1	0	0
T2	7288	1	0	0
T3	23286	8	0	0
T4	15825	2	0	0
T5	23444	8	0	0
T6	181630	27	0	0
T7	23318	8	0	0
T8	10048	2	0	0
T9	23330	8	0	0
T10	7096	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920884	8542	0	0
T1	7165	1	0	0
T2	3645	1	0	0
T3	11646	8	0	0
T4	7912	2	0	0
T5	11719	8	0	0
T6	90815	27	0	0
T7	11651	8	0	0
T8	5027	2	0	0
T9	11656	8	0	0
T10	3548	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920884	8542	0	0
T1	7165	1	0	0
T2	3645	1	0	0
T3	11646	8	0	0
T4	7912	2	0	0
T5	11719	8	0	0
T6	90815	27	0	0
T7	11651	8	0	0
T8	5027	2	0	0
T9	11656	8	0	0
T10	3548	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	8542	0	0
T1	3581	1	0	0
T2	1821	1	0	0
T3	5823	8	0	0
T4	3955	2	0	0
T5	5857	8	0	0
T6	45425	27	0	0
T7	5828	8	0	0
T8	2510	2	0	0
T9	5831	8	0	0
T10	1773	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	8542	0	0
T1	3581	1	0	0
T2	1821	1	0	0
T3	5823	8	0	0
T4	3955	2	0	0
T5	5857	8	0	0
T6	45425	27	0	0
T7	5828	8	0	0
T8	2510	2	0	0
T9	5831	8	0	0
T10	1773	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920931	8542	0	0
T1	7165	1	0	0
T2	3645	1	0	0
T3	11654	8	0	0
T4	7912	2	0	0
T5	11718	8	0	0
T6	90812	27	0	0
T7	11655	8	0	0
T8	5028	2	0	0
T9	11668	8	0	0
T10	3548	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24920931	8542	0	0
T1	7165	1	0	0
T2	3645	1	0	0
T3	11654	8	0	0
T4	7912	2	0	0
T5	11718	8	0	0
T6	90812	27	0	0
T7	11655	8	0	0
T8	5028	2	0	0
T9	11668	8	0	0
T10	3548	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51918659	21621	0	0
T1	14926	1	0	0
T2	7593	4	0	0
T3	24273	8	0	0
T4	16485	2	0	0
T5	24411	8	0	0
T6	189222	102	0	0
T7	24287	8	0	0
T8	10468	6	0	0
T9	24310	8	0	0
T10	7392	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51918659	21621	0	0
T1	14926	1	0	0
T2	7593	4	0	0
T3	24273	8	0	0
T4	16485	2	0	0
T5	24411	8	0	0
T6	189222	102	0	0
T7	24287	8	0	0
T8	10468	6	0	0
T9	24310	8	0	0
T10	7392	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	21621	0	0
T1	447	1	0	0
T2	225	4	0	0
T3	730	8	0	0
T4	494	2	0	0
T5	733	8	0	0
T6	5691	102	0	0
T7	731	8	0	0
T8	313	6	0	0
T9	731	8	0	0
T10	220	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	21621	0	0
T1	447	1	0	0
T2	225	4	0	0
T3	730	8	0	0
T4	494	2	0	0
T5	733	8	0	0
T6	5691	102	0	0
T7	731	8	0	0
T8	313	6	0	0
T9	731	8	0	0
T10	220	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51918659	21621	0	0
T1	14926	1	0	0
T2	7593	4	0	0
T3	24273	8	0	0
T4	16485	2	0	0
T5	24411	8	0	0
T6	189222	102	0	0
T7	24287	8	0	0
T8	10468	6	0	0
T9	24310	8	0	0
T10	7392	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51918659	21621	0	0
T1	14926	1	0	0
T2	7593	4	0	0
T3	24273	8	0	0
T4	16485	2	0	0
T5	24411	8	0	0
T6	189222	102	0	0
T7	24287	8	0	0
T8	10468	6	0	0
T9	24310	8	0	0
T10	7392	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	6779	0	0
T1	447	1	0	0
T2	225	1	0	0
T3	730	8	0	0
T4	494	9	0	0
T5	733	8	0	0
T6	5691	27	0	0
T7	731	8	0	0
T8	313	1	0	0
T9	731	8	0	0
T10	220	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51918659	21621	0	0
T1	14926	1	0	0
T2	7593	4	0	0
T3	24273	8	0	0
T4	16485	2	0	0
T5	24411	8	0	0
T6	189222	102	0	0
T7	24287	8	0	0
T8	10468	6	0	0
T9	24310	8	0	0
T10	7392	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51918659	21621	0	0
T1	14926	1	0	0
T2	7593	4	0	0
T3	24273	8	0	0
T4	16485	2	0	0
T5	24411	8	0	0
T6	189222	102	0	0
T7	24287	8	0	0
T8	10468	6	0	0
T9	24310	8	0	0
T10	7392	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	195	0	0
T12	9038	3	0	0
T13	1534	0	0	0
T14	405	0	0	0
T15	519	0	0	0
T16	681	0	0	0
T17	40258	8	0	0
T18	5850	2	0	0
T57	0	1	0	0
T62	25147	0	0	0
T77	217	0	0	0
T101	606	1	0	0
T110	0	1	0	0
T112	0	5	0	0
T114	0	1	0	0
T115	0	1	0	0
T138	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573928	8542	0	0
T1	447	1	0	0
T2	225	1	0	0
T3	730	8	0	0
T4	494	2	0	0
T5	733	8	0	0
T6	5691	27	0	0
T7	731	8	0	0
T8	313	2	0	0
T9	731	8	0	0
T10	220	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	21621	0	0
T1	3563	1	0	0
T2	1616	4	0	0
T3	5663	8	0	0
T4	3792	2	0	0
T5	5505	8	0	0
T6	42094	102	0	0
T7	5473	8	0	0
T8	2226	6	0	0
T9	5478	8	0	0
T10	1683	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	21621	0	0
T1	3563	1	0	0
T2	1616	4	0	0
T3	5663	8	0	0
T4	3792	2	0	0
T5	5505	8	0	0
T6	42094	102	0	0
T7	5473	8	0	0
T8	2226	6	0	0
T9	5478	8	0	0
T10	1683	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	21621	0	0
T1	3563	1	0	0
T2	1616	4	0	0
T3	5663	8	0	0
T4	3792	2	0	0
T5	5505	8	0	0
T6	42094	102	0	0
T7	5473	8	0	0
T8	2226	6	0	0
T9	5478	8	0	0
T10	1683	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	21621	0	0
T1	3563	1	0	0
T2	1616	4	0	0
T3	5663	8	0	0
T4	3792	2	0	0
T5	5505	8	0	0
T6	42094	102	0	0
T7	5473	8	0	0
T8	2226	6	0	0
T9	5478	8	0	0
T10	1683	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	21621	0	0
T1	3581	1	0	0
T2	1821	4	0	0
T3	5823	8	0	0
T4	3955	2	0	0
T5	5857	8	0	0
T6	45425	102	0	0
T7	5828	8	0	0
T8	2510	6	0	0
T9	5831	8	0	0
T10	1773	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12460125	21621	0	0
T1	3581	1	0	0
T2	1821	4	0	0
T3	5823	8	0	0
T4	3955	2	0	0
T5	5857	8	0	0
T6	45425	102	0	0
T7	5828	8	0	0
T8	2510	6	0	0
T9	5831	8	0	0
T10	1773	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	21621	0	0
T1	3563	1	0	0
T2	1616	4	0	0
T3	5663	8	0	0
T4	3792	2	0	0
T5	5505	8	0	0
T6	42094	102	0	0
T7	5473	8	0	0
T8	2226	6	0	0
T9	5478	8	0	0
T10	1683	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	21621	0	0
T1	3563	1	0	0
T2	1616	4	0	0
T3	5663	8	0	0
T4	3792	2	0	0
T5	5505	8	0	0
T6	42094	102	0	0
T7	5473	8	0	0
T8	2226	6	0	0
T9	5478	8	0	0
T10	1683	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	21621	0	0
T1	3563	1	0	0
T2	1616	4	0	0
T3	5663	8	0	0
T4	3792	2	0	0
T5	5505	8	0	0
T6	42094	102	0	0
T7	5473	8	0	0
T8	2226	6	0	0
T9	5478	8	0	0
T10	1683	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11012484	21621	0	0
T1	3563	1	0	0
T2	1616	4	0	0
T3	5663	8	0	0
T4	3792	2	0	0
T5	5505	8	0	0
T6	42094	102	0	0
T7	5473	8	0	0
T8	2226	6	0	0
T9	5478	8	0	0
T10	1683	1	0	0