Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	600083	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

363393

1

T1

44

T2

3996

T3

1091

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	511584	1			T1	72		T2	5842		T3	1500
values[0x0]	225969	1			T1	47		T2	2455		T3	843
values[0x1]	225923	1			T1	31		T2	2404		T3	857

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	503525	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

459951

1

T1

60

T2

5087

T3

1448

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3422	1			T3	12		T9	24		T10	16
valid_sources[0x01]	3692	1			T3	11		T6	1		T9	27
valid_sources[0x02]	3819	1			T3	19		T9	32		T10	10
valid_sources[0x03]	3948	1			T3	15		T9	3		T10	7
valid_sources[0x04]	3721	1			T2	138		T3	15		T9	1
valid_sources[0x05]	3074	1			T3	15		T9	8		T10	12
valid_sources[0x06]	3236	1			T3	13		T9	4		T10	6
valid_sources[0x07]	3091	1			T3	10		T9	4		T10	11
valid_sources[0x08]	3107	1			T3	7		T6	1		T9	9
valid_sources[0x09]	3553	1			T3	10		T4	282		T6	2
valid_sources[0x0a]	3249	1			T3	15		T9	34		T10	19
valid_sources[0x0b]	3360	1			T3	17		T6	1		T10	5
valid_sources[0x0c]	3860	1			T3	18		T6	1		T9	7
valid_sources[0x0d]	3378	1			T2	113		T3	22		T6	1
valid_sources[0x0e]	4184	1			T3	10		T4	70		T6	1
valid_sources[0x0f]	3789	1			T2	59		T3	10		T6	1
valid_sources[0x10]	4560	1			T3	9		T9	9		T10	9
valid_sources[0x11]	3591	1			T3	15		T4	70		T9	26
valid_sources[0x12]	3547	1			T3	19		T4	70		T10	9
valid_sources[0x13]	3791	1			T3	10		T6	1		T9	8
valid_sources[0x14]	3273	1			T3	8		T6	1		T9	14
valid_sources[0x15]	4705	1			T3	7		T7	495		T10	18
valid_sources[0x16]	3565	1			T2	2		T3	7		T6	1
valid_sources[0x17]	2971	1			T3	2		T9	1		T10	10
valid_sources[0x18]	3574	1			T3	11		T6	1		T10	6
valid_sources[0x19]	4929	1			T3	24		T9	46		T10	14
valid_sources[0x1a]	4019	1			T3	11		T4	365		T8	70
valid_sources[0x1b]	3522	1			T3	10		T6	1		T9	13
valid_sources[0x1c]	4351	1			T3	13		T9	7		T10	11
valid_sources[0x1d]	4063	1			T3	17		T8	55		T9	1
valid_sources[0x1e]	3795	1			T2	81		T3	3		T9	21
valid_sources[0x1f]	3593	1			T3	15		T10	13		T61	3
valid_sources[0x20]	3525	1			T2	13		T3	13		T6	3
valid_sources[0x21]	3300	1			T2	10		T3	14		T6	2
valid_sources[0x22]	4056	1			T1	150		T3	14		T6	1
valid_sources[0x23]	3038	1			T2	156		T3	18		T4	70
valid_sources[0x24]	3065	1			T3	12		T6	1		T10	15
valid_sources[0x25]	4050	1			T2	185		T3	8		T6	1
valid_sources[0x26]	3727	1			T3	14		T4	13		T9	38
valid_sources[0x27]	3111	1			T3	21		T6	3		T9	4
valid_sources[0x28]	3630	1			T3	10		T9	2		T10	13
valid_sources[0x29]	3189	1			T3	12		T4	7		T9	2
valid_sources[0x2a]	3615	1			T3	12		T6	1		T10	10
valid_sources[0x2b]	3333	1			T3	14		T9	12		T10	16
valid_sources[0x2c]	3223	1			T3	12		T9	23		T10	12
valid_sources[0x2d]	3060	1			T3	13		T6	1		T10	7
valid_sources[0x2e]	4058	1			T2	326		T3	18		T4	608
valid_sources[0x2f]	3281	1			T3	6		T4	70		T9	23
valid_sources[0x30]	3234	1			T3	17		T10	3		T56	53
valid_sources[0x31]	3801	1			T2	10		T3	11		T4	325
valid_sources[0x32]	3368	1			T2	2		T3	17		T7	70
valid_sources[0x33]	3028	1			T2	118		T3	14		T9	4
valid_sources[0x34]	3543	1			T3	11		T9	5		T10	12
valid_sources[0x35]	3981	1			T2	190		T3	9		T9	14
valid_sources[0x36]	3882	1			T3	4		T6	1		T9	6
valid_sources[0x37]	6170	1			T3	16		T10	15		T56	70
valid_sources[0x38]	3444	1			T2	294		T3	6		T6	2
valid_sources[0x39]	3288	1			T3	13		T9	68		T10	7
valid_sources[0x3a]	3092	1			T3	11		T6	1		T8	198
valid_sources[0x3b]	3331	1			T3	10		T4	112		T9	2
valid_sources[0x3c]	3570	1			T3	10		T6	3		T9	21
valid_sources[0x3d]	3577	1			T2	1		T3	13		T6	1
valid_sources[0x3e]	3675	1			T3	8		T4	70		T6	1
valid_sources[0x3f]	5098	1			T2	960		T3	13		T4	155
valid_sources[0x40]	3431	1			T2	2		T3	18		T4	70
valid_sources[0x41]	3195	1			T3	9		T6	1		T8	198
valid_sources[0x42]	3052	1			T2	155		T3	12		T9	13
valid_sources[0x43]	3074	1			T3	13		T4	6		T9	3
valid_sources[0x44]	3928	1			T3	10		T4	324		T9	15
valid_sources[0x45]	4246	1			T2	12		T3	19		T4	70
valid_sources[0x46]	3858	1			T2	1		T3	10		T6	2
valid_sources[0x47]	3965	1			T3	5		T4	113		T9	1
valid_sources[0x48]	3642	1			T2	113		T3	13		T4	70
valid_sources[0x49]	4092	1			T3	12		T4	178		T9	59
valid_sources[0x4a]	3336	1			T3	13		T4	240		T6	1
valid_sources[0x4b]	3552	1			T3	12		T6	2		T9	11
valid_sources[0x4c]	3871	1			T2	55		T3	16		T4	691
valid_sources[0x4d]	3903	1			T3	13		T6	1		T10	14
valid_sources[0x4e]	3664	1			T3	11		T6	5		T9	17
valid_sources[0x4f]	3136	1			T3	13		T9	17		T10	9
valid_sources[0x50]	3146	1			T3	14		T9	21		T10	7
valid_sources[0x51]	3495	1			T2	3		T3	13		T4	70
valid_sources[0x52]	4366	1			T3	9		T6	1		T9	19
valid_sources[0x53]	3263	1			T3	14		T4	70		T9	38
valid_sources[0x54]	3380	1			T3	11		T6	2		T9	9
valid_sources[0x55]	3348	1			T3	12		T8	70		T9	3
valid_sources[0x56]	3565	1			T3	11		T6	1		T10	10
valid_sources[0x57]	3310	1			T3	19		T9	1		T10	7
valid_sources[0x58]	3626	1			T2	3		T3	15		T6	2
valid_sources[0x59]	4041	1			T3	18		T6	1		T9	14
valid_sources[0x5a]	3383	1			T3	8		T9	19		T10	14
valid_sources[0x5b]	3064	1			T3	17		T4	3		T9	5
valid_sources[0x5c]	3428	1			T3	20		T9	19		T10	12
valid_sources[0x5d]	3253	1			T3	9		T4	70		T10	10
valid_sources[0x5e]	5217	1			T2	1		T3	13		T4	70
valid_sources[0x5f]	4014	1			T2	57		T3	16		T9	17
valid_sources[0x60]	2961	1			T3	15		T8	112		T9	21
valid_sources[0x61]	3304	1			T3	8		T6	1		T9	13
valid_sources[0x62]	3223	1			T2	1		T3	18		T9	9
valid_sources[0x63]	3974	1			T2	261		T3	12		T4	112
valid_sources[0x64]	3409	1			T3	6		T9	13		T10	12
valid_sources[0x65]	3031	1			T2	99		T3	4		T9	5
valid_sources[0x66]	3508	1			T3	13		T6	2		T8	197
valid_sources[0x67]	5225	1			T3	14		T9	2		T10	10
valid_sources[0x68]	3108	1			T3	8		T6	1		T10	5
valid_sources[0x69]	3989	1			T3	15		T4	113		T6	1
valid_sources[0x6a]	3418	1			T3	16		T7	156		T9	4
valid_sources[0x6b]	3895	1			T2	70		T3	18		T4	310
valid_sources[0x6c]	3564	1			T3	10		T10	11		T65	2
valid_sources[0x6d]	4702	1			T3	16		T8	266		T9	10
valid_sources[0x6e]	3437	1			T3	18		T6	2		T9	6
valid_sources[0x6f]	3660	1			T3	9		T6	2		T7	155
valid_sources[0x70]	3656	1			T3	10		T9	34		T10	10
valid_sources[0x71]	3073	1			T3	8		T6	1		T9	10
valid_sources[0x72]	3480	1			T2	70		T3	13		T9	17
valid_sources[0x73]	4511	1			T2	58		T3	9		T4	70
valid_sources[0x74]	6361	1			T3	17		T6	1		T9	2
valid_sources[0x75]	3527	1			T2	3		T3	13		T6	1
valid_sources[0x76]	3037	1			T2	2		T3	10		T9	7
valid_sources[0x77]	3156	1			T3	12		T9	24		T10	9
valid_sources[0x78]	3497	1			T2	316		T3	22		T8	70
valid_sources[0x79]	4147	1			T3	12		T6	2		T9	2
valid_sources[0x7a]	4459	1			T2	273		T3	9		T4	845
valid_sources[0x7b]	4637	1			T2	832		T3	11		T4	155
valid_sources[0x7c]	3615	1			T3	14		T4	149		T6	1
valid_sources[0x7d]	3443	1			T2	1		T3	4		T7	155
valid_sources[0x7e]	7745	1			T3	11		T6	1		T10	10
valid_sources[0x7f]	3909	1			T2	391		T3	21		T10	11
valid_sources[0x80]	3661	1			T3	9		T9	14		T10	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

240328

1

T1

32

T2

2740

T3

648

values[0x0]

all_enables

biggest_size

80097

1

T1

10

T2

829

T3

307

values[0x1]

all_enables

biggest_size

42968

1

T1

2

T2

427

T3

136