Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T55
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T55
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T55
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T55
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T55
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T55
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13178728	13804	0	0
gen_assertions[0].RstEnOn_A	13178728	1130	0	0
gen_assertions[0].RstNOff_A	13178728	13804	0	0
gen_assertions[0].RstNOn_A	13178728	1130	0	0
gen_assertions[1].RstEnOff_A	52714499	12582	0	0
gen_assertions[1].RstEnOn_A	52714499	1055	0	0
gen_assertions[1].RstNOff_A	52714499	12582	0	0
gen_assertions[1].RstNOn_A	52714499	1055	0	0
gen_assertions[2].RstEnOff_A	26358064	12662	0	0
gen_assertions[2].RstEnOn_A	26358064	1078	0	0
gen_assertions[2].RstNOff_A	26358064	12662	0	0
gen_assertions[2].RstNOn_A	26358064	1078	0	0
gen_assertions[3].RstEnOff_A	26358073	12694	0	0
gen_assertions[3].RstEnOn_A	26358073	1099	0	0
gen_assertions[3].RstNOff_A	26358073	12694	0	0
gen_assertions[3].RstNOn_A	26358073	1099	0	0
gen_assertions[4].RstEnOff_A	1663042	21117	0	0
gen_assertions[4].RstEnOn_A	1663042	1153	0	0
gen_assertions[4].RstNOff_A	1663042	21117	0	0
gen_assertions[4].RstNOn_A	1663042	1153	0	0
gen_assertions[5].RstEnOff_A	13178728	14017	0	0
gen_assertions[5].RstEnOn_A	13178728	1192	0	0
gen_assertions[5].RstNOff_A	13178728	14017	0	0
gen_assertions[5].RstNOn_A	13178728	1192	0	0
gen_assertions[6].RstEnOff_A	13178728	14066	0	0
gen_assertions[6].RstEnOn_A	13178728	1242	0	0
gen_assertions[6].RstNOff_A	13178728	14066	0	0
gen_assertions[6].RstNOn_A	13178728	1242	0	0
gen_assertions[7].RstEnOff_A	13178728	14104	0	0
gen_assertions[7].RstEnOn_A	13178728	1285	0	0
gen_assertions[7].RstNOff_A	13178728	14104	0	0
gen_assertions[7].RstNOn_A	13178728	1285	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	13804	0	0
T1	2986	8	0	0
T2	84788	151	0	0
T3	56600	75	0	0
T4	152385	156	0	0
T5	5813	0	0	0
T6	3836	4	0	0
T7	34332	39	0	0
T8	40087	37	0	0
T9	29485	75	0	0
T10	46050	30	0	0
T11	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	1130	0	0
T1	2986	3	0	0
T2	84788	6	0	0
T3	56600	0	0	0
T4	152385	12	0	0
T5	5813	0	0	0
T6	3836	0	0	0
T7	34332	0	0	0
T8	40087	0	0	0
T9	29485	0	0	0
T10	46050	0	0	0
T24	0	2	0	0
T27	0	2	0	0
T55	0	1	0	0
T56	0	48	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	13804	0	0
T1	2986	8	0	0
T2	84788	151	0	0
T3	56600	75	0	0
T4	152385	156	0	0
T5	5813	0	0	0
T6	3836	4	0	0
T7	34332	39	0	0
T8	40087	37	0	0
T9	29485	75	0	0
T10	46050	30	0	0
T11	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	1130	0	0
T1	2986	3	0	0
T2	84788	6	0	0
T3	56600	0	0	0
T4	152385	12	0	0
T5	5813	0	0	0
T6	3836	0	0	0
T7	34332	0	0	0
T8	40087	0	0	0
T9	29485	0	0	0
T10	46050	0	0	0
T24	0	2	0	0
T27	0	2	0	0
T55	0	1	0	0
T56	0	48	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52714499	12582	0	0
T1	11945	8	0	0
T2	339167	140	0	0
T3	226407	68	0	0
T4	609493	141	0	0
T5	23253	0	0	0
T6	15346	4	0	0
T7	137326	35	0	0
T8	160339	34	0	0
T9	117935	69	0	0
T10	184187	27	0	0
T11	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52714499	1055	0	0
T2	339167	6	0	0
T3	226407	0	0	0
T4	609493	12	0	0
T5	23253	0	0	0
T6	15346	0	0	0
T7	137326	0	0	0
T8	160339	0	0	0
T9	117935	0	0	0
T10	184187	0	0	0
T11	11211	0	0	0
T27	0	3	0	0
T28	0	55	0	0
T40	0	1	0	0
T55	0	3	0	0
T56	0	40	0	0
T75	0	2	0	0
T98	0	23	0	0
T99	0	9	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52714499	12582	0	0
T1	11945	8	0	0
T2	339167	140	0	0
T3	226407	68	0	0
T4	609493	141	0	0
T5	23253	0	0	0
T6	15346	4	0	0
T7	137326	35	0	0
T8	160339	34	0	0
T9	117935	69	0	0
T10	184187	27	0	0
T11	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52714499	1055	0	0
T2	339167	6	0	0
T3	226407	0	0	0
T4	609493	12	0	0
T5	23253	0	0	0
T6	15346	0	0	0
T7	137326	0	0	0
T8	160339	0	0	0
T9	117935	0	0	0
T10	184187	0	0	0
T11	11211	0	0	0
T27	0	3	0	0
T28	0	55	0	0
T40	0	1	0	0
T55	0	3	0	0
T56	0	40	0	0
T75	0	2	0	0
T98	0	23	0	0
T99	0	9	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358064	12662	0	0
T1	5972	8	0	0
T2	169570	139	0	0
T3	113212	68	0	0
T4	304744	142	0	0
T5	11620	0	0	0
T6	7675	4	0	0
T7	68665	35	0	0
T8	80154	34	0	0
T9	58966	69	0	0
T10	92101	27	0	0
T11	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358064	1078	0	0
T2	169570	4	0	0
T3	113212	0	0	0
T4	304744	13	0	0
T5	11620	0	0	0
T6	7675	0	0	0
T7	68665	0	0	0
T8	80154	0	0	0
T9	58966	0	0	0
T10	92101	0	0	0
T11	5605	0	0	0
T27	0	4	0	0
T28	0	62	0	0
T41	0	7	0	0
T55	0	4	0	0
T56	0	45	0	0
T75	0	3	0	0
T98	0	19	0	0
T99	0	10	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358064	12662	0	0
T1	5972	8	0	0
T2	169570	139	0	0
T3	113212	68	0	0
T4	304744	142	0	0
T5	11620	0	0	0
T6	7675	4	0	0
T7	68665	35	0	0
T8	80154	34	0	0
T9	58966	69	0	0
T10	92101	27	0	0
T11	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358064	1078	0	0
T2	169570	4	0	0
T3	113212	0	0	0
T4	304744	13	0	0
T5	11620	0	0	0
T6	7675	0	0	0
T7	68665	0	0	0
T8	80154	0	0	0
T9	58966	0	0	0
T10	92101	0	0	0
T11	5605	0	0	0
T27	0	4	0	0
T28	0	62	0	0
T41	0	7	0	0
T55	0	4	0	0
T56	0	45	0	0
T75	0	3	0	0
T98	0	19	0	0
T99	0	10	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358073	12694	0	0
T1	5972	8	0	0
T2	169576	140	0	0
T3	113222	68	0	0
T4	304783	145	0	0
T5	11630	0	0	0
T6	7673	4	0	0
T7	68663	35	0	0
T8	80164	34	0	0
T9	58988	69	0	0
T10	92085	27	0	0
T11	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358073	1099	0	0
T2	169576	5	0	0
T3	113222	0	0	0
T4	304783	15	0	0
T5	11630	0	0	0
T6	7673	0	0	0
T7	68663	0	0	0
T8	80164	0	0	0
T9	58988	0	0	0
T10	92085	0	0	0
T11	5607	1	0	0
T27	0	6	0	0
T28	0	63	0	0
T55	0	5	0	0
T56	0	43	0	0
T75	0	4	0	0
T98	0	21	0	0
T99	0	11	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358073	12694	0	0
T1	5972	8	0	0
T2	169576	140	0	0
T3	113222	68	0	0
T4	304783	145	0	0
T5	11630	0	0	0
T6	7673	4	0	0
T7	68663	35	0	0
T8	80164	34	0	0
T9	58988	69	0	0
T10	92085	27	0	0
T11	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358073	1099	0	0
T2	169576	5	0	0
T3	113222	0	0	0
T4	304783	15	0	0
T5	11630	0	0	0
T6	7673	0	0	0
T7	68663	0	0	0
T8	80164	0	0	0
T9	58988	0	0	0
T10	92085	0	0	0
T11	5607	1	0	0
T27	0	6	0	0
T28	0	63	0	0
T55	0	5	0	0
T56	0	43	0	0
T75	0	4	0	0
T98	0	21	0	0
T99	0	11	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	21117	0	0
T1	372	9	0	0
T2	10821	213	0	0
T3	7090	98	0	0
T4	19316	232	0	0
T5	729	3	0	0
T6	478	6	0	0
T7	4364	54	0	0
T8	5061	59	0	0
T9	3701	77	0	0
T10	5792	53	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	1153	0	0
T2	10821	6	0	0
T3	7090	0	0	0
T4	19316	10	0	0
T5	729	0	0	0
T6	478	0	0	0
T7	4364	0	0	0
T8	5061	0	0	0
T9	3701	0	0	0
T10	5792	0	0	0
T11	349	0	0	0
T27	0	6	0	0
T28	0	62	0	0
T41	0	7	0	0
T55	0	6	0	0
T56	0	41	0	0
T75	0	5	0	0
T98	0	24	0	0
T99	0	9	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	21117	0	0
T1	372	9	0	0
T2	10821	213	0	0
T3	7090	98	0	0
T4	19316	232	0	0
T5	729	3	0	0
T6	478	6	0	0
T7	4364	54	0	0
T8	5061	59	0	0
T9	3701	77	0	0
T10	5792	53	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	1153	0	0
T2	10821	6	0	0
T3	7090	0	0	0
T4	19316	10	0	0
T5	729	0	0	0
T6	478	0	0	0
T7	4364	0	0	0
T8	5061	0	0	0
T9	3701	0	0	0
T10	5792	0	0	0
T11	349	0	0	0
T27	0	6	0	0
T28	0	62	0	0
T41	0	7	0	0
T55	0	6	0	0
T56	0	41	0	0
T75	0	5	0	0
T98	0	24	0	0
T99	0	9	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	14017	0	0
T1	2986	8	0	0
T2	84788	146	0	0
T3	56600	75	0	0
T4	152385	156	0	0
T5	5813	0	0	0
T6	3836	4	0	0
T7	34332	39	0	0
T8	40087	37	0	0
T9	29485	75	0	0
T10	46050	30	0	0
T11	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	1192	0	0
T2	84788	1	0	0
T3	56600	0	0	0
T4	152385	12	0	0
T5	5813	0	0	0
T6	3836	0	0	0
T7	34332	0	0	0
T8	40087	0	0	0
T9	29485	0	0	0
T10	46050	0	0	0
T11	2801	0	0	0
T27	0	6	0	0
T28	0	55	0	0
T41	0	7	0	0
T55	0	6	0	0
T56	0	41	0	0
T75	0	6	0	0
T98	0	28	0	0
T99	0	11	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	14017	0	0
T1	2986	8	0	0
T2	84788	146	0	0
T3	56600	75	0	0
T4	152385	156	0	0
T5	5813	0	0	0
T6	3836	4	0	0
T7	34332	39	0	0
T8	40087	37	0	0
T9	29485	75	0	0
T10	46050	30	0	0
T11	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	1192	0	0
T2	84788	1	0	0
T3	56600	0	0	0
T4	152385	12	0	0
T5	5813	0	0	0
T6	3836	0	0	0
T7	34332	0	0	0
T8	40087	0	0	0
T9	29485	0	0	0
T10	46050	0	0	0
T11	2801	0	0	0
T27	0	6	0	0
T28	0	55	0	0
T41	0	7	0	0
T55	0	6	0	0
T56	0	41	0	0
T75	0	6	0	0
T98	0	28	0	0
T99	0	11	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	14066	0	0
T1	2986	8	0	0
T2	84788	150	0	0
T3	56600	75	0	0
T4	152385	157	0	0
T5	5813	0	0	0
T6	3836	4	0	0
T7	34332	39	0	0
T8	40087	37	0	0
T9	29485	75	0	0
T10	46050	30	0	0
T11	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	1242	0	0
T2	84788	5	0	0
T3	56600	0	0	0
T4	152385	12	0	0
T5	5813	0	0	0
T6	3836	0	0	0
T7	34332	0	0	0
T8	40087	0	0	0
T9	29485	0	0	0
T10	46050	0	0	0
T11	2801	0	0	0
T27	0	7	0	0
T28	0	58	0	0
T41	0	9	0	0
T55	0	8	0	0
T56	0	40	0	0
T75	0	6	0	0
T98	0	23	0	0
T99	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	14066	0	0
T1	2986	8	0	0
T2	84788	150	0	0
T3	56600	75	0	0
T4	152385	157	0	0
T5	5813	0	0	0
T6	3836	4	0	0
T7	34332	39	0	0
T8	40087	37	0	0
T9	29485	75	0	0
T10	46050	30	0	0
T11	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	1242	0	0
T2	84788	5	0	0
T3	56600	0	0	0
T4	152385	12	0	0
T5	5813	0	0	0
T6	3836	0	0	0
T7	34332	0	0	0
T8	40087	0	0	0
T9	29485	0	0	0
T10	46050	0	0	0
T11	2801	0	0	0
T27	0	7	0	0
T28	0	58	0	0
T41	0	9	0	0
T55	0	8	0	0
T56	0	40	0	0
T75	0	6	0	0
T98	0	23	0	0
T99	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	14104	0	0
T1	2986	8	0	0
T2	84788	148	0	0
T3	56600	75	0	0
T4	152385	159	0	0
T5	5813	0	0	0
T6	3836	4	0	0
T7	34332	39	0	0
T8	40087	37	0	0
T9	29485	75	0	0
T10	46050	30	0	0
T11	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	1285	0	0
T2	84788	4	0	0
T3	56600	0	0	0
T4	152385	14	0	0
T5	5813	0	0	0
T6	3836	0	0	0
T7	34332	0	0	0
T8	40087	0	0	0
T9	29485	0	0	0
T10	46050	0	0	0
T11	2801	0	0	0
T27	0	10	0	0
T28	0	55	0	0
T41	0	9	0	0
T55	0	9	0	0
T56	0	43	0	0
T75	0	8	0	0
T98	0	26	0	0
T99	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	14104	0	0
T1	2986	8	0	0
T2	84788	148	0	0
T3	56600	75	0	0
T4	152385	159	0	0
T5	5813	0	0	0
T6	3836	4	0	0
T7	34332	39	0	0
T8	40087	37	0	0
T9	29485	75	0	0
T10	46050	30	0	0
T11	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	1285	0	0
T2	84788	4	0	0
T3	56600	0	0	0
T4	152385	14	0	0
T5	5813	0	0	0
T6	3836	0	0	0
T7	34332	0	0	0
T8	40087	0	0	0
T9	29485	0	0	0
T10	46050	0	0	0
T11	2801	0	0	0
T27	0	10	0	0
T28	0	55	0	0
T41	0	9	0	0
T55	0	9	0	0
T56	0	43	0	0
T75	0	8	0	0
T98	0	26	0	0
T99	0	10	0	0