Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12612470	15806	0	0
alert_regwen_rd_A	12612470	5066	0	0
cpu_regwen_rd_A	12612470	5324	0	0
sw_rst_ctrl_n_0_rd_A	12612470	10262	0	0
sw_rst_ctrl_n_1_rd_A	12612470	10295	0	0
sw_rst_ctrl_n_2_rd_A	12612470	10086	0	0
sw_rst_ctrl_n_3_rd_A	12612470	10410	0	0
sw_rst_ctrl_n_4_rd_A	12612470	10134	0	0
sw_rst_ctrl_n_5_rd_A	12612470	10537	0	0
sw_rst_ctrl_n_6_rd_A	12612470	10379	0	0
sw_rst_ctrl_n_7_rd_A	12612470	10543	0	0
sw_rst_regwen_0_rd_A	12612470	5447	0	0
sw_rst_regwen_1_rd_A	12612470	5754	0	0
sw_rst_regwen_2_rd_A	12612470	5752	0	0
sw_rst_regwen_3_rd_A	12612470	5909	0	0
sw_rst_regwen_4_rd_A	12612470	5785	0	0
sw_rst_regwen_5_rd_A	12612470	5541	0	0
sw_rst_regwen_6_rd_A	12612470	5760	0	0
sw_rst_regwen_7_rd_A	12612470	5601	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	15806	0	0
T80	19124	4	0	0
T81	6224	268	0	0
T82	12848	784	0	0
T83	4262	522	0	0
T100	5827	371	0	0
T101	16619	2	0	0
T102	11960	466	0	0
T103	14717	558	0	0
T104	6278	151	0	0
T105	10935	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5066	0	0
T10	40621	73	0	0
T11	2659	0	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T98	0	397	0	0
T112	0	193	0	0
T113	0	132	0	0
T118	0	59	0	0
T135	0	35	0	0
T136	0	30	0	0
T137	0	54	0	0
T138	0	408	0	0
T139	0	22	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5324	0	0
T10	40621	81	0	0
T11	2659	0	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T98	0	423	0	0
T112	0	196	0	0
T113	0	137	0	0
T118	0	77	0	0
T135	0	35	0	0
T136	0	13	0	0
T137	0	84	0	0
T138	0	476	0	0
T139	0	32	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	10262	0	0
T10	40621	79	0	0
T11	2659	0	0	0
T24	0	34	0	0
T27	0	148	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	37	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	98	0	0
T98	0	760	0	0
T112	0	436	0	0
T113	0	460	0	0
T140	0	13	0	0
T141	0	65	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	10295	0	0
T10	40621	95	0	0
T11	2659	0	0	0
T24	0	36	0	0
T27	0	123	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	42	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	60	0	0
T98	0	791	0	0
T112	0	500	0	0
T113	0	505	0	0
T140	0	21	0	0
T141	0	52	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	10086	0	0
T10	40621	91	0	0
T11	2659	0	0	0
T24	0	27	0	0
T27	0	161	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	40	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	55	0	0
T98	0	731	0	0
T112	0	481	0	0
T113	0	475	0	0
T140	0	20	0	0
T141	0	82	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	10410	0	0
T10	40621	71	0	0
T11	2659	0	0	0
T24	0	45	0	0
T27	0	138	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	35	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	80	0	0
T98	0	733	0	0
T112	0	420	0	0
T113	0	455	0	0
T140	0	16	0	0
T141	0	80	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	10134	0	0
T10	40621	66	0	0
T11	2659	0	0	0
T24	0	25	0	0
T27	0	148	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	39	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	80	0	0
T98	0	726	0	0
T112	0	488	0	0
T113	0	437	0	0
T140	0	17	0	0
T141	0	53	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	10537	0	0
T10	40621	102	0	0
T11	2659	0	0	0
T24	0	32	0	0
T27	0	133	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	48	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	66	0	0
T98	0	694	0	0
T112	0	443	0	0
T113	0	466	0	0
T140	0	16	0	0
T141	0	78	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	10379	0	0
T10	40621	98	0	0
T11	2659	0	0	0
T24	0	36	0	0
T27	0	131	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	40	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	134	0	0
T98	0	790	0	0
T112	0	468	0	0
T113	0	465	0	0
T140	0	12	0	0
T141	0	57	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	10543	0	0
T10	40621	112	0	0
T11	2659	0	0	0
T24	0	44	0	0
T27	0	125	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	35	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	97	0	0
T98	0	729	0	0
T112	0	455	0	0
T113	0	555	0	0
T140	0	19	0	0
T141	0	75	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5447	0	0
T10	40621	74	0	0
T11	2659	0	0	0
T27	0	39	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	11	0	0
T98	0	386	0	0
T112	0	221	0	0
T113	0	98	0	0
T140	0	2	0	0
T141	0	24	0	0
T142	0	7	0	0
T143	0	34	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5754	0	0
T10	40621	76	0	0
T11	2659	0	0	0
T27	0	29	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	25	0	0
T98	0	425	0	0
T112	0	195	0	0
T113	0	145	0	0
T140	0	4	0	0
T141	0	32	0	0
T142	0	10	0	0
T143	0	21	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5752	0	0
T10	40621	61	0	0
T11	2659	0	0	0
T27	0	35	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	19	0	0
T98	0	447	0	0
T112	0	159	0	0
T113	0	139	0	0
T140	0	6	0	0
T141	0	11	0	0
T142	0	3	0	0
T143	0	9	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5909	0	0
T10	40621	67	0	0
T11	2659	0	0	0
T27	0	19	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	15	0	0
T98	0	456	0	0
T112	0	175	0	0
T113	0	129	0	0
T140	0	12	0	0
T141	0	11	0	0
T142	0	17	0	0
T143	0	34	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5785	0	0
T10	40621	76	0	0
T11	2659	0	0	0
T27	0	26	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	19	0	0
T98	0	377	0	0
T112	0	218	0	0
T113	0	126	0	0
T140	0	11	0	0
T141	0	18	0	0
T142	0	6	0	0
T143	0	27	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5541	0	0
T10	40621	63	0	0
T11	2659	0	0	0
T27	0	24	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	12	0	0
T98	0	458	0	0
T112	0	200	0	0
T113	0	120	0	0
T140	0	8	0	0
T141	0	11	0	0
T142	0	8	0	0
T143	0	8	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5760	0	0
T10	40621	73	0	0
T11	2659	0	0	0
T27	0	41	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	15	0	0
T98	0	414	0	0
T112	0	171	0	0
T113	0	127	0	0
T140	0	15	0	0
T141	0	14	0	0
T142	0	6	0	0
T143	0	19	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12612470	5601	0	0
T10	40621	85	0	0
T11	2659	0	0	0
T27	0	45	0	0
T54	5693	0	0	0
T55	2767	0	0	0
T56	158712	0	0	0
T61	3892	0	0	0
T62	3358	0	0	0
T63	3701	0	0	0
T64	5277	0	0	0
T65	4406	0	0	0
T75	0	29	0	0
T98	0	419	0	0
T112	0	218	0	0
T113	0	102	0	0
T140	0	10	0	0
T141	0	22	0	0
T142	0	9	0	0
T143	0	26	0	0