Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T7

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54912806	8439	0	0
CascadeEffAonToRstPorAboveRise_A	54912806	8439	0	0
CascadeEffAonToRstPorIoAboveFall_A	52714499	8439	0	0
CascadeEffAonToRstPorIoAboveRise_A	52714499	8439	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26358064	8439	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26358064	8439	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13178728	8439	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13178728	8439	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26358073	8439	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26358073	8439	0	0
CascadeLcToLcAboveFall_A	54912806	21297	0	0
CascadeLcToLcAboveRise_A	54912806	21297	0	0
CascadeLcToLcAonAboveFall_A	1663042	21297	0	0
CascadeLcToLcAonAboveRise_A	1663042	21297	0	0
CascadeLcToLcShadowedAboveFall_A	54912806	21297	0	0
CascadeLcToLcShadowedAboveRise_A	54912806	21297	0	0
CascadePorToAonAboveFall_A	1663042	6766	0	0
CascadeSysToSysAboveFall_A	54912806	21297	0	0
CascadeSysToSysAboveRise_A	54912806	21297	0	0
ScanRstToAonRise_A	1663042	221	0	0
StablePorToAonRise_A	1663042	8439	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11779012	21297	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11779012	21297	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11779012	21297	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11779012	21297	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13178728	21297	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13178728	21297	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11779012	21297	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11779012	21297	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11779012	21297	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11779012	21297	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54912806	8439	0	0
T1	12443	1	0	0
T2	353287	69	0	0
T3	235858	27	0	0
T4	634873	82	0	0
T5	24224	8	0	0
T6	15988	2	0	0
T7	143058	17	0	0
T8	167014	23	0	0
T9	122850	27	0	0
T10	191877	23	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54912806	8439	0	0
T1	12443	1	0	0
T2	353287	69	0	0
T3	235858	27	0	0
T4	634873	82	0	0
T5	24224	8	0	0
T6	15988	2	0	0
T7	143058	17	0	0
T8	167014	23	0	0
T9	122850	27	0	0
T10	191877	23	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52714499	8439	0	0
T1	11945	1	0	0
T2	339167	69	0	0
T3	226407	27	0	0
T4	609493	82	0	0
T5	23253	8	0	0
T6	15346	2	0	0
T7	137326	17	0	0
T8	160339	23	0	0
T9	117935	27	0	0
T10	184187	23	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52714499	8439	0	0
T1	11945	1	0	0
T2	339167	69	0	0
T3	226407	27	0	0
T4	609493	82	0	0
T5	23253	8	0	0
T6	15346	2	0	0
T7	137326	17	0	0
T8	160339	23	0	0
T9	117935	27	0	0
T10	184187	23	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358064	8439	0	0
T1	5972	1	0	0
T2	169570	69	0	0
T3	113212	27	0	0
T4	304744	82	0	0
T5	11620	8	0	0
T6	7675	2	0	0
T7	68665	17	0	0
T8	80154	23	0	0
T9	58966	27	0	0
T10	92101	23	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358064	8439	0	0
T1	5972	1	0	0
T2	169570	69	0	0
T3	113212	27	0	0
T4	304744	82	0	0
T5	11620	8	0	0
T6	7675	2	0	0
T7	68665	17	0	0
T8	80154	23	0	0
T9	58966	27	0	0
T10	92101	23	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	8439	0	0
T1	2986	1	0	0
T2	84788	69	0	0
T3	56600	27	0	0
T4	152385	82	0	0
T5	5813	8	0	0
T6	3836	2	0	0
T7	34332	17	0	0
T8	40087	23	0	0
T9	29485	27	0	0
T10	46050	23	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	8439	0	0
T1	2986	1	0	0
T2	84788	69	0	0
T3	56600	27	0	0
T4	152385	82	0	0
T5	5813	8	0	0
T6	3836	2	0	0
T7	34332	17	0	0
T8	40087	23	0	0
T9	29485	27	0	0
T10	46050	23	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358073	8439	0	0
T1	5972	1	0	0
T2	169576	69	0	0
T3	113222	27	0	0
T4	304783	82	0	0
T5	11630	8	0	0
T6	7673	2	0	0
T7	68663	17	0	0
T8	80164	23	0	0
T9	58988	27	0	0
T10	92085	23	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26358073	8439	0	0
T1	5972	1	0	0
T2	169576	69	0	0
T3	113222	27	0	0
T4	304783	82	0	0
T5	11630	8	0	0
T6	7673	2	0	0
T7	68663	17	0	0
T8	80164	23	0	0
T9	58988	27	0	0
T10	92085	23	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54912806	21297	0	0
T1	12443	9	0	0
T2	353287	214	0	0
T3	235858	102	0	0
T4	634873	227	0	0
T5	24224	8	0	0
T6	15988	6	0	0
T7	143058	56	0	0
T8	167014	60	0	0
T9	122850	102	0	0
T10	191877	53	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54912806	21297	0	0
T1	12443	9	0	0
T2	353287	214	0	0
T3	235858	102	0	0
T4	634873	227	0	0
T5	24224	8	0	0
T6	15988	6	0	0
T7	143058	56	0	0
T8	167014	60	0	0
T9	122850	102	0	0
T10	191877	53	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	21297	0	0
T1	372	9	0	0
T2	10821	214	0	0
T3	7090	102	0	0
T4	19316	227	0	0
T5	729	8	0	0
T6	478	6	0	0
T7	4364	56	0	0
T8	5061	60	0	0
T9	3701	102	0	0
T10	5792	53	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	21297	0	0
T1	372	9	0	0
T2	10821	214	0	0
T3	7090	102	0	0
T4	19316	227	0	0
T5	729	8	0	0
T6	478	6	0	0
T7	4364	56	0	0
T8	5061	60	0	0
T9	3701	102	0	0
T10	5792	53	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54912806	21297	0	0
T1	12443	9	0	0
T2	353287	214	0	0
T3	235858	102	0	0
T4	634873	227	0	0
T5	24224	8	0	0
T6	15988	6	0	0
T7	143058	56	0	0
T8	167014	60	0	0
T9	122850	102	0	0
T10	191877	53	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54912806	21297	0	0
T1	12443	9	0	0
T2	353287	214	0	0
T3	235858	102	0	0
T4	634873	227	0	0
T5	24224	8	0	0
T6	15988	6	0	0
T7	143058	56	0	0
T8	167014	60	0	0
T9	122850	102	0	0
T10	191877	53	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	6766	0	0
T1	372	1	0	0
T2	10821	35	0	0
T3	7090	27	0	0
T4	19316	42	0	0
T5	729	8	0	0
T6	478	1	0	0
T7	4364	10	0	0
T8	5061	13	0	0
T9	3701	27	0	0
T10	5792	14	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54912806	21297	0	0
T1	12443	9	0	0
T2	353287	214	0	0
T3	235858	102	0	0
T4	634873	227	0	0
T5	24224	8	0	0
T6	15988	6	0	0
T7	143058	56	0	0
T8	167014	60	0	0
T9	122850	102	0	0
T10	191877	53	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54912806	21297	0	0
T1	12443	9	0	0
T2	353287	214	0	0
T3	235858	102	0	0
T4	634873	227	0	0
T5	24224	8	0	0
T6	15988	6	0	0
T7	143058	56	0	0
T8	167014	60	0	0
T9	122850	102	0	0
T10	191877	53	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	221	0	0
T2	10821	3	0	0
T3	7090	0	0	0
T4	19316	2	0	0
T5	729	0	0	0
T6	478	0	0	0
T7	4364	1	0	0
T8	5061	1	0	0
T9	3701	0	0	0
T10	5792	0	0	0
T11	349	0	0	0
T28	0	10	0	0
T56	0	2	0	0
T98	0	3	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1663042	8439	0	0
T1	372	1	0	0
T2	10821	69	0	0
T3	7090	27	0	0
T4	19316	82	0	0
T5	729	8	0	0
T6	478	2	0	0
T7	4364	17	0	0
T8	5061	23	0	0
T9	3701	27	0	0
T10	5792	23	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11779012	21297	0	0
T1	2584	9	0	0
T2	67320	214	0	0
T3	53349	102	0	0
T4	133525	227	0	0
T5	5075	8	0	0
T6	3689	6	0	0
T7	29422	56	0	0
T8	34418	60	0	0
T9	26046	102	0	0
T10	40621	53	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11779012	21297	0	0
T1	2584	9	0	0
T2	67320	214	0	0
T3	53349	102	0	0
T4	133525	227	0	0
T5	5075	8	0	0
T6	3689	6	0	0
T7	29422	56	0	0
T8	34418	60	0	0
T9	26046	102	0	0
T10	40621	53	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11779012	21297	0	0
T1	2584	9	0	0
T2	67320	214	0	0
T3	53349	102	0	0
T4	133525	227	0	0
T5	5075	8	0	0
T6	3689	6	0	0
T7	29422	56	0	0
T8	34418	60	0	0
T9	26046	102	0	0
T10	40621	53	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11779012	21297	0	0
T1	2584	9	0	0
T2	67320	214	0	0
T3	53349	102	0	0
T4	133525	227	0	0
T5	5075	8	0	0
T6	3689	6	0	0
T7	29422	56	0	0
T8	34418	60	0	0
T9	26046	102	0	0
T10	40621	53	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	21297	0	0
T1	2986	9	0	0
T2	84788	214	0	0
T3	56600	102	0	0
T4	152385	227	0	0
T5	5813	8	0	0
T6	3836	6	0	0
T7	34332	56	0	0
T8	40087	60	0	0
T9	29485	102	0	0
T10	46050	53	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13178728	21297	0	0
T1	2986	9	0	0
T2	84788	214	0	0
T3	56600	102	0	0
T4	152385	227	0	0
T5	5813	8	0	0
T6	3836	6	0	0
T7	34332	56	0	0
T8	40087	60	0	0
T9	29485	102	0	0
T10	46050	53	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11779012	21297	0	0
T1	2584	9	0	0
T2	67320	214	0	0
T3	53349	102	0	0
T4	133525	227	0	0
T5	5075	8	0	0
T6	3689	6	0	0
T7	29422	56	0	0
T8	34418	60	0	0
T9	26046	102	0	0
T10	40621	53	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11779012	21297	0	0
T1	2584	9	0	0
T2	67320	214	0	0
T3	53349	102	0	0
T4	133525	227	0	0
T5	5075	8	0	0
T6	3689	6	0	0
T7	29422	56	0	0
T8	34418	60	0	0
T9	26046	102	0	0
T10	40621	53	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11779012	21297	0	0
T1	2584	9	0	0
T2	67320	214	0	0
T3	53349	102	0	0
T4	133525	227	0	0
T5	5075	8	0	0
T6	3689	6	0	0
T7	29422	56	0	0
T8	34418	60	0	0
T9	26046	102	0	0
T10	40621	53	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11779012	21297	0	0
T1	2584	9	0	0
T2	67320	214	0	0
T3	53349	102	0	0
T4	133525	227	0	0
T5	5075	8	0	0
T6	3689	6	0	0
T7	29422	56	0	0
T8	34418	60	0	0
T9	26046	102	0	0
T10	40621	53	0	0