Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	618309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

372292

1

T2

3

T3

78

T4

153

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	528191	1			T1	1		T3	99		T4	186
values[0x0]	231046	1			T2	15		T3	61		T4	103
values[0x1]	231364	1			T2	15		T3	46		T4	90

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	518976	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

471625

1

T1

1

T2

5

T3

91

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6038	1			T4	1		T6	20		T9	6
valid_sources[0x01]	6582	1			T3	3		T4	1		T6	13
valid_sources[0x02]	4203	1			T4	3		T6	7		T8	9
valid_sources[0x03]	3502	1			T3	1		T4	1		T6	8
valid_sources[0x04]	3304	1			T4	3		T6	6		T7	1
valid_sources[0x05]	7743	1			T6	11		T8	20		T9	1
valid_sources[0x06]	2962	1			T6	15		T9	3		T51	6
valid_sources[0x07]	3273	1			T4	1		T6	16		T9	3
valid_sources[0x08]	3689	1			T4	5		T6	17		T8	2
valid_sources[0x09]	2980	1			T3	2		T4	1		T6	10
valid_sources[0x0a]	3917	1			T2	2		T4	2		T6	7
valid_sources[0x0b]	3321	1			T6	22		T9	1		T10	6
valid_sources[0x0c]	3140	1			T4	7		T6	19		T8	18
valid_sources[0x0d]	3122	1			T4	2		T6	9		T9	2
valid_sources[0x0e]	4034	1			T4	2		T6	17		T8	25
valid_sources[0x0f]	3659	1			T3	1		T4	1		T6	10
valid_sources[0x10]	2778	1			T6	10		T9	1		T23	64
valid_sources[0x11]	3266	1			T4	3		T6	30		T8	2
valid_sources[0x12]	3539	1			T2	1		T4	1		T6	13
valid_sources[0x13]	3521	1			T6	21		T9	4		T56	5
valid_sources[0x14]	3506	1			T3	3		T4	1		T6	7
valid_sources[0x15]	2931	1			T3	1		T6	13		T9	4
valid_sources[0x16]	4005	1			T4	1		T6	17		T9	6
valid_sources[0x17]	3671	1			T3	7		T4	1		T6	13
valid_sources[0x18]	3248	1			T3	2		T4	3		T6	7
valid_sources[0x19]	3660	1			T2	1		T6	5		T9	5
valid_sources[0x1a]	4251	1			T3	1		T4	4		T6	27
valid_sources[0x1b]	3779	1			T3	5		T4	1		T6	17
valid_sources[0x1c]	3603	1			T4	3		T6	13		T9	3
valid_sources[0x1d]	3252	1			T6	10		T9	3		T23	2
valid_sources[0x1e]	5174	1			T4	1		T6	20		T8	4
valid_sources[0x1f]	4229	1			T6	14		T9	4		T23	237
valid_sources[0x20]	3004	1			T4	2		T6	7		T9	2
valid_sources[0x21]	3618	1			T4	1		T6	16		T9	7
valid_sources[0x22]	4143	1			T4	1		T6	20		T9	5
valid_sources[0x23]	3156	1			T6	12		T9	1		T51	6
valid_sources[0x24]	3095	1			T4	2		T6	8		T9	5
valid_sources[0x25]	5343	1			T3	1		T4	5		T6	7
valid_sources[0x26]	3374	1			T3	2		T4	1		T6	8
valid_sources[0x27]	3444	1			T2	1		T3	5		T6	5
valid_sources[0x28]	3522	1			T3	3		T6	23		T9	3
valid_sources[0x29]	3435	1			T6	7		T9	3		T22	566
valid_sources[0x2a]	3328	1			T3	10		T4	2		T6	6
valid_sources[0x2b]	3505	1			T3	1		T4	1		T6	4
valid_sources[0x2c]	3345	1			T2	1		T4	1		T6	21
valid_sources[0x2d]	3158	1			T4	1		T6	18		T9	4
valid_sources[0x2e]	4410	1			T4	4		T6	13		T23	116
valid_sources[0x2f]	3646	1			T3	6		T4	1		T6	16
valid_sources[0x30]	3214	1			T6	20		T8	10		T9	4
valid_sources[0x31]	3590	1			T4	1		T6	14		T9	2
valid_sources[0x32]	3087	1			T4	1		T6	10		T8	2
valid_sources[0x33]	3877	1			T3	4		T6	6		T9	3
valid_sources[0x34]	3735	1			T4	1		T6	15		T9	5
valid_sources[0x35]	2876	1			T4	2		T6	2		T8	3
valid_sources[0x36]	4088	1			T3	3		T6	10		T9	4
valid_sources[0x37]	4520	1			T2	1		T4	1		T6	13
valid_sources[0x38]	3045	1			T3	7		T4	1		T6	7
valid_sources[0x39]	3151	1			T3	1		T6	9		T9	2
valid_sources[0x3a]	3166	1			T4	2		T6	15		T9	3
valid_sources[0x3b]	4192	1			T4	1		T6	19		T9	1
valid_sources[0x3c]	3156	1			T4	1		T6	11		T10	2
valid_sources[0x3d]	3441	1			T2	1		T4	1		T6	7
valid_sources[0x3e]	3563	1			T4	3		T6	5		T9	2
valid_sources[0x3f]	6367	1			T6	11		T9	5		T11	6
valid_sources[0x40]	3705	1			T4	1		T6	14		T9	1
valid_sources[0x41]	3164	1			T4	2		T6	18		T9	2
valid_sources[0x42]	5777	1			T4	1		T6	11		T9	2
valid_sources[0x43]	3113	1			T4	4		T6	11		T8	9
valid_sources[0x44]	3500	1			T4	4		T6	18		T8	7
valid_sources[0x45]	3467	1			T6	10		T9	3		T23	197
valid_sources[0x46]	3357	1			T4	1		T6	16		T9	7
valid_sources[0x47]	3072	1			T4	4		T6	4		T9	3
valid_sources[0x48]	3623	1			T4	3		T6	20		T9	2
valid_sources[0x49]	3585	1			T6	5		T9	1		T23	112
valid_sources[0x4a]	3373	1			T3	6		T4	3		T6	15
valid_sources[0x4b]	4204	1			T4	2		T6	19		T8	2
valid_sources[0x4c]	3293	1			T6	12		T23	70		T25	11
valid_sources[0x4d]	4018	1			T3	2		T4	2		T6	7
valid_sources[0x4e]	3580	1			T4	1		T6	12		T9	3
valid_sources[0x4f]	2956	1			T4	1		T6	4		T9	1
valid_sources[0x50]	3807	1			T4	3		T6	18		T9	6
valid_sources[0x51]	3083	1			T4	1		T6	4		T9	5
valid_sources[0x52]	3703	1			T4	1		T6	14		T9	4
valid_sources[0x53]	3661	1			T3	9		T4	1		T6	13
valid_sources[0x54]	2953	1			T4	3		T6	17		T9	1
valid_sources[0x55]	3667	1			T4	1		T6	11		T8	3
valid_sources[0x56]	3767	1			T4	1		T6	9		T8	31
valid_sources[0x57]	4083	1			T3	13		T4	3		T6	8
valid_sources[0x58]	3598	1			T4	5		T6	10		T9	5
valid_sources[0x59]	4014	1			T4	3		T6	9		T9	8
valid_sources[0x5a]	3937	1			T6	11		T9	2		T11	2
valid_sources[0x5b]	5115	1			T4	1		T6	21		T9	3
valid_sources[0x5c]	3813	1			T6	7		T9	3		T11	1
valid_sources[0x5d]	4356	1			T6	16		T9	6		T11	3
valid_sources[0x5e]	3488	1			T4	1		T6	15		T9	3
valid_sources[0x5f]	3436	1			T6	16		T9	5		T22	156
valid_sources[0x60]	3367	1			T4	1		T6	16		T9	1
valid_sources[0x61]	4072	1			T6	3		T11	1		T23	198
valid_sources[0x62]	3652	1			T6	17		T9	6		T11	3
valid_sources[0x63]	3736	1			T3	1		T4	1		T6	16
valid_sources[0x64]	3533	1			T4	1		T6	17		T9	6
valid_sources[0x65]	4196	1			T4	1		T6	11		T9	2
valid_sources[0x66]	3129	1			T6	9		T9	1		T23	147
valid_sources[0x67]	3539	1			T6	18		T9	4		T51	2
valid_sources[0x68]	3169	1			T4	1		T6	10		T9	4
valid_sources[0x69]	3961	1			T4	3		T6	8		T9	2
valid_sources[0x6a]	7785	1			T2	1		T4	2		T6	13
valid_sources[0x6b]	4122	1			T4	3		T6	12		T9	4
valid_sources[0x6c]	4351	1			T3	1		T4	2		T6	15
valid_sources[0x6d]	3283	1			T4	2		T6	20		T9	6
valid_sources[0x6e]	3258	1			T4	1		T6	16		T8	3
valid_sources[0x6f]	4278	1			T4	1		T6	8		T9	8
valid_sources[0x70]	4246	1			T3	2		T6	9		T9	3
valid_sources[0x71]	3782	1			T4	4		T6	9		T9	3
valid_sources[0x72]	3462	1			T6	6		T9	1		T11	3
valid_sources[0x73]	4357	1			T2	1		T6	22		T9	2
valid_sources[0x74]	3654	1			T4	1		T6	8		T9	4
valid_sources[0x75]	4367	1			T4	3		T6	16		T9	2
valid_sources[0x76]	3774	1			T6	2		T9	3		T11	1
valid_sources[0x77]	3232	1			T6	8		T8	11		T9	3
valid_sources[0x78]	3853	1			T6	11		T8	18		T9	1
valid_sources[0x79]	6867	1			T4	4		T6	20		T9	4
valid_sources[0x7a]	4573	1			T4	2		T6	15		T9	2
valid_sources[0x7b]	7333	1			T4	2		T6	8		T9	4
valid_sources[0x7c]	3214	1			T3	2		T4	1		T6	22
valid_sources[0x7d]	4046	1			T3	3		T6	18		T9	2
valid_sources[0x7e]	3712	1			T2	1		T4	1		T6	11
valid_sources[0x7f]	3911	1			T3	2		T6	14		T8	2
valid_sources[0x80]	3539	1			T6	14		T9	4		T51	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

247517

1

T3

46

T4

93

T6

690

values[0x0]

all_enables

biggest_size

81335

1

T2

3

T3

22

T4

40

values[0x1]

all_enables

biggest_size

43440

1

T3

10

T4

20

T6

113