Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T22,T23
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T13
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T13,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T22,T23
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13109261	14113	0	0
gen_assertions[0].RstEnOn_A	13109261	1101	0	0
gen_assertions[0].RstNOff_A	13109261	14113	0	0
gen_assertions[0].RstNOn_A	13109261	1101	0	0
gen_assertions[1].RstEnOff_A	52435776	12836	0	0
gen_assertions[1].RstEnOn_A	52435776	1039	0	0
gen_assertions[1].RstNOff_A	52435776	12836	0	0
gen_assertions[1].RstNOn_A	52435776	1039	0	0
gen_assertions[2].RstEnOff_A	26219054	12892	0	0
gen_assertions[2].RstEnOn_A	26219054	1046	0	0
gen_assertions[2].RstNOff_A	26219054	12892	0	0
gen_assertions[2].RstNOn_A	26219054	1046	0	0
gen_assertions[3].RstEnOff_A	26218988	12939	0	0
gen_assertions[3].RstEnOn_A	26218988	1083	0	0
gen_assertions[3].RstNOff_A	26218988	12939	0	0
gen_assertions[3].RstNOn_A	26218988	1083	0	0
gen_assertions[4].RstEnOff_A	1655278	21423	0	0
gen_assertions[4].RstEnOn_A	1655278	1119	0	0
gen_assertions[4].RstNOff_A	1655278	21423	0	0
gen_assertions[4].RstNOn_A	1655278	1119	0	0
gen_assertions[5].RstEnOff_A	13109261	14321	0	0
gen_assertions[5].RstEnOn_A	13109261	1153	0	0
gen_assertions[5].RstNOff_A	13109261	14321	0	0
gen_assertions[5].RstNOn_A	13109261	1153	0	0
gen_assertions[6].RstEnOff_A	13109261	14403	0	0
gen_assertions[6].RstEnOn_A	13109261	1236	0	0
gen_assertions[6].RstNOff_A	13109261	14403	0	0
gen_assertions[6].RstNOn_A	13109261	1236	0	0
gen_assertions[7].RstEnOff_A	13109261	14466	0	0
gen_assertions[7].RstEnOn_A	13109261	1296	0	0
gen_assertions[7].RstNOff_A	13109261	14466	0	0
gen_assertions[7].RstNOn_A	13109261	1296	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	14113	0	0
T3	3810	11	0	0
T4	5593	4	0	0
T5	5825	0	0	0
T6	29312	75	0	0
T7	2608	0	0	0
T8	5957	5	0	0
T9	7436	2	0	0
T10	2906	8	0	0
T11	2265	4	0	0
T12	0	4	0	0
T13	0	5	0	0
T22	0	228	0	0
T24	2057	0	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	1101	0	0
T3	3810	1	0	0
T4	5593	0	0	0
T5	5825	0	0	0
T6	29312	0	0	0
T7	2608	0	0	0
T8	5957	1	0	0
T9	7436	2	0	0
T10	2906	3	0	0
T11	2265	0	0	0
T13	0	1	0	0
T22	0	22	0	0
T23	0	26	0	0
T24	2057	0	0	0
T40	0	6	0	0
T41	0	2	0	0
T51	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	14113	0	0
T3	3810	11	0	0
T4	5593	4	0	0
T5	5825	0	0	0
T6	29312	75	0	0
T7	2608	0	0	0
T8	5957	5	0	0
T9	7436	2	0	0
T10	2906	8	0	0
T11	2265	4	0	0
T12	0	4	0	0
T13	0	5	0	0
T22	0	228	0	0
T24	2057	0	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	1101	0	0
T3	3810	1	0	0
T4	5593	0	0	0
T5	5825	0	0	0
T6	29312	0	0	0
T7	2608	0	0	0
T8	5957	1	0	0
T9	7436	2	0	0
T10	2906	3	0	0
T11	2265	0	0	0
T13	0	1	0	0
T22	0	22	0	0
T23	0	26	0	0
T24	2057	0	0	0
T40	0	6	0	0
T41	0	2	0	0
T51	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52435776	12836	0	0
T3	15246	10	0	0
T4	22373	3	0	0
T5	23307	0	0	0
T6	117234	61	0	0
T7	10433	0	0	0
T8	23827	3	0	0
T9	29746	2	0	0
T10	11628	7	0	0
T11	9065	3	0	0
T12	0	4	0	0
T13	0	3	0	0
T22	0	211	0	0
T24	8230	0	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52435776	1039	0	0
T9	29746	2	0	0
T10	11628	0	0	0
T11	9065	0	0	0
T12	17641	0	0	0
T13	11647	0	0	0
T22	893048	19	0	0
T23	140140	26	0	0
T24	8230	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T47	0	5	0	0
T51	38691	5	0	0
T56	10635	1	0	0
T77	0	1	0	0
T78	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52435776	12836	0	0
T3	15246	10	0	0
T4	22373	3	0	0
T5	23307	0	0	0
T6	117234	61	0	0
T7	10433	0	0	0
T8	23827	3	0	0
T9	29746	2	0	0
T10	11628	7	0	0
T11	9065	3	0	0
T12	0	4	0	0
T13	0	3	0	0
T22	0	211	0	0
T24	8230	0	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52435776	1039	0	0
T9	29746	2	0	0
T10	11628	0	0	0
T11	9065	0	0	0
T12	17641	0	0	0
T13	11647	0	0	0
T22	893048	19	0	0
T23	140140	26	0	0
T24	8230	0	0	0
T40	0	5	0	0
T41	0	4	0	0
T47	0	5	0	0
T51	38691	5	0	0
T56	10635	1	0	0
T77	0	1	0	0
T78	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26219054	12892	0	0
T3	7622	10	0	0
T4	11186	3	0	0
T5	11651	0	0	0
T6	58641	61	0	0
T7	5217	0	0	0
T8	11912	4	0	0
T9	14873	6	0	0
T10	5813	7	0	0
T11	4533	3	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	213	0	0
T24	4114	0	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26219054	1046	0	0
T8	11912	1	0	0
T9	14873	6	0	0
T10	5813	0	0	0
T11	4533	0	0	0
T12	8819	0	0	0
T13	5818	1	0	0
T22	446514	22	0	0
T23	700718	20	0	0
T24	4114	0	0	0
T40	0	9	0	0
T41	0	3	0	0
T47	0	8	0	0
T51	19346	7	0	0
T77	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26219054	12892	0	0
T3	7622	10	0	0
T4	11186	3	0	0
T5	11651	0	0	0
T6	58641	61	0	0
T7	5217	0	0	0
T8	11912	4	0	0
T9	14873	6	0	0
T10	5813	7	0	0
T11	4533	3	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	213	0	0
T24	4114	0	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26219054	1046	0	0
T8	11912	1	0	0
T9	14873	6	0	0
T10	5813	0	0	0
T11	4533	0	0	0
T12	8819	0	0	0
T13	5818	1	0	0
T22	446514	22	0	0
T23	700718	20	0	0
T24	4114	0	0	0
T40	0	9	0	0
T41	0	3	0	0
T47	0	8	0	0
T51	19346	7	0	0
T77	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26218988	12939	0	0
T3	7622	10	0	0
T4	11183	4	0	0
T5	11656	0	0	0
T6	58609	61	0	0
T7	5216	0	0	0
T8	11914	4	0	0
T9	14873	6	0	0
T10	5813	7	0	0
T11	4532	3	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	211	0	0
T24	4115	0	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26218988	1083	0	0
T4	11183	1	0	0
T5	11656	0	0	0
T6	58609	0	0	0
T7	5216	0	0	0
T8	11914	1	0	0
T9	14873	6	0	0
T10	5813	0	0	0
T11	4532	0	0	0
T12	8821	0	0	0
T13	0	1	0	0
T22	0	21	0	0
T23	0	30	0	0
T24	4115	0	0	0
T40	0	10	0	0
T41	0	6	0	0
T47	0	9	0	0
T51	0	9	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26218988	12939	0	0
T3	7622	10	0	0
T4	11183	4	0	0
T5	11656	0	0	0
T6	58609	61	0	0
T7	5216	0	0	0
T8	11914	4	0	0
T9	14873	6	0	0
T10	5813	7	0	0
T11	4532	3	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	211	0	0
T24	4115	0	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26218988	1083	0	0
T4	11183	1	0	0
T5	11656	0	0	0
T6	58609	0	0	0
T7	5216	0	0	0
T8	11914	1	0	0
T9	14873	6	0	0
T10	5813	0	0	0
T11	4532	0	0	0
T12	8821	0	0	0
T13	0	1	0	0
T22	0	21	0	0
T23	0	30	0	0
T24	4115	0	0	0
T40	0	10	0	0
T41	0	6	0	0
T47	0	9	0	0
T51	0	9	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	21423	0	0
T1	529	2	0	0
T2	234	1	0	0
T3	474	12	0	0
T4	697	5	0	0
T5	730	3	0	0
T6	3678	74	0	0
T7	325	2	0	0
T8	743	5	0	0
T9	928	9	0	0
T10	362	9	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	1119	0	0
T9	928	8	0	0
T10	362	0	0	0
T11	282	0	0	0
T12	551	0	0	0
T13	363	1	0	0
T22	28244	19	0	0
T23	44416	32	0	0
T24	256	0	0	0
T40	0	11	0	0
T41	0	6	0	0
T47	0	7	0	0
T51	1207	9	0	0
T56	331	0	0	0
T79	0	4	0	0
T80	0	24	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	21423	0	0
T1	529	2	0	0
T2	234	1	0	0
T3	474	12	0	0
T4	697	5	0	0
T5	730	3	0	0
T6	3678	74	0	0
T7	325	2	0	0
T8	743	5	0	0
T9	928	9	0	0
T10	362	9	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	1119	0	0
T9	928	8	0	0
T10	362	0	0	0
T11	282	0	0	0
T12	551	0	0	0
T13	363	1	0	0
T22	28244	19	0	0
T23	44416	32	0	0
T24	256	0	0	0
T40	0	11	0	0
T41	0	6	0	0
T47	0	7	0	0
T51	1207	9	0	0
T56	331	0	0	0
T79	0	4	0	0
T80	0	24	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	14321	0	0
T3	3810	11	0	0
T4	5593	5	0	0
T5	5825	0	0	0
T6	29312	75	0	0
T7	2608	0	0	0
T8	5957	4	0	0
T9	7436	9	0	0
T10	2906	8	0	0
T11	2265	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	230	0	0
T24	2057	0	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	1153	0	0
T4	5593	1	0	0
T5	5825	0	0	0
T6	29312	0	0	0
T7	2608	0	0	0
T8	5957	0	0	0
T9	7436	9	0	0
T10	2906	0	0	0
T11	2265	0	0	0
T12	4409	0	0	0
T22	0	21	0	0
T23	0	22	0	0
T24	2057	0	0	0
T40	0	13	0	0
T41	0	6	0	0
T47	0	11	0	0
T51	0	9	0	0
T56	0	1	0	0
T81	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	14321	0	0
T3	3810	11	0	0
T4	5593	5	0	0
T5	5825	0	0	0
T6	29312	75	0	0
T7	2608	0	0	0
T8	5957	4	0	0
T9	7436	9	0	0
T10	2906	8	0	0
T11	2265	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	230	0	0
T24	2057	0	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	1153	0	0
T4	5593	1	0	0
T5	5825	0	0	0
T6	29312	0	0	0
T7	2608	0	0	0
T8	5957	0	0	0
T9	7436	9	0	0
T10	2906	0	0	0
T11	2265	0	0	0
T12	4409	0	0	0
T22	0	21	0	0
T23	0	22	0	0
T24	2057	0	0	0
T40	0	13	0	0
T41	0	6	0	0
T47	0	11	0	0
T51	0	9	0	0
T56	0	1	0	0
T81	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	14403	0	0
T3	3810	11	0	0
T4	5593	4	0	0
T5	5825	0	0	0
T6	29312	75	0	0
T7	2608	0	0	0
T8	5957	5	0	0
T9	7436	10	0	0
T10	2906	8	0	0
T11	2265	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	226	0	0
T24	2057	0	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	1236	0	0
T8	5957	1	0	0
T9	7436	10	0	0
T10	2906	0	0	0
T11	2265	0	0	0
T12	4409	0	0	0
T13	2910	0	0	0
T22	223269	16	0	0
T23	350373	29	0	0
T24	2057	0	0	0
T39	0	1	0	0
T40	0	13	0	0
T41	0	7	0	0
T47	0	10	0	0
T51	9672	11	0	0
T82	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	14403	0	0
T3	3810	11	0	0
T4	5593	4	0	0
T5	5825	0	0	0
T6	29312	75	0	0
T7	2608	0	0	0
T8	5957	5	0	0
T9	7436	10	0	0
T10	2906	8	0	0
T11	2265	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	226	0	0
T24	2057	0	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	1236	0	0
T8	5957	1	0	0
T9	7436	10	0	0
T10	2906	0	0	0
T11	2265	0	0	0
T12	4409	0	0	0
T13	2910	0	0	0
T22	223269	16	0	0
T23	350373	29	0	0
T24	2057	0	0	0
T39	0	1	0	0
T40	0	13	0	0
T41	0	7	0	0
T47	0	10	0	0
T51	9672	11	0	0
T82	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	14466	0	0
T3	3810	11	0	0
T4	5593	4	0	0
T5	5825	0	0	0
T6	29312	75	0	0
T7	2608	0	0	0
T8	5957	4	0	0
T9	7436	11	0	0
T10	2906	8	0	0
T11	2265	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	231	0	0
T24	2057	0	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	1296	0	0
T9	7436	11	0	0
T10	2906	0	0	0
T11	2265	0	0	0
T12	4409	0	0	0
T13	2910	0	0	0
T22	223269	22	0	0
T23	350373	23	0	0
T24	2057	0	0	0
T40	0	15	0	0
T41	0	8	0	0
T47	0	12	0	0
T51	9672	12	0	0
T56	2658	0	0	0
T79	0	7	0	0
T81	0	1	0	0
T83	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	14466	0	0
T3	3810	11	0	0
T4	5593	4	0	0
T5	5825	0	0	0
T6	29312	75	0	0
T7	2608	0	0	0
T8	5957	4	0	0
T9	7436	11	0	0
T10	2906	8	0	0
T11	2265	4	0	0
T12	0	4	0	0
T13	0	4	0	0
T22	0	231	0	0
T24	2057	0	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	1296	0	0
T9	7436	11	0	0
T10	2906	0	0	0
T11	2265	0	0	0
T12	4409	0	0	0
T13	2910	0	0	0
T22	223269	22	0	0
T23	350373	23	0	0
T24	2057	0	0	0
T40	0	15	0	0
T41	0	8	0	0
T47	0	12	0	0
T51	9672	12	0	0
T56	2658	0	0	0
T79	0	7	0	0
T81	0	1	0	0
T83	0	1	0	0