Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12423726	9835	0	0
alert_regwen_rd_A	12423726	5703	0	0
cpu_regwen_rd_A	12423726	5865	0	0
sw_rst_ctrl_n_0_rd_A	12423726	11893	0	0
sw_rst_ctrl_n_1_rd_A	12423726	12157	0	0
sw_rst_ctrl_n_2_rd_A	12423726	11806	0	0
sw_rst_ctrl_n_3_rd_A	12423726	12025	0	0
sw_rst_ctrl_n_4_rd_A	12423726	12043	0	0
sw_rst_ctrl_n_5_rd_A	12423726	12323	0	0
sw_rst_ctrl_n_6_rd_A	12423726	11827	0	0
sw_rst_ctrl_n_7_rd_A	12423726	12212	0	0
sw_rst_regwen_0_rd_A	12423726	6090	0	0
sw_rst_regwen_1_rd_A	12423726	6271	0	0
sw_rst_regwen_2_rd_A	12423726	6217	0	0
sw_rst_regwen_3_rd_A	12423726	6467	0	0
sw_rst_regwen_4_rd_A	12423726	6127	0	0
sw_rst_regwen_5_rd_A	12423726	6326	0	0
sw_rst_regwen_6_rd_A	12423726	6152	0	0
sw_rst_regwen_7_rd_A	12423726	6494	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	9835	0	0
T57	4102	117	0	0
T58	6343	390	0	0
T59	10225	1	0	0
T60	4092	23	0	0
T61	10585	3	0	0
T87	3757	47	0	0
T88	2848	69	0	0
T89	6270	263	0	0
T90	4717	22	0	0
T93	17502	6	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	5703	0	0
T14	4475	0	0	0
T22	200106	159	0	0
T23	316453	540	0	0
T25	41908	0	0	0
T26	53458	0	0	0
T36	5278	0	0	0
T37	30724	0	0	0
T38	5451	0	0	0
T51	9581	0	0	0
T56	2512	0	0	0
T73	0	47	0	0
T96	0	59	0	0
T98	0	35	0	0
T100	0	30	0	0
T101	0	47	0	0
T103	0	257	0	0
T127	0	56	0	0
T128	0	53	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	5865	0	0
T14	4475	0	0	0
T22	200106	143	0	0
T23	316453	535	0	0
T25	41908	0	0	0
T26	53458	0	0	0
T36	5278	0	0	0
T37	30724	0	0	0
T38	5451	0	0	0
T51	9581	0	0	0
T56	2512	0	0	0
T73	0	45	0	0
T96	0	52	0	0
T98	0	68	0	0
T100	0	32	0	0
T101	0	46	0	0
T103	0	344	0	0
T127	0	66	0	0
T128	0	71	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	11893	0	0
T4	5302	14	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	2	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	254	0	0
T23	0	899	0	0
T24	1990	0	0	0
T41	0	68	0	0
T47	0	204	0	0
T51	0	102	0	0
T79	0	124	0	0
T83	0	22	0	0
T106	0	45	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	12157	0	0
T4	5302	15	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	5	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	240	0	0
T23	0	887	0	0
T24	1990	0	0	0
T41	0	102	0	0
T47	0	187	0	0
T51	0	88	0	0
T79	0	138	0	0
T83	0	8	0	0
T106	0	51	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	11806	0	0
T4	5302	9	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	12	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	320	0	0
T23	0	867	0	0
T24	1990	0	0	0
T41	0	63	0	0
T47	0	165	0	0
T51	0	97	0	0
T79	0	74	0	0
T83	0	16	0	0
T106	0	39	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	12025	0	0
T4	5302	7	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	20	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	296	0	0
T23	0	897	0	0
T24	1990	0	0	0
T41	0	90	0	0
T47	0	190	0	0
T51	0	92	0	0
T79	0	91	0	0
T83	0	18	0	0
T106	0	52	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	12043	0	0
T8	5714	20	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T13	2667	0	0	0
T22	200106	321	0	0
T23	316453	796	0	0
T24	1990	0	0	0
T41	0	84	0	0
T47	0	213	0	0
T51	9581	83	0	0
T79	0	128	0	0
T83	0	11	0	0
T96	0	65	0	0
T106	0	29	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	12323	0	0
T4	5302	8	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	14	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	327	0	0
T23	0	788	0	0
T24	1990	0	0	0
T41	0	76	0	0
T47	0	153	0	0
T51	0	79	0	0
T79	0	108	0	0
T83	0	17	0	0
T106	0	45	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	11827	0	0
T4	5302	11	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	11	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	280	0	0
T23	0	730	0	0
T24	1990	0	0	0
T41	0	82	0	0
T47	0	137	0	0
T51	0	110	0	0
T79	0	105	0	0
T83	0	6	0	0
T106	0	57	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	12212	0	0
T4	5302	11	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	5	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	304	0	0
T23	0	889	0	0
T24	1990	0	0	0
T41	0	112	0	0
T47	0	169	0	0
T51	0	108	0	0
T79	0	100	0	0
T83	0	20	0	0
T106	0	52	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	6090	0	0
T4	5302	9	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	1	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	155	0	0
T23	0	503	0	0
T24	1990	0	0	0
T41	0	15	0	0
T47	0	33	0	0
T51	0	8	0	0
T79	0	28	0	0
T83	0	5	0	0
T96	0	32	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	6271	0	0
T4	5302	4	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	6	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	132	0	0
T23	0	460	0	0
T24	1990	0	0	0
T41	0	30	0	0
T47	0	45	0	0
T51	0	31	0	0
T79	0	38	0	0
T83	0	11	0	0
T96	0	40	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	6217	0	0
T8	5714	9	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T13	2667	0	0	0
T22	200106	168	0	0
T23	316453	479	0	0
T24	1990	0	0	0
T41	0	19	0	0
T47	0	24	0	0
T51	9581	19	0	0
T79	0	29	0	0
T83	0	16	0	0
T96	0	47	0	0
T129	0	5	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	6467	0	0
T4	5302	2	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	8	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	162	0	0
T23	0	496	0	0
T24	1990	0	0	0
T41	0	11	0	0
T47	0	38	0	0
T51	0	24	0	0
T79	0	35	0	0
T83	0	9	0	0
T96	0	42	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	6127	0	0
T4	5302	1	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	3	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	147	0	0
T23	0	437	0	0
T24	1990	0	0	0
T41	0	12	0	0
T47	0	28	0	0
T51	0	18	0	0
T79	0	30	0	0
T83	0	11	0	0
T96	0	62	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	6326	0	0
T8	5714	7	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T13	2667	0	0	0
T22	200106	196	0	0
T23	316453	496	0	0
T24	1990	0	0	0
T41	0	12	0	0
T47	0	29	0	0
T51	9581	17	0	0
T79	0	20	0	0
T83	0	5	0	0
T96	0	47	0	0
T129	0	7	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	6152	0	0
T4	5302	6	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	1	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	88	0	0
T23	0	460	0	0
T24	1990	0	0	0
T41	0	11	0	0
T47	0	22	0	0
T51	0	15	0	0
T79	0	35	0	0
T83	0	9	0	0
T96	0	50	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12423726	6494	0	0
T4	5302	7	0	0
T5	5282	0	0	0
T6	26057	0	0	0
T7	2517	0	0	0
T8	5714	7	0	0
T9	7369	0	0	0
T10	2370	0	0	0
T11	2073	0	0	0
T12	4166	0	0	0
T22	0	120	0	0
T23	0	536	0	0
T24	1990	0	0	0
T41	0	17	0	0
T47	0	29	0	0
T51	0	28	0	0
T79	0	21	0	0
T83	0	10	0	0
T96	0	69	0	0