Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T11
0	1	Covered	T11,T12,T22
1	0	Covered	T4,T8,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T8,T11
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54623077	8391	0	0
CascadeEffAonToRstPorAboveRise_A	54623077	8391	0	0
CascadeEffAonToRstPorIoAboveFall_A	52435776	8391	0	0
CascadeEffAonToRstPorIoAboveRise_A	52435776	8391	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26219054	8391	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26219054	8391	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13109261	8391	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13109261	8391	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26218988	8391	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26218988	8391	0	0
CascadeLcToLcAboveFall_A	54623077	21596	0	0
CascadeLcToLcAboveRise_A	54623077	21596	0	0
CascadeLcToLcAonAboveFall_A	1655278	21596	0	0
CascadeLcToLcAonAboveRise_A	1655278	21596	0	0
CascadeLcToLcShadowedAboveFall_A	54623077	21596	0	0
CascadeLcToLcShadowedAboveRise_A	54623077	21596	0	0
CascadePorToAonAboveFall_A	1655278	6606	0	0
CascadeSysToSysAboveFall_A	54623077	21596	0	0
CascadeSysToSysAboveRise_A	54623077	21596	0	0
ScanRstToAonRise_A	1655278	192	0	0
StablePorToAonRise_A	1655278	8391	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11678716	21596	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11678716	21596	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11678716	21596	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11678716	21596	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13109261	21596	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13109261	21596	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11678716	21596	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11678716	21596	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11678716	21596	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11678716	21596	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54623077	8391	0	0
T1	17667	2	0	0
T2	7854	1	0	0
T3	15880	1	0	0
T4	23309	2	0	0
T5	24291	8	0	0
T6	122150	27	0	0
T7	10868	2	0	0
T8	24821	2	0	0
T9	30986	1	0	0
T10	12115	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54623077	8391	0	0
T1	17667	2	0	0
T2	7854	1	0	0
T3	15880	1	0	0
T4	23309	2	0	0
T5	24291	8	0	0
T6	122150	27	0	0
T7	10868	2	0	0
T8	24821	2	0	0
T9	30986	1	0	0
T10	12115	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52435776	8391	0	0
T1	16959	2	0	0
T2	7540	1	0	0
T3	15246	1	0	0
T4	22373	2	0	0
T5	23307	8	0	0
T6	117234	27	0	0
T7	10433	2	0	0
T8	23827	2	0	0
T9	29746	1	0	0
T10	11628	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52435776	8391	0	0
T1	16959	2	0	0
T2	7540	1	0	0
T3	15246	1	0	0
T4	22373	2	0	0
T5	23307	8	0	0
T6	117234	27	0	0
T7	10433	2	0	0
T8	23827	2	0	0
T9	29746	1	0	0
T10	11628	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26219054	8391	0	0
T1	8480	2	0	0
T2	3770	1	0	0
T3	7622	1	0	0
T4	11186	2	0	0
T5	11651	8	0	0
T6	58641	27	0	0
T7	5217	2	0	0
T8	11912	2	0	0
T9	14873	1	0	0
T10	5813	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26219054	8391	0	0
T1	8480	2	0	0
T2	3770	1	0	0
T3	7622	1	0	0
T4	11186	2	0	0
T5	11651	8	0	0
T6	58641	27	0	0
T7	5217	2	0	0
T8	11912	2	0	0
T9	14873	1	0	0
T10	5813	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	8391	0	0
T1	4239	2	0	0
T2	1884	1	0	0
T3	3810	1	0	0
T4	5593	2	0	0
T5	5825	8	0	0
T6	29312	27	0	0
T7	2608	2	0	0
T8	5957	2	0	0
T9	7436	1	0	0
T10	2906	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	8391	0	0
T1	4239	2	0	0
T2	1884	1	0	0
T3	3810	1	0	0
T4	5593	2	0	0
T5	5825	8	0	0
T6	29312	27	0	0
T7	2608	2	0	0
T8	5957	2	0	0
T9	7436	1	0	0
T10	2906	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26218988	8391	0	0
T1	8480	2	0	0
T2	3770	1	0	0
T3	7622	1	0	0
T4	11183	2	0	0
T5	11656	8	0	0
T6	58609	27	0	0
T7	5216	2	0	0
T8	11914	2	0	0
T9	14873	1	0	0
T10	5813	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26218988	8391	0	0
T1	8480	2	0	0
T2	3770	1	0	0
T3	7622	1	0	0
T4	11183	2	0	0
T5	11656	8	0	0
T6	58609	27	0	0
T7	5216	2	0	0
T8	11914	2	0	0
T9	14873	1	0	0
T10	5813	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54623077	21596	0	0
T1	17667	2	0	0
T2	7854	1	0	0
T3	15880	12	0	0
T4	23309	6	0	0
T5	24291	8	0	0
T6	122150	102	0	0
T7	10868	2	0	0
T8	24821	6	0	0
T9	30986	1	0	0
T10	12115	9	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54623077	21596	0	0
T1	17667	2	0	0
T2	7854	1	0	0
T3	15880	12	0	0
T4	23309	6	0	0
T5	24291	8	0	0
T6	122150	102	0	0
T7	10868	2	0	0
T8	24821	6	0	0
T9	30986	1	0	0
T10	12115	9	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	21596	0	0
T1	529	2	0	0
T2	234	1	0	0
T3	474	12	0	0
T4	697	6	0	0
T5	730	8	0	0
T6	3678	102	0	0
T7	325	2	0	0
T8	743	6	0	0
T9	928	1	0	0
T10	362	9	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	21596	0	0
T1	529	2	0	0
T2	234	1	0	0
T3	474	12	0	0
T4	697	6	0	0
T5	730	8	0	0
T6	3678	102	0	0
T7	325	2	0	0
T8	743	6	0	0
T9	928	1	0	0
T10	362	9	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54623077	21596	0	0
T1	17667	2	0	0
T2	7854	1	0	0
T3	15880	12	0	0
T4	23309	6	0	0
T5	24291	8	0	0
T6	122150	102	0	0
T7	10868	2	0	0
T8	24821	6	0	0
T9	30986	1	0	0
T10	12115	9	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54623077	21596	0	0
T1	17667	2	0	0
T2	7854	1	0	0
T3	15880	12	0	0
T4	23309	6	0	0
T5	24291	8	0	0
T6	122150	102	0	0
T7	10868	2	0	0
T8	24821	6	0	0
T9	30986	1	0	0
T10	12115	9	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	6606	0	0
T1	529	16	0	0
T2	234	1	0	0
T3	474	1	0	0
T4	697	1	0	0
T5	730	8	0	0
T6	3678	27	0	0
T7	325	6	0	0
T8	743	1	0	0
T9	928	1	0	0
T10	362	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54623077	21596	0	0
T1	17667	2	0	0
T2	7854	1	0	0
T3	15880	12	0	0
T4	23309	6	0	0
T5	24291	8	0	0
T6	122150	102	0	0
T7	10868	2	0	0
T8	24821	6	0	0
T9	30986	1	0	0
T10	12115	9	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54623077	21596	0	0
T1	17667	2	0	0
T2	7854	1	0	0
T3	15880	12	0	0
T4	23309	6	0	0
T5	24291	8	0	0
T6	122150	102	0	0
T7	10868	2	0	0
T8	24821	6	0	0
T9	30986	1	0	0
T10	12115	9	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	192	0	0
T14	570	0	0	0
T22	28244	5	0	0
T23	44416	5	0	0
T25	5675	0	0	0
T26	7117	0	0	0
T36	730	0	0	0
T37	4556	1	0	0
T38	728	0	0	0
T42	0	1	0	0
T51	1207	0	0	0
T56	331	0	0	0
T73	0	2	0	0
T80	0	3	0	0
T83	0	1	0	0
T84	0	5	0	0
T97	0	1	0	0
T130	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1655278	8391	0	0
T1	529	2	0	0
T2	234	1	0	0
T3	474	1	0	0
T4	697	2	0	0
T5	730	8	0	0
T6	3678	27	0	0
T7	325	2	0	0
T8	743	2	0	0
T9	928	1	0	0
T10	362	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11678716	21596	0	0
T1	4100	2	0	0
T2	1865	1	0	0
T3	2967	12	0	0
T4	5302	6	0	0
T5	5282	8	0	0
T6	26057	102	0	0
T7	2517	2	0	0
T8	5714	6	0	0
T9	7369	1	0	0
T10	2370	9	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11678716	21596	0	0
T1	4100	2	0	0
T2	1865	1	0	0
T3	2967	12	0	0
T4	5302	6	0	0
T5	5282	8	0	0
T6	26057	102	0	0
T7	2517	2	0	0
T8	5714	6	0	0
T9	7369	1	0	0
T10	2370	9	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11678716	21596	0	0
T1	4100	2	0	0
T2	1865	1	0	0
T3	2967	12	0	0
T4	5302	6	0	0
T5	5282	8	0	0
T6	26057	102	0	0
T7	2517	2	0	0
T8	5714	6	0	0
T9	7369	1	0	0
T10	2370	9	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11678716	21596	0	0
T1	4100	2	0	0
T2	1865	1	0	0
T3	2967	12	0	0
T4	5302	6	0	0
T5	5282	8	0	0
T6	26057	102	0	0
T7	2517	2	0	0
T8	5714	6	0	0
T9	7369	1	0	0
T10	2370	9	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	21596	0	0
T1	4239	2	0	0
T2	1884	1	0	0
T3	3810	12	0	0
T4	5593	6	0	0
T5	5825	8	0	0
T6	29312	102	0	0
T7	2608	2	0	0
T8	5957	6	0	0
T9	7436	1	0	0
T10	2906	9	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13109261	21596	0	0
T1	4239	2	0	0
T2	1884	1	0	0
T3	3810	12	0	0
T4	5593	6	0	0
T5	5825	8	0	0
T6	29312	102	0	0
T7	2608	2	0	0
T8	5957	6	0	0
T9	7436	1	0	0
T10	2906	9	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11678716	21596	0	0
T1	4100	2	0	0
T2	1865	1	0	0
T3	2967	12	0	0
T4	5302	6	0	0
T5	5282	8	0	0
T6	26057	102	0	0
T7	2517	2	0	0
T8	5714	6	0	0
T9	7369	1	0	0
T10	2370	9	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11678716	21596	0	0
T1	4100	2	0	0
T2	1865	1	0	0
T3	2967	12	0	0
T4	5302	6	0	0
T5	5282	8	0	0
T6	26057	102	0	0
T7	2517	2	0	0
T8	5714	6	0	0
T9	7369	1	0	0
T10	2370	9	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11678716	21596	0	0
T1	4100	2	0	0
T2	1865	1	0	0
T3	2967	12	0	0
T4	5302	6	0	0
T5	5282	8	0	0
T6	26057	102	0	0
T7	2517	2	0	0
T8	5714	6	0	0
T9	7369	1	0	0
T10	2370	9	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11678716	21596	0	0
T1	4100	2	0	0
T2	1865	1	0	0
T3	2967	12	0	0
T4	5302	6	0	0
T5	5282	8	0	0
T6	26057	102	0	0
T7	2517	2	0	0
T8	5714	6	0	0
T9	7369	1	0	0
T10	2370	9	0	0