Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8134

1

T1

10

T5

3

T7

16

auto[1]

11335

1

T1

91

T3

4

T5

21

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5840	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6666	1			T1	27		T2	1		T3	2
reset_info_cp[2]	3100	1			T1	22		T3	1		T5	5
reset_info_cp[4]	3911	1			T1	19		T3	1		T5	5
reset_info_cp[8]	110	1			T75	1		T141	1		T77	1
reset_info_cp[16]	125	1			T74	2		T148	1		T93	3
reset_info_cp[32]	109	1			T1	2		T8	1		T21	3
reset_info_cp[64]	121	1			T1	1		T9	1		T21	2
reset_info_cp[128]	107	1			T5	1		T7	1		T8	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3153	1			T1	10		T5	3		T8	6
reset_info_cp[1]	auto[1]	2893	1			T1	16		T3	1		T5	6
reset_info_cp[2]	auto[0]	945	1			T8	2		T9	5		T21	4
reset_info_cp[2]	auto[1]	2155	1			T1	22		T3	1		T5	5
reset_info_cp[4]	auto[0]	1380	1			T8	10		T9	3		T21	18
reset_info_cp[4]	auto[1]	2531	1			T1	19		T3	1		T5	5
reset_info_cp[8]	auto[0]	44	1			T77	1		T148	1		T105	2
reset_info_cp[8]	auto[1]	66	1			T75	1		T141	1		T25	2
reset_info_cp[16]	auto[0]	42	1			T74	2		T93	1		T97	1
reset_info_cp[16]	auto[1]	83	1			T148	1		T93	2		T27	2
reset_info_cp[32]	auto[0]	46	1			T41	1		T74	1		T77	1
reset_info_cp[32]	auto[1]	63	1			T1	2		T8	1		T21	3
reset_info_cp[64]	auto[0]	53	1			T9	1		T21	1		T41	1
reset_info_cp[64]	auto[1]	68	1			T1	1		T21	1		T24	1
reset_info_cp[128]	auto[0]	42	1			T7	1		T41	1		T74	1
reset_info_cp[128]	auto[1]	65	1			T5	1		T8	1		T22	1