---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A	0	0	1600565	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A	0	0	52781146	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A	0	0	12667148	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A	0	0	50668276	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	11231730	6449866	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	11231730	70	0	0
tb.dut.ParameterMatch_A	0	0	505	505	0	0
tb.dut.PwrKnownO_A	0	0	11231730	6449866	0	0
tb.dut.ResetsKnownO_A	0	0	11231730	6449866	0	0
tb.dut.RstEnKnownO_A	0	0	11231730	6449866	0	0
tb.dut.TlAReadyKnownO_A	0	0	11231730	6449866	0	0
tb.dut.TlDValidKnownO_A	0	0	11231730	6449866	0	0
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A	0	0	11231730	70	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A	0	0	1600565	964636	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0	0	0	9174	8669	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	8735	8230	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0	0	0	6863	6358	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0	0	0	8735	8230	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A	0	0	1600565	946306	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A	0	0	11231730	13160	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A	0	0	11231730	121440	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A	0	0	11231730	6490461	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A	0	0	11231730	193264	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A	0	0	11231730	13160	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A	0	0	11231730	121440	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A	0	0	11231730	6490461	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A	0	0	11231730	193264	0	0
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A	0	0	505	505	0	0
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A	0	0	505	505	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A	0	0	52781146	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A	0	0	52781146	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A	0	0	50668276	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A	0	0	50668276	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A	0	0	25334739	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A	0	0	25334739	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A	0	0	12667148	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A	0	0	12667148	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A	0	0	25334676	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A	0	0	25334676	8735	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A	0	0	52781146	21895	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A	0	0	52781146	21895	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A	0	0	1600565	21895	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A	0	0	1600565	21895	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A	0	0	52781146	21895	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A	0	0	52781146	21895	0	0
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A	0	0	1600565	6874	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A	0	0	52781146	21895	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A	0	0	52781146	21895	0	0
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A	0	0	1600565	266	0	0
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A	0	0	1600565	8735	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A	0	0	11231730	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A	0	0	11231730	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A	0	0	11231730	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A	0	0	11231730	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	0	0	12667148	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	0	0	12667148	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A	0	0	11231730	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A	0	0	11231730	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A	0	0	11231730	21895	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A	0	0	11231730	21895	0	0
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A	0	0	11962251	9478	0	0
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A	0	0	11962251	4682	0	0
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A	0	0	11962251	4661	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A	0	0	11962251	9199	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A	0	0	11962251	9248	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A	0	0	11962251	9258	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A	0	0	11962251	9230	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A	0	0	11962251	8868	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A	0	0	11962251	9181	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A	0	0	11962251	9186	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A	0	0	11962251	9019	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A	0	0	11962251	5142	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A	0	0	11962251	5022	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A	0	0	11962251	5178	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A	0	0	11962251	4983	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A	0	0	11962251	5162	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A	0	0	11962251	5097	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A	0	0	11962251	5251	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A	0	0	11962251	5236	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A	0	0	12667148	14359	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A	0	0	12667148	22985	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A	0	0	12667148	14386	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A	0	0	12667148	23014	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A	0	0	12667148	14474	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A	0	0	12667148	23097	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	25334739	13234	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	25334739	21895	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	12667148	13260	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	12667148	21945	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A	0	0	50668276	13240	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A	0	0	50668276	21895	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A	0	0	52781146	13210	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	52781146	21895	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A	0	0	25334676	13231	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A	0	0	25334676	21895	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A	0	0	1600565	50	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A	0	0	1600565	8717	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A	0	0	12667148	14137	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A	0	0	12667148	22757	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A	0	0	50668276	14143	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A	0	0	50668276	22776	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A	0	0	25334739	14215	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A	0	0	25334739	22837	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A	0	0	52781146	13239	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A	0	0	52781146	21895	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A	0	0	1600565	13942	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A	0	0	1600565	22154	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A	0	0	25334676	14295	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A	0	0	25334676	22925	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A	0	0	1600565	13185	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A	0	0	1600565	21877	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	25334739	13179	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	25334739	21895	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	12667148	13210	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	12667148	21945	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A	0	0	50668276	13188	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A	0	0	50668276	21895	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A	0	0	52781146	13236	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	52781146	21945	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A	0	0	25334676	13194	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A	0	0	25334676	21895	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A	0	0	1600565	8735	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A	0	0	52781146	25	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A	0	0	25334739	25	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A	0	0	25334739	2223	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A	0	0	12667148	8735	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A	0	0	50668276	20	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A	0	0	25334676	28	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A	0	0	25334676	2223	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A	0	0	12667148	13188	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A	0	0	12667148	21895	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A	0	0	12667148	14019	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A	0	0	12667148	1024	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A	0	0	50668276	12717	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A	0	0	50668276	967	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A	0	0	50668276	12717	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A	0	0	50668276	967	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A	0	0	25334739	983	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A	0	0	25334739	983	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A	0	0	25334676	1061	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A	0	0	25334676	1061	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A	0	0	1600565	1086	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A	0	0	1600565	1086	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A	0	0	12667148	1123	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOn_A	0	0	12667148	1148	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOn_A	0	0	12667148	1148	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOff_A	0	0	12667148	14359	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOn_A	0	0	12667148	1240	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A	0	0	12667148	1240	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	11962251	1139554	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	11962251	6906529	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	11962251	6906529	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	11962251	1944914	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	11962251	6906529	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	11962251	6906529	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
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tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
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tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
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tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
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tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
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tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
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tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	620	620	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	11962871	502221	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	11962251	6501	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	11962871	838962	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	11962871	1009115	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	11962251	7074	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	11962871	1139684	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	11962871	1945071	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	11962871	1139684	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	11962871	1945071	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	11962871	1945071	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	11962871	1945071	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	11962251	3778	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	11962251	3064	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	620	620	0	0
tb.dut.u_alert_info.CntStoreSlot_A	0	0	505	505	0	0
tb.dut.u_alert_info.CntWidth_A	0	0	505	505	0	0
tb.dut.u_cpu_info.CntStoreSlot_A	0	0	505	505	0	0
tb.dut.u_cpu_info.CntWidth_A	0	0	505	505	0	0
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A	0	0	12667148	7553333	0	0
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	12667148	7553333	0	0
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6354718	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22982	22477	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6365757	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23011	22506	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6356732	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	23094	22589	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	52781146	27146443	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	50668276	26058368	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25334739	13019070	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6481945	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6481945	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	52781146	27147748	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25334676	13019138	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6355595	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22754	22249	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A	0	0	50668276	25568067	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22768	22263	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A	0	0	25334739	12754288	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22831	22326	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A	0	0	52781146	26846885	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25334676	12752415	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22920	22415	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21827	21322	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1600565	789990	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22932	22427	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	52781146	27864928	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21827	21322	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1600565	827120	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	50668276	26750389	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25334739	13365136	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6654902	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6654902	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	52781146	27864893	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25334676	13364702	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A	0	0	52781146	31495221	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8735	8230	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	50668276	30234011	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8735	8230	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25334739	15113186	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8735	8230	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	7553333	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8735	8230	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25334676	15113076	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8735	8230	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21945	21440	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12667148	6583210	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	505	505	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11231730	6449866	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11231730	6449866	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_reg.en2addrHit	0	0	11962251	980309	0	0
tb.dut.u_reg.reAfterRv	0	0	11962251	980170	0	0
tb.dut.u_reg.rePulse	0	0	11962251	526308	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	620	620	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	620	620	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	620	620	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	620	620	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	620	620	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	620	620	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	620	620	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	620	620	0	0
tb.dut.u_reg.wePulse	0	0	11962251	453862	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	21895	21390	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	2856	2351	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	11962871	6130	6130	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	11962871	2820	2820	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	11962871	2827	2827	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	11962871	1979	1979	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	11962871	113	113	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	11962871	1526	1526	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	11962871	1297	1297	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	11962871	3649	3649	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	11962871	60665	60665	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	11962871	469779	469779	455

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	11962871	6130	6130	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	11962871	2820	2820	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	11962871	2827	2827	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	11962871	1979	1979	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	11962871	113	113	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	11962871	1526	1526	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	11962871	1297	1297	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	11962871	3649	3649	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	11962871	60665	60665	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	11962871	469779	469779	455