Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T537 /workspace/coverage/default/39.rstmgr_por_stretcher.3777412513 Feb 25 02:25:41 PM PST 24 Feb 25 02:25:42 PM PST 24 195124703 ps
T538 /workspace/coverage/default/14.rstmgr_reset.1926312604 Feb 25 02:24:24 PM PST 24 Feb 25 02:24:31 PM PST 24 1560298787 ps
T539 /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.621796654 Feb 25 02:25:50 PM PST 24 Feb 25 02:25:52 PM PST 24 149116194 ps
T540 /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3585989434 Feb 25 02:24:04 PM PST 24 Feb 25 02:24:06 PM PST 24 244024393 ps
T541 /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.915274778 Feb 25 02:24:53 PM PST 24 Feb 25 02:24:55 PM PST 24 217157989 ps
T51 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4166923857 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:52 PM PST 24 124161129 ps
T52 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1134215510 Feb 25 01:45:45 PM PST 24 Feb 25 01:45:46 PM PST 24 69327749 ps
T53 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.206711339 Feb 25 01:45:31 PM PST 24 Feb 25 01:45:32 PM PST 24 122243864 ps
T55 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2526843913 Feb 25 01:45:31 PM PST 24 Feb 25 01:45:34 PM PST 24 176198527 ps
T56 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2957311868 Feb 25 01:45:41 PM PST 24 Feb 25 01:45:44 PM PST 24 368786177 ps
T54 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4165894185 Feb 25 01:45:29 PM PST 24 Feb 25 01:45:31 PM PST 24 474365718 ps
T62 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.405409649 Feb 25 01:45:42 PM PST 24 Feb 25 01:45:45 PM PST 24 806161894 ps
T82 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3814415197 Feb 25 01:45:40 PM PST 24 Feb 25 01:45:42 PM PST 24 472032822 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3753311828 Feb 25 01:45:35 PM PST 24 Feb 25 01:45:39 PM PST 24 278874433 ps
T114 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.736441535 Feb 25 01:45:43 PM PST 24 Feb 25 01:45:43 PM PST 24 71780591 ps
T543 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.308038844 Feb 25 01:45:37 PM PST 24 Feb 25 01:45:38 PM PST 24 91448592 ps
T544 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.243369408 Feb 25 01:45:29 PM PST 24 Feb 25 01:45:30 PM PST 24 72869959 ps
T83 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1980433866 Feb 25 01:45:50 PM PST 24 Feb 25 01:45:53 PM PST 24 494752967 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3908180005 Feb 25 01:45:37 PM PST 24 Feb 25 01:45:42 PM PST 24 1020128650 ps
T115 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2170482149 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:52 PM PST 24 136565048 ps
T84 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3814086895 Feb 25 01:45:44 PM PST 24 Feb 25 01:45:45 PM PST 24 200625340 ps
T85 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3768012744 Feb 25 01:45:45 PM PST 24 Feb 25 01:45:46 PM PST 24 117952770 ps
T546 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2112861905 Feb 25 01:45:33 PM PST 24 Feb 25 01:45:35 PM PST 24 71873925 ps
T86 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1083562120 Feb 25 01:45:53 PM PST 24 Feb 25 01:45:56 PM PST 24 415247115 ps
T87 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3004717598 Feb 25 01:45:45 PM PST 24 Feb 25 01:45:48 PM PST 24 393572922 ps
T88 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2032346471 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:54 PM PST 24 132870606 ps
T116 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.631364584 Feb 25 01:45:44 PM PST 24 Feb 25 01:45:45 PM PST 24 58742602 ps
T89 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2674993171 Feb 25 01:45:47 PM PST 24 Feb 25 01:45:49 PM PST 24 189321069 ps
T90 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1309672073 Feb 25 01:45:51 PM PST 24 Feb 25 01:45:55 PM PST 24 595652168 ps
T91 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1763329211 Feb 25 01:45:47 PM PST 24 Feb 25 01:45:50 PM PST 24 206198435 ps
T117 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1232551651 Feb 25 01:45:41 PM PST 24 Feb 25 01:45:43 PM PST 24 195487183 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3076341129 Feb 25 01:45:33 PM PST 24 Feb 25 01:45:39 PM PST 24 1027877737 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3935733768 Feb 25 01:45:35 PM PST 24 Feb 25 01:45:37 PM PST 24 280074484 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.171440886 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:52 PM PST 24 189658323 ps
T122 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1524692280 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:51 PM PST 24 477069374 ps
T118 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3823841925 Feb 25 01:45:33 PM PST 24 Feb 25 01:45:35 PM PST 24 86188266 ps
T119 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3700047260 Feb 25 01:45:32 PM PST 24 Feb 25 01:45:34 PM PST 24 82872234 ps
T550 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3751435301 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:52 PM PST 24 188357756 ps
T120 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3241787938 Feb 25 01:45:46 PM PST 24 Feb 25 01:45:48 PM PST 24 144449146 ps
T126 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2392305812 Feb 25 01:45:42 PM PST 24 Feb 25 01:45:44 PM PST 24 457951159 ps
T551 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2057202786 Feb 25 01:45:43 PM PST 24 Feb 25 01:45:46 PM PST 24 419741035 ps
T121 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.820125777 Feb 25 01:45:39 PM PST 24 Feb 25 01:45:41 PM PST 24 108873287 ps
T552 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1875788043 Feb 25 01:45:51 PM PST 24 Feb 25 01:45:54 PM PST 24 197572333 ps
T553 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1615588415 Feb 25 01:45:51 PM PST 24 Feb 25 01:45:52 PM PST 24 85495293 ps
T124 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1407891312 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:54 PM PST 24 863987492 ps
T554 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3717950006 Feb 25 01:45:37 PM PST 24 Feb 25 01:45:39 PM PST 24 286483216 ps
T555 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3972728418 Feb 25 01:45:31 PM PST 24 Feb 25 01:45:37 PM PST 24 1184924473 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1541603069 Feb 25 01:45:38 PM PST 24 Feb 25 01:45:39 PM PST 24 77319409 ps
T144 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.694176562 Feb 25 01:45:42 PM PST 24 Feb 25 01:45:45 PM PST 24 783741852 ps
T557 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3904746143 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:52 PM PST 24 226572428 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.872266634 Feb 25 01:45:31 PM PST 24 Feb 25 01:45:33 PM PST 24 115455954 ps
T559 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1602131459 Feb 25 01:45:44 PM PST 24 Feb 25 01:45:45 PM PST 24 97326279 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.762500669 Feb 25 01:45:33 PM PST 24 Feb 25 01:45:35 PM PST 24 245192430 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1608522075 Feb 25 01:45:45 PM PST 24 Feb 25 01:45:46 PM PST 24 83745230 ps
T562 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3535067825 Feb 25 01:45:55 PM PST 24 Feb 25 01:45:56 PM PST 24 119953771 ps
T563 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2645126602 Feb 25 01:45:35 PM PST 24 Feb 25 01:45:37 PM PST 24 117440547 ps
T564 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3072891184 Feb 25 01:45:44 PM PST 24 Feb 25 01:45:47 PM PST 24 276287568 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.700336257 Feb 25 01:45:31 PM PST 24 Feb 25 01:45:32 PM PST 24 71189132 ps
T566 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.760203794 Feb 25 01:45:44 PM PST 24 Feb 25 01:45:44 PM PST 24 73955493 ps
T127 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1631748361 Feb 25 01:45:45 PM PST 24 Feb 25 01:45:48 PM PST 24 874153559 ps
T567 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2013725796 Feb 25 01:45:50 PM PST 24 Feb 25 01:45:52 PM PST 24 127163802 ps
T568 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1178100747 Feb 25 01:45:50 PM PST 24 Feb 25 01:45:52 PM PST 24 76947980 ps
T569 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2074114127 Feb 25 01:45:43 PM PST 24 Feb 25 01:45:44 PM PST 24 211522489 ps
T570 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.661040164 Feb 25 01:45:39 PM PST 24 Feb 25 01:45:40 PM PST 24 141831072 ps
T571 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1080894229 Feb 25 01:45:43 PM PST 24 Feb 25 01:45:46 PM PST 24 179417002 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2290911253 Feb 25 01:45:39 PM PST 24 Feb 25 01:45:41 PM PST 24 208655812 ps
T573 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.917713474 Feb 25 01:45:50 PM PST 24 Feb 25 01:45:52 PM PST 24 67665735 ps
T574 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3908039398 Feb 25 01:45:28 PM PST 24 Feb 25 01:45:30 PM PST 24 352201706 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.646516860 Feb 25 01:45:35 PM PST 24 Feb 25 01:45:36 PM PST 24 196747898 ps
T576 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2273683605 Feb 25 01:45:50 PM PST 24 Feb 25 01:45:53 PM PST 24 119874166 ps
T577 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.798171471 Feb 25 01:45:47 PM PST 24 Feb 25 01:45:49 PM PST 24 170941331 ps
T145 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1752851914 Feb 25 01:45:34 PM PST 24 Feb 25 01:45:36 PM PST 24 522734158 ps
T578 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4107505425 Feb 25 01:45:42 PM PST 24 Feb 25 01:45:43 PM PST 24 102397510 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3441548169 Feb 25 01:45:39 PM PST 24 Feb 25 01:45:43 PM PST 24 266040813 ps
T580 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1148110769 Feb 25 01:45:55 PM PST 24 Feb 25 01:45:56 PM PST 24 123486515 ps
T128 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3781347188 Feb 25 01:45:39 PM PST 24 Feb 25 01:45:42 PM PST 24 463289855 ps
T581 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1889676697 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:55 PM PST 24 778919681 ps
T582 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1167912938 Feb 25 01:45:45 PM PST 24 Feb 25 01:45:46 PM PST 24 85537101 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2471963400 Feb 25 01:45:31 PM PST 24 Feb 25 01:45:33 PM PST 24 132320023 ps
T584 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.873188864 Feb 25 01:45:29 PM PST 24 Feb 25 01:45:31 PM PST 24 467945574 ps
T585 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1353444337 Feb 25 01:45:41 PM PST 24 Feb 25 01:45:44 PM PST 24 358751878 ps
T586 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.853554207 Feb 25 01:45:45 PM PST 24 Feb 25 01:45:47 PM PST 24 246234749 ps
T587 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2896701804 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:54 PM PST 24 148370347 ps
T588 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2250511764 Feb 25 01:45:34 PM PST 24 Feb 25 01:45:36 PM PST 24 118151256 ps
T589 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2852707974 Feb 25 01:45:58 PM PST 24 Feb 25 01:45:59 PM PST 24 209792271 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2532659224 Feb 25 01:45:30 PM PST 24 Feb 25 01:45:32 PM PST 24 114944109 ps
T147 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2320874730 Feb 25 01:46:02 PM PST 24 Feb 25 01:46:06 PM PST 24 882672613 ps
T146 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2516075143 Feb 25 01:45:43 PM PST 24 Feb 25 01:45:45 PM PST 24 483195234 ps
T125 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2166284714 Feb 25 01:45:37 PM PST 24 Feb 25 01:45:40 PM PST 24 898112197 ps
T591 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2498109049 Feb 25 01:46:05 PM PST 24 Feb 25 01:46:06 PM PST 24 203750056 ps
T592 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1444015637 Feb 25 01:45:34 PM PST 24 Feb 25 01:45:37 PM PST 24 211534661 ps
T593 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3014352357 Feb 25 01:45:51 PM PST 24 Feb 25 01:45:53 PM PST 24 421278149 ps
T594 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3886590668 Feb 25 01:45:56 PM PST 24 Feb 25 01:45:59 PM PST 24 304819283 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3036128137 Feb 25 01:45:39 PM PST 24 Feb 25 01:45:40 PM PST 24 99658145 ps
T596 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.251174022 Feb 25 01:45:50 PM PST 24 Feb 25 01:45:53 PM PST 24 174190145 ps
T123 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1266331980 Feb 25 01:45:49 PM PST 24 Feb 25 01:45:54 PM PST 24 902743104 ps
T597 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4088141502 Feb 25 01:45:41 PM PST 24 Feb 25 01:45:42 PM PST 24 93237198 ps
T598 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3791918616 Feb 25 01:45:41 PM PST 24 Feb 25 01:45:43 PM PST 24 107528680 ps
T599 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3682452786 Feb 25 01:45:46 PM PST 24 Feb 25 01:45:47 PM PST 24 94076983 ps
T600 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2210798187 Feb 25 01:45:47 PM PST 24 Feb 25 01:45:48 PM PST 24 119914629 ps
T601 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2927408874 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:53 PM PST 24 61161496 ps
T602 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.393743213 Feb 25 01:46:05 PM PST 24 Feb 25 01:46:06 PM PST 24 99902099 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1816903896 Feb 25 01:45:48 PM PST 24 Feb 25 01:45:52 PM PST 24 153833205 ps
T604 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1643000819 Feb 25 01:45:44 PM PST 24 Feb 25 01:45:48 PM PST 24 426121765 ps
T605 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3261336643 Feb 25 01:45:28 PM PST 24 Feb 25 01:45:30 PM PST 24 175523458 ps
T606 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2016314650 Feb 25 01:45:53 PM PST 24 Feb 25 01:45:54 PM PST 24 70361183 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.289312339 Feb 25 01:45:46 PM PST 24 Feb 25 01:45:47 PM PST 24 75064721 ps
T608 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1719418914 Feb 25 01:45:31 PM PST 24 Feb 25 01:45:32 PM PST 24 115164457 ps
T609 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1203344878 Feb 25 01:45:52 PM PST 24 Feb 25 01:45:53 PM PST 24 66204840 ps
T610 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.26359862 Feb 25 01:45:50 PM PST 24 Feb 25 01:45:53 PM PST 24 130323307 ps
T611 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2154787658 Feb 25 01:45:39 PM PST 24 Feb 25 01:45:42 PM PST 24 775951343 ps
T612 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4095390414 Feb 25 01:45:58 PM PST 24 Feb 25 01:46:01 PM PST 24 804199702 ps
T613 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1743832267 Feb 25 01:46:02 PM PST 24 Feb 25 01:46:04 PM PST 24 179329100 ps
T614 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1797936862 Feb 25 01:45:43 PM PST 24 Feb 25 01:45:44 PM PST 24 79022740 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2833561173 Feb 25 01:45:30 PM PST 24 Feb 25 01:45:31 PM PST 24 95111064 ps
T616 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3648468081 Feb 25 01:45:44 PM PST 24 Feb 25 01:45:46 PM PST 24 139858864 ps
T617 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.513193084 Feb 25 01:45:47 PM PST 24 Feb 25 01:45:48 PM PST 24 118444920 ps
T618 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.964928071 Feb 25 01:45:39 PM PST 24 Feb 25 01:45:41 PM PST 24 241826361 ps
T619 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1260653867 Feb 25 01:45:45 PM PST 24 Feb 25 01:45:47 PM PST 24 214572785 ps
T620 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2050204271 Feb 25 01:45:42 PM PST 24 Feb 25 01:45:43 PM PST 24 100489562 ps

Test location /workspace/coverage/default/32.rstmgr_stress_all.964416296
Short name T5
Test name
Test status
Simulation time 986528734 ps
CPU time 4.8 seconds
Started Feb 25 02:25:31 PM PST 24
Finished Feb 25 02:25:36 PM PST 24
Peak memory 200716 kb
Host smart-9b56969e-ea56-43a7-b1ac-402138742b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964416296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.964416296
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.367061542
Short name T6
Test name
Test status
Simulation time 403357987 ps
CPU time 2.31 seconds
Started Feb 25 02:24:09 PM PST 24
Finished Feb 25 02:24:11 PM PST 24
Peak memory 200540 kb
Host smart-1000ec54-1329-4eed-8506-d824790fc8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367061542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.367061542
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4012191128
Short name T1
Test name
Test status
Simulation time 2175666981 ps
CPU time 8.73 seconds
Started Feb 25 02:23:38 PM PST 24
Finished Feb 25 02:23:47 PM PST 24
Peak memory 218656 kb
Host smart-93b4662a-744a-4eff-9a58-1f5d77ab5b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012191128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4012191128
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2526843913
Short name T55
Test name
Test status
Simulation time 176198527 ps
CPU time 2.6 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:34 PM PST 24
Peak memory 200156 kb
Host smart-63d8dd26-4c30-4f66-960e-330d767952be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526843913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2526843913
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3008871182
Short name T58
Test name
Test status
Simulation time 16557112399 ps
CPU time 26.57 seconds
Started Feb 25 02:23:40 PM PST 24
Finished Feb 25 02:24:07 PM PST 24
Peak memory 218564 kb
Host smart-11324b2e-51e6-497f-83a2-569e795df249
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008871182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3008871182
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1874124782
Short name T93
Test name
Test status
Simulation time 3668982426 ps
CPU time 16.69 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:58 PM PST 24
Peak memory 200896 kb
Host smart-fdb92036-b53a-48b7-9e05-d1631b744dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874124782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1874124782
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.405409649
Short name T62
Test name
Test status
Simulation time 806161894 ps
CPU time 2.83 seconds
Started Feb 25 01:45:42 PM PST 24
Finished Feb 25 01:45:45 PM PST 24
Peak memory 200140 kb
Host smart-ddfb6cd9-eba3-4d69-a958-5598ffad8464
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405409649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.405409649
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2280169962
Short name T150
Test name
Test status
Simulation time 69284766 ps
CPU time 0.74 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:14 PM PST 24
Peak memory 200484 kb
Host smart-60fa7e5b-e0b2-4dbc-a89f-4b3e63c4d987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280169962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2280169962
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2108943531
Short name T107
Test name
Test status
Simulation time 12652722233 ps
CPU time 52.01 seconds
Started Feb 25 02:25:42 PM PST 24
Finished Feb 25 02:26:35 PM PST 24
Peak memory 200832 kb
Host smart-1846baf9-927b-4a1c-a213-1483549c7595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108943531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2108943531
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3916532228
Short name T25
Test name
Test status
Simulation time 1230623936 ps
CPU time 5.7 seconds
Started Feb 25 02:25:30 PM PST 24
Finished Feb 25 02:25:36 PM PST 24
Peak memory 217412 kb
Host smart-614bae36-0e55-4dc0-867f-5198be5b55bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916532228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3916532228
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.626592700
Short name T22
Test name
Test status
Simulation time 162952461 ps
CPU time 1.2 seconds
Started Feb 25 02:23:28 PM PST 24
Finished Feb 25 02:23:30 PM PST 24
Peak memory 200496 kb
Host smart-12ecaace-4779-4e1e-9e7e-da33141ae019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626592700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.626592700
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2586041242
Short name T4
Test name
Test status
Simulation time 116860068 ps
CPU time 0.81 seconds
Started Feb 25 02:24:14 PM PST 24
Finished Feb 25 02:24:15 PM PST 24
Peak memory 200372 kb
Host smart-fafbb1b2-a7d9-478a-a914-23467352e9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586041242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2586041242
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2516075143
Short name T146
Test name
Test status
Simulation time 483195234 ps
CPU time 1.88 seconds
Started Feb 25 01:45:43 PM PST 24
Finished Feb 25 01:45:45 PM PST 24
Peak memory 200140 kb
Host smart-c8f86c5e-4001-47bb-b81f-d36a726b9029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516075143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2516075143
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.832588869
Short name T44
Test name
Test status
Simulation time 2360921236 ps
CPU time 8.67 seconds
Started Feb 25 02:25:26 PM PST 24
Finished Feb 25 02:25:35 PM PST 24
Peak memory 218312 kb
Host smart-f4ee8e9f-880d-42bb-a0fc-09b460985cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832588869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.832588869
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3730864896
Short name T105
Test name
Test status
Simulation time 120530321 ps
CPU time 1.09 seconds
Started Feb 25 02:25:07 PM PST 24
Finished Feb 25 02:25:09 PM PST 24
Peak memory 200460 kb
Host smart-b45b2601-db3d-46cc-871a-043b72a8df37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730864896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3730864896
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.171440886
Short name T549
Test name
Test status
Simulation time 189658323 ps
CPU time 1.37 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 199960 kb
Host smart-64e6f0df-0cdf-4512-98b9-db67c2133b25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171440886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.171440886
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3823841925
Short name T118
Test name
Test status
Simulation time 86188266 ps
CPU time 0.94 seconds
Started Feb 25 01:45:33 PM PST 24
Finished Feb 25 01:45:35 PM PST 24
Peak memory 200028 kb
Host smart-b7784608-9186-43cd-a442-c0f84441cb65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823841925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3823841925
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.395763262
Short name T142
Test name
Test status
Simulation time 2361379431 ps
CPU time 8.99 seconds
Started Feb 25 02:24:38 PM PST 24
Finished Feb 25 02:24:48 PM PST 24
Peak memory 217792 kb
Host smart-d8503c60-84e7-4618-9d3c-723452c45bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395763262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.395763262
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4165894185
Short name T54
Test name
Test status
Simulation time 474365718 ps
CPU time 1.8 seconds
Started Feb 25 01:45:29 PM PST 24
Finished Feb 25 01:45:31 PM PST 24
Peak memory 200248 kb
Host smart-f1f42717-dc8d-404e-8387-0885e6ebaddf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165894185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4165894185
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3781347188
Short name T128
Test name
Test status
Simulation time 463289855 ps
CPU time 1.72 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:42 PM PST 24
Peak memory 200256 kb
Host smart-594e0d77-d84c-4826-8f9e-2cd2e1c506cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781347188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3781347188
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3908039398
Short name T574
Test name
Test status
Simulation time 352201706 ps
CPU time 2.42 seconds
Started Feb 25 01:45:28 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 200152 kb
Host smart-4c448ddc-23fc-4a90-9a47-fba4a9e07d4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908039398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
908039398
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3753311828
Short name T542
Test name
Test status
Simulation time 278874433 ps
CPU time 3.42 seconds
Started Feb 25 01:45:35 PM PST 24
Finished Feb 25 01:45:39 PM PST 24
Peak memory 200180 kb
Host smart-2895aa75-6e65-4c55-9186-b10cfe594529
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753311828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
753311828
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3036128137
Short name T595
Test name
Test status
Simulation time 99658145 ps
CPU time 0.82 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:40 PM PST 24
Peak memory 199948 kb
Host smart-003f1e25-9b8c-4901-8c7e-6462794bc18a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036128137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
036128137
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.872266634
Short name T558
Test name
Test status
Simulation time 115455954 ps
CPU time 1.13 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:33 PM PST 24
Peak memory 199992 kb
Host smart-87ebbca9-01f3-4f7c-a849-535adc1c33f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872266634 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.872266634
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2112861905
Short name T546
Test name
Test status
Simulation time 71873925 ps
CPU time 0.76 seconds
Started Feb 25 01:45:33 PM PST 24
Finished Feb 25 01:45:35 PM PST 24
Peak memory 200024 kb
Host smart-3330f5bc-d846-4e8d-b0f2-2082b7354b79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112861905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2112861905
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3261336643
Short name T605
Test name
Test status
Simulation time 175523458 ps
CPU time 2.26 seconds
Started Feb 25 01:45:28 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 208324 kb
Host smart-887ba517-77df-484e-8923-d4b8d40763d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261336643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3261336643
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.762500669
Short name T560
Test name
Test status
Simulation time 245192430 ps
CPU time 1.63 seconds
Started Feb 25 01:45:33 PM PST 24
Finished Feb 25 01:45:35 PM PST 24
Peak memory 200140 kb
Host smart-ea9495d5-280a-42c6-9542-909bc941cd10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762500669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.762500669
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3076341129
Short name T547
Test name
Test status
Simulation time 1027877737 ps
CPU time 5.38 seconds
Started Feb 25 01:45:33 PM PST 24
Finished Feb 25 01:45:39 PM PST 24
Peak memory 200176 kb
Host smart-e1a5b9f7-513b-43c0-9e9b-504d02657695
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076341129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
076341129
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4107505425
Short name T578
Test name
Test status
Simulation time 102397510 ps
CPU time 0.8 seconds
Started Feb 25 01:45:42 PM PST 24
Finished Feb 25 01:45:43 PM PST 24
Peak memory 199932 kb
Host smart-74272fcb-29c4-41ca-93f7-c4587692c0e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107505425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4
107505425
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.206711339
Short name T53
Test name
Test status
Simulation time 122243864 ps
CPU time 1.02 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:32 PM PST 24
Peak memory 200064 kb
Host smart-1e059732-725f-4bcb-92f5-79eedc59f396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206711339 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.206711339
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1541603069
Short name T556
Test name
Test status
Simulation time 77319409 ps
CPU time 0.76 seconds
Started Feb 25 01:45:38 PM PST 24
Finished Feb 25 01:45:39 PM PST 24
Peak memory 199944 kb
Host smart-7f974fae-54af-424a-97b6-5f286e30ce10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541603069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1541603069
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.820125777
Short name T121
Test name
Test status
Simulation time 108873287 ps
CPU time 1.2 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:41 PM PST 24
Peak memory 200256 kb
Host smart-f70c951f-233b-41c2-8fe3-2d5da92486bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820125777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.820125777
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2645126602
Short name T563
Test name
Test status
Simulation time 117440547 ps
CPU time 1.74 seconds
Started Feb 25 01:45:35 PM PST 24
Finished Feb 25 01:45:37 PM PST 24
Peak memory 200104 kb
Host smart-74476239-1811-4b6f-8435-9397b0b169ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645126602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2645126602
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2674993171
Short name T89
Test name
Test status
Simulation time 189321069 ps
CPU time 1.81 seconds
Started Feb 25 01:45:47 PM PST 24
Finished Feb 25 01:45:49 PM PST 24
Peak memory 208484 kb
Host smart-19f0911e-21c5-4a83-83cf-281b1e1d8e1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674993171 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2674993171
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3682452786
Short name T599
Test name
Test status
Simulation time 94076983 ps
CPU time 0.86 seconds
Started Feb 25 01:45:46 PM PST 24
Finished Feb 25 01:45:47 PM PST 24
Peak memory 199716 kb
Host smart-32be8f30-fec7-407a-9238-12c37dd21c12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682452786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3682452786
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.26359862
Short name T610
Test name
Test status
Simulation time 130323307 ps
CPU time 1.1 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 199980 kb
Host smart-9a551ef2-0560-4187-87f4-d74d43d4d846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26359862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sam
e_csr_outstanding.26359862
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3004717598
Short name T87
Test name
Test status
Simulation time 393572922 ps
CPU time 2.56 seconds
Started Feb 25 01:45:45 PM PST 24
Finished Feb 25 01:45:48 PM PST 24
Peak memory 200176 kb
Host smart-6c24ef94-de6a-40ac-8a2d-a0137aa57ccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004717598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3004717598
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1407891312
Short name T124
Test name
Test status
Simulation time 863987492 ps
CPU time 3.2 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 200248 kb
Host smart-6d24e0e9-6803-4f58-9b2a-f8b9da2fb32e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407891312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1407891312
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3814086895
Short name T84
Test name
Test status
Simulation time 200625340 ps
CPU time 1.39 seconds
Started Feb 25 01:45:44 PM PST 24
Finished Feb 25 01:45:45 PM PST 24
Peak memory 200036 kb
Host smart-2c3de771-87f0-4df0-914a-fd44ad484dab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814086895 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3814086895
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1608522075
Short name T561
Test name
Test status
Simulation time 83745230 ps
CPU time 0.89 seconds
Started Feb 25 01:45:45 PM PST 24
Finished Feb 25 01:45:46 PM PST 24
Peak memory 200004 kb
Host smart-a79cc369-d22e-40a6-8313-49a9706f506d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608522075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1608522075
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1260653867
Short name T619
Test name
Test status
Simulation time 214572785 ps
CPU time 1.53 seconds
Started Feb 25 01:45:45 PM PST 24
Finished Feb 25 01:45:47 PM PST 24
Peak memory 200236 kb
Host smart-72281e43-5455-4e69-8fd1-5804b9b429a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260653867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1260653867
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1631748361
Short name T127
Test name
Test status
Simulation time 874153559 ps
CPU time 3.19 seconds
Started Feb 25 01:45:45 PM PST 24
Finished Feb 25 01:45:48 PM PST 24
Peak memory 200280 kb
Host smart-50d7218f-aa62-4629-96e4-799dea6bf391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631748361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1631748361
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2210798187
Short name T600
Test name
Test status
Simulation time 119914629 ps
CPU time 1.18 seconds
Started Feb 25 01:45:47 PM PST 24
Finished Feb 25 01:45:48 PM PST 24
Peak memory 199988 kb
Host smart-11ccfa19-5bd7-4fed-a01e-dd04884a3fbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210798187 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2210798187
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.760203794
Short name T566
Test name
Test status
Simulation time 73955493 ps
CPU time 0.78 seconds
Started Feb 25 01:45:44 PM PST 24
Finished Feb 25 01:45:44 PM PST 24
Peak memory 200008 kb
Host smart-f0843b69-0b3e-45f8-8d49-2f764b554a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760203794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.760203794
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3904746143
Short name T557
Test name
Test status
Simulation time 226572428 ps
CPU time 1.55 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 200176 kb
Host smart-dbee46eb-2e5b-406b-bae5-9c9e7d26fab4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904746143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3904746143
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1875788043
Short name T552
Test name
Test status
Simulation time 197572333 ps
CPU time 1.67 seconds
Started Feb 25 01:45:51 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 200128 kb
Host smart-8141cbbd-ab68-4a2d-8363-645cea1870e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875788043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1875788043
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1889676697
Short name T581
Test name
Test status
Simulation time 778919681 ps
CPU time 2.78 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:55 PM PST 24
Peak memory 200144 kb
Host smart-908ac935-940e-4e3e-8a62-8d1e3ce55551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889676697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1889676697
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.798171471
Short name T577
Test name
Test status
Simulation time 170941331 ps
CPU time 1.56 seconds
Started Feb 25 01:45:47 PM PST 24
Finished Feb 25 01:45:49 PM PST 24
Peak memory 200232 kb
Host smart-fed79d4c-c137-4f3c-8349-22bcbf70d0b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798171471 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.798171471
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.631364584
Short name T116
Test name
Test status
Simulation time 58742602 ps
CPU time 0.8 seconds
Started Feb 25 01:45:44 PM PST 24
Finished Feb 25 01:45:45 PM PST 24
Peak memory 200008 kb
Host smart-2be861aa-40b5-4c1c-b490-b9e029dceb92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631364584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.631364584
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1615588415
Short name T553
Test name
Test status
Simulation time 85495293 ps
CPU time 0.95 seconds
Started Feb 25 01:45:51 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 200016 kb
Host smart-ef69edfc-35dd-4cb8-8cb1-cd30d593f24e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615588415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1615588415
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1763329211
Short name T91
Test name
Test status
Simulation time 206198435 ps
CPU time 2.79 seconds
Started Feb 25 01:45:47 PM PST 24
Finished Feb 25 01:45:50 PM PST 24
Peak memory 200220 kb
Host smart-21620705-d53f-4302-95b3-4ac03bdb7c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763329211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1763329211
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3768012744
Short name T85
Test name
Test status
Simulation time 117952770 ps
CPU time 0.94 seconds
Started Feb 25 01:45:45 PM PST 24
Finished Feb 25 01:45:46 PM PST 24
Peak memory 200040 kb
Host smart-3270057d-475d-426a-a0f9-cee23d7c1a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768012744 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3768012744
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1167912938
Short name T582
Test name
Test status
Simulation time 85537101 ps
CPU time 0.83 seconds
Started Feb 25 01:45:45 PM PST 24
Finished Feb 25 01:45:46 PM PST 24
Peak memory 199996 kb
Host smart-888fb9a3-ab52-4fce-85bd-b1a64fa6cb27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167912938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1167912938
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3241787938
Short name T120
Test name
Test status
Simulation time 144449146 ps
CPU time 1.36 seconds
Started Feb 25 01:45:46 PM PST 24
Finished Feb 25 01:45:48 PM PST 24
Peak memory 200152 kb
Host smart-4c9ac1a7-8388-4578-a240-4b18cef89ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241787938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3241787938
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1080894229
Short name T571
Test name
Test status
Simulation time 179417002 ps
CPU time 2.7 seconds
Started Feb 25 01:45:43 PM PST 24
Finished Feb 25 01:45:46 PM PST 24
Peak memory 200184 kb
Host smart-24b7e09f-cfe5-4519-8f65-1ec63ed54958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080894229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1080894229
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.694176562
Short name T144
Test name
Test status
Simulation time 783741852 ps
CPU time 2.92 seconds
Started Feb 25 01:45:42 PM PST 24
Finished Feb 25 01:45:45 PM PST 24
Peak memory 200148 kb
Host smart-18cc1d00-a196-4a2b-9ca2-7e5a9ed0ed78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694176562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.694176562
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3648468081
Short name T616
Test name
Test status
Simulation time 139858864 ps
CPU time 0.98 seconds
Started Feb 25 01:45:44 PM PST 24
Finished Feb 25 01:45:46 PM PST 24
Peak memory 200056 kb
Host smart-d6c04fce-6f67-491a-ab0c-68c5befe6a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648468081 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3648468081
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1178100747
Short name T568
Test name
Test status
Simulation time 76947980 ps
CPU time 0.83 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 200136 kb
Host smart-599c5887-163b-4594-968e-2d0de4656490
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178100747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1178100747
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.853554207
Short name T586
Test name
Test status
Simulation time 246234749 ps
CPU time 1.66 seconds
Started Feb 25 01:45:45 PM PST 24
Finished Feb 25 01:45:47 PM PST 24
Peak memory 200224 kb
Host smart-adaee982-1a96-4249-b8e5-96ad41f933f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853554207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.853554207
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2273683605
Short name T576
Test name
Test status
Simulation time 119874166 ps
CPU time 1.67 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 208388 kb
Host smart-42eabcf1-7f3f-4c97-ab40-ea8e0fe1a3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273683605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2273683605
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2392305812
Short name T126
Test name
Test status
Simulation time 457951159 ps
CPU time 1.84 seconds
Started Feb 25 01:45:42 PM PST 24
Finished Feb 25 01:45:44 PM PST 24
Peak memory 200228 kb
Host smart-032723a2-87b0-4096-a148-848cfc903964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392305812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2392305812
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2013725796
Short name T567
Test name
Test status
Simulation time 127163802 ps
CPU time 0.95 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 200048 kb
Host smart-f58840a5-a384-4bf0-9c01-6a24dbbc5479
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013725796 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2013725796
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.917713474
Short name T573
Test name
Test status
Simulation time 67665735 ps
CPU time 0.81 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 200020 kb
Host smart-38c36dbe-dda7-4d03-91fa-18f96bb5f415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917713474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.917713474
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2852707974
Short name T589
Test name
Test status
Simulation time 209792271 ps
CPU time 1.43 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:45:59 PM PST 24
Peak memory 200176 kb
Host smart-7be17035-9fec-449c-8730-81251b4c211f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852707974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2852707974
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1816903896
Short name T603
Test name
Test status
Simulation time 153833205 ps
CPU time 2.2 seconds
Started Feb 25 01:45:48 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 200148 kb
Host smart-1b234c22-d81a-416e-a757-0e0156cc34ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816903896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1816903896
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2320874730
Short name T147
Test name
Test status
Simulation time 882672613 ps
CPU time 3.21 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 200248 kb
Host smart-7c47a041-352c-4557-9391-5181d69950f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320874730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2320874730
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2498109049
Short name T591
Test name
Test status
Simulation time 203750056 ps
CPU time 1.33 seconds
Started Feb 25 01:46:05 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 199984 kb
Host smart-73d786d0-06b6-49d5-9dcf-2f06fe19caf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498109049 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2498109049
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1203344878
Short name T609
Test name
Test status
Simulation time 66204840 ps
CPU time 0.74 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 199896 kb
Host smart-c04fc185-f85c-4a33-a0d8-1d784d94f688
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203344878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1203344878
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1148110769
Short name T580
Test name
Test status
Simulation time 123486515 ps
CPU time 1.24 seconds
Started Feb 25 01:45:55 PM PST 24
Finished Feb 25 01:45:56 PM PST 24
Peak memory 200188 kb
Host smart-c17eae9f-234b-4d61-89f8-1f5fb6a14102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148110769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1148110769
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2032346471
Short name T88
Test name
Test status
Simulation time 132870606 ps
CPU time 2.01 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 200128 kb
Host smart-a6747e2e-1168-4fe7-a8ef-fde4397ba3a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032346471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2032346471
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4095390414
Short name T612
Test name
Test status
Simulation time 804199702 ps
CPU time 2.79 seconds
Started Feb 25 01:45:58 PM PST 24
Finished Feb 25 01:46:01 PM PST 24
Peak memory 200192 kb
Host smart-e1257e48-e392-4c03-b1cf-32ea2dd41743
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095390414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4095390414
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3535067825
Short name T562
Test name
Test status
Simulation time 119953771 ps
CPU time 1.16 seconds
Started Feb 25 01:45:55 PM PST 24
Finished Feb 25 01:45:56 PM PST 24
Peak memory 199948 kb
Host smart-d685896a-b2e3-491b-8bc0-875d1b3ae5bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535067825 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3535067825
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2927408874
Short name T601
Test name
Test status
Simulation time 61161496 ps
CPU time 0.8 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 199964 kb
Host smart-365c2de8-d5d6-4a00-8113-1449d4d7ca24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927408874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2927408874
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.393743213
Short name T602
Test name
Test status
Simulation time 99902099 ps
CPU time 1.27 seconds
Started Feb 25 01:46:05 PM PST 24
Finished Feb 25 01:46:06 PM PST 24
Peak memory 200264 kb
Host smart-d82cf8b3-9abc-4aba-b31e-69b687912e6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393743213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.393743213
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1083562120
Short name T86
Test name
Test status
Simulation time 415247115 ps
CPU time 3.16 seconds
Started Feb 25 01:45:53 PM PST 24
Finished Feb 25 01:45:56 PM PST 24
Peak memory 200160 kb
Host smart-0b96d7a1-0abd-4d88-bc9a-6ff7f85ec76f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083562120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1083562120
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1266331980
Short name T123
Test name
Test status
Simulation time 902743104 ps
CPU time 2.99 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 200196 kb
Host smart-60ce6695-3240-4320-89fa-0cc402ff3747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266331980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1266331980
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1743832267
Short name T613
Test name
Test status
Simulation time 179329100 ps
CPU time 1.93 seconds
Started Feb 25 01:46:02 PM PST 24
Finished Feb 25 01:46:04 PM PST 24
Peak memory 208460 kb
Host smart-5c484c5f-d72a-4adf-9a2e-f3477403ef25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743832267 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1743832267
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2016314650
Short name T606
Test name
Test status
Simulation time 70361183 ps
CPU time 0.76 seconds
Started Feb 25 01:45:53 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 200008 kb
Host smart-4c672f41-659e-4ea5-b92b-c72f34942bcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016314650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2016314650
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2170482149
Short name T115
Test name
Test status
Simulation time 136565048 ps
CPU time 1.1 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 200004 kb
Host smart-1a92ad47-85f1-41b6-b518-7f048c1a0931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170482149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2170482149
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3886590668
Short name T594
Test name
Test status
Simulation time 304819283 ps
CPU time 2.39 seconds
Started Feb 25 01:45:56 PM PST 24
Finished Feb 25 01:45:59 PM PST 24
Peak memory 200164 kb
Host smart-bf1f394b-4c8d-4b15-96b2-5bd4feb248c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886590668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3886590668
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1524692280
Short name T122
Test name
Test status
Simulation time 477069374 ps
CPU time 1.79 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:51 PM PST 24
Peak memory 200244 kb
Host smart-67cbe2f5-ef98-4dac-bf1b-a137adcebc6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524692280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1524692280
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2290911253
Short name T572
Test name
Test status
Simulation time 208655812 ps
CPU time 1.57 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:41 PM PST 24
Peak memory 200144 kb
Host smart-2ba94f70-f488-4d7c-a54d-60eabc3c8543
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290911253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
290911253
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3972728418
Short name T555
Test name
Test status
Simulation time 1184924473 ps
CPU time 5.44 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:37 PM PST 24
Peak memory 200268 kb
Host smart-fb04eb5c-1f10-432b-8189-38069a2ed54f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972728418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
972728418
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2833561173
Short name T615
Test name
Test status
Simulation time 95111064 ps
CPU time 0.82 seconds
Started Feb 25 01:45:30 PM PST 24
Finished Feb 25 01:45:31 PM PST 24
Peak memory 200132 kb
Host smart-a2b946b6-804a-409d-bbd2-049254c8e94c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833561173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
833561173
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1719418914
Short name T608
Test name
Test status
Simulation time 115164457 ps
CPU time 1.01 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:32 PM PST 24
Peak memory 199144 kb
Host smart-d1e40a12-401a-4689-8cfa-7bc0383e096a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719418914 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1719418914
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.700336257
Short name T565
Test name
Test status
Simulation time 71189132 ps
CPU time 0.82 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:32 PM PST 24
Peak memory 199200 kb
Host smart-da701d8b-f94f-4196-baff-638a53a68c02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700336257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.700336257
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2471963400
Short name T583
Test name
Test status
Simulation time 132320023 ps
CPU time 1.09 seconds
Started Feb 25 01:45:31 PM PST 24
Finished Feb 25 01:45:33 PM PST 24
Peak memory 200036 kb
Host smart-22bfb15b-f1e0-4495-884e-640ddf9d39e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471963400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2471963400
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3935733768
Short name T548
Test name
Test status
Simulation time 280074484 ps
CPU time 2 seconds
Started Feb 25 01:45:35 PM PST 24
Finished Feb 25 01:45:37 PM PST 24
Peak memory 200132 kb
Host smart-dd119f44-f60b-4b12-bd3e-b98f39211bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935733768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3935733768
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3814415197
Short name T82
Test name
Test status
Simulation time 472032822 ps
CPU time 1.94 seconds
Started Feb 25 01:45:40 PM PST 24
Finished Feb 25 01:45:42 PM PST 24
Peak memory 200196 kb
Host smart-7559d3ca-6ac1-443e-ba85-71d274e82e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814415197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3814415197
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1353444337
Short name T585
Test name
Test status
Simulation time 358751878 ps
CPU time 2.41 seconds
Started Feb 25 01:45:41 PM PST 24
Finished Feb 25 01:45:44 PM PST 24
Peak memory 200176 kb
Host smart-9b6ed335-067e-4457-92b3-6b2927fbb755
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353444337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
353444337
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3908180005
Short name T545
Test name
Test status
Simulation time 1020128650 ps
CPU time 5.12 seconds
Started Feb 25 01:45:37 PM PST 24
Finished Feb 25 01:45:42 PM PST 24
Peak memory 200128 kb
Host smart-c22c436d-324b-4316-bce9-caa46697962b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908180005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
908180005
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.4088141502
Short name T597
Test name
Test status
Simulation time 93237198 ps
CPU time 0.79 seconds
Started Feb 25 01:45:41 PM PST 24
Finished Feb 25 01:45:42 PM PST 24
Peak memory 199924 kb
Host smart-c27067da-1d32-462d-97e5-b8dd216b792f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088141502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.4
088141502
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.661040164
Short name T570
Test name
Test status
Simulation time 141831072 ps
CPU time 0.98 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:40 PM PST 24
Peak memory 200068 kb
Host smart-e4fad397-ecaf-4712-8380-9d2738c46133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661040164 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.661040164
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.243369408
Short name T544
Test name
Test status
Simulation time 72869959 ps
CPU time 0.82 seconds
Started Feb 25 01:45:29 PM PST 24
Finished Feb 25 01:45:30 PM PST 24
Peak memory 200016 kb
Host smart-cb43cff3-a48d-4dad-95f2-e847f7f6fc93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243369408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.243369408
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1232551651
Short name T117
Test name
Test status
Simulation time 195487183 ps
CPU time 1.45 seconds
Started Feb 25 01:45:41 PM PST 24
Finished Feb 25 01:45:43 PM PST 24
Peak memory 200248 kb
Host smart-d9291f5f-06a8-4cc0-adb1-95b1ae07f286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232551651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1232551651
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2957311868
Short name T56
Test name
Test status
Simulation time 368786177 ps
CPU time 2.37 seconds
Started Feb 25 01:45:41 PM PST 24
Finished Feb 25 01:45:44 PM PST 24
Peak memory 200180 kb
Host smart-acbf57c2-a968-43dd-a905-fb679b44300d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957311868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2957311868
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2154787658
Short name T611
Test name
Test status
Simulation time 775951343 ps
CPU time 2.94 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:42 PM PST 24
Peak memory 200232 kb
Host smart-011e7442-046d-4f60-9e42-9d184153fe5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154787658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2154787658
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3791918616
Short name T598
Test name
Test status
Simulation time 107528680 ps
CPU time 1.36 seconds
Started Feb 25 01:45:41 PM PST 24
Finished Feb 25 01:45:43 PM PST 24
Peak memory 200168 kb
Host smart-bbbbfdd1-0d20-42c5-b470-d8117414d1cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791918616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
791918616
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3441548169
Short name T579
Test name
Test status
Simulation time 266040813 ps
CPU time 3.16 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:43 PM PST 24
Peak memory 200196 kb
Host smart-4d6319c8-8456-44ce-a671-bbf2212e68ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441548169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
441548169
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2050204271
Short name T620
Test name
Test status
Simulation time 100489562 ps
CPU time 0.83 seconds
Started Feb 25 01:45:42 PM PST 24
Finished Feb 25 01:45:43 PM PST 24
Peak memory 199964 kb
Host smart-871f42c9-af55-4216-bd83-7f2f25f2782d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050204271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
050204271
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.646516860
Short name T575
Test name
Test status
Simulation time 196747898 ps
CPU time 1.73 seconds
Started Feb 25 01:45:35 PM PST 24
Finished Feb 25 01:45:36 PM PST 24
Peak memory 200164 kb
Host smart-5cd23293-4796-43ee-9c01-535018f0f94d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646516860 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.646516860
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.308038844
Short name T543
Test name
Test status
Simulation time 91448592 ps
CPU time 0.87 seconds
Started Feb 25 01:45:37 PM PST 24
Finished Feb 25 01:45:38 PM PST 24
Peak memory 199944 kb
Host smart-624af58a-463f-4d59-865e-2fbde4ae098b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308038844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.308038844
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.964928071
Short name T618
Test name
Test status
Simulation time 241826361 ps
CPU time 1.49 seconds
Started Feb 25 01:45:39 PM PST 24
Finished Feb 25 01:45:41 PM PST 24
Peak memory 200156 kb
Host smart-294a0933-bc62-46a7-a17a-2475a289dc36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964928071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.964928071
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2532659224
Short name T590
Test name
Test status
Simulation time 114944109 ps
CPU time 1.59 seconds
Started Feb 25 01:45:30 PM PST 24
Finished Feb 25 01:45:32 PM PST 24
Peak memory 200356 kb
Host smart-d80ba0f0-df54-4f6b-b3ff-db6e923d5112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532659224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2532659224
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.873188864
Short name T584
Test name
Test status
Simulation time 467945574 ps
CPU time 1.81 seconds
Started Feb 25 01:45:29 PM PST 24
Finished Feb 25 01:45:31 PM PST 24
Peak memory 200244 kb
Host smart-1c3fe27e-3406-472d-b1f3-e6e7bf7fbb34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873188864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
873188864
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2250511764
Short name T588
Test name
Test status
Simulation time 118151256 ps
CPU time 1.02 seconds
Started Feb 25 01:45:34 PM PST 24
Finished Feb 25 01:45:36 PM PST 24
Peak memory 199996 kb
Host smart-5d57599a-104c-4a5d-bfe7-8deccb770e6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250511764 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2250511764
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3700047260
Short name T119
Test name
Test status
Simulation time 82872234 ps
CPU time 0.83 seconds
Started Feb 25 01:45:32 PM PST 24
Finished Feb 25 01:45:34 PM PST 24
Peak memory 199996 kb
Host smart-3a30a635-9902-4d9c-a627-b121e5874e21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700047260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3700047260
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3717950006
Short name T554
Test name
Test status
Simulation time 286483216 ps
CPU time 1.84 seconds
Started Feb 25 01:45:37 PM PST 24
Finished Feb 25 01:45:39 PM PST 24
Peak memory 200136 kb
Host smart-fceb93b1-7b8b-48b4-b4c3-edddb74ec637
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717950006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3717950006
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2166284714
Short name T125
Test name
Test status
Simulation time 898112197 ps
CPU time 3.14 seconds
Started Feb 25 01:45:37 PM PST 24
Finished Feb 25 01:45:40 PM PST 24
Peak memory 200192 kb
Host smart-037f1c0d-6a23-489e-8e96-530143e9cf03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166284714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2166284714
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3751435301
Short name T550
Test name
Test status
Simulation time 188357756 ps
CPU time 1.79 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 216596 kb
Host smart-b0c8ec07-cbf0-4c1b-be39-f6c4fd27d05c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751435301 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3751435301
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1134215510
Short name T52
Test name
Test status
Simulation time 69327749 ps
CPU time 0.81 seconds
Started Feb 25 01:45:45 PM PST 24
Finished Feb 25 01:45:46 PM PST 24
Peak memory 199912 kb
Host smart-e0de31c9-874a-4ba2-bbdb-a78a1679024d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134215510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1134215510
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1602131459
Short name T559
Test name
Test status
Simulation time 97326279 ps
CPU time 1.29 seconds
Started Feb 25 01:45:44 PM PST 24
Finished Feb 25 01:45:45 PM PST 24
Peak memory 200244 kb
Host smart-1649f4ab-64b7-4712-893d-63247b7b6f6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602131459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1602131459
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1444015637
Short name T592
Test name
Test status
Simulation time 211534661 ps
CPU time 2.78 seconds
Started Feb 25 01:45:34 PM PST 24
Finished Feb 25 01:45:37 PM PST 24
Peak memory 200188 kb
Host smart-2d8956bd-a4db-4262-9755-ad5323bb2cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444015637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1444015637
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1752851914
Short name T145
Test name
Test status
Simulation time 522734158 ps
CPU time 1.93 seconds
Started Feb 25 01:45:34 PM PST 24
Finished Feb 25 01:45:36 PM PST 24
Peak memory 200228 kb
Host smart-a2e93e08-e439-4f0a-83dc-6baa44196136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752851914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1752851914
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.513193084
Short name T617
Test name
Test status
Simulation time 118444920 ps
CPU time 1.22 seconds
Started Feb 25 01:45:47 PM PST 24
Finished Feb 25 01:45:48 PM PST 24
Peak memory 200008 kb
Host smart-6a79f9cf-28ec-4e2f-9cb9-f2639cec8226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513193084 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.513193084
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.289312339
Short name T607
Test name
Test status
Simulation time 75064721 ps
CPU time 0.81 seconds
Started Feb 25 01:45:46 PM PST 24
Finished Feb 25 01:45:47 PM PST 24
Peak memory 199708 kb
Host smart-286b105a-241e-4128-97b4-2563f31c3ffa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289312339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.289312339
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3072891184
Short name T564
Test name
Test status
Simulation time 276287568 ps
CPU time 1.68 seconds
Started Feb 25 01:45:44 PM PST 24
Finished Feb 25 01:45:47 PM PST 24
Peak memory 200252 kb
Host smart-5eb8c1ac-d087-41a7-b9ed-e3651cf86443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072891184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3072891184
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1309672073
Short name T90
Test name
Test status
Simulation time 595652168 ps
CPU time 3.76 seconds
Started Feb 25 01:45:51 PM PST 24
Finished Feb 25 01:45:55 PM PST 24
Peak memory 200156 kb
Host smart-1fbabeee-7b20-4136-99b1-6e477e8dc63c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309672073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1309672073
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2896701804
Short name T587
Test name
Test status
Simulation time 148370347 ps
CPU time 1.1 seconds
Started Feb 25 01:45:52 PM PST 24
Finished Feb 25 01:45:54 PM PST 24
Peak memory 200000 kb
Host smart-1d2f5c5d-d6d9-4838-bce7-4476596a0660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896701804 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2896701804
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1797936862
Short name T614
Test name
Test status
Simulation time 79022740 ps
CPU time 0.86 seconds
Started Feb 25 01:45:43 PM PST 24
Finished Feb 25 01:45:44 PM PST 24
Peak memory 200000 kb
Host smart-58e86413-7c5c-4cd3-9514-a41e0eedd271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797936862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1797936862
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2074114127
Short name T569
Test name
Test status
Simulation time 211522489 ps
CPU time 1.48 seconds
Started Feb 25 01:45:43 PM PST 24
Finished Feb 25 01:45:44 PM PST 24
Peak memory 200180 kb
Host smart-3afce565-eb23-40bb-8a1a-2645f5dc02df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074114127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2074114127
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2057202786
Short name T551
Test name
Test status
Simulation time 419741035 ps
CPU time 3.02 seconds
Started Feb 25 01:45:43 PM PST 24
Finished Feb 25 01:45:46 PM PST 24
Peak memory 200156 kb
Host smart-748ba91e-7b6a-4a43-a74e-38285774e4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057202786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2057202786
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1980433866
Short name T83
Test name
Test status
Simulation time 494752967 ps
CPU time 1.86 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 200248 kb
Host smart-684ba2e0-a091-46bb-9411-6dd137bea0eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980433866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1980433866
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.251174022
Short name T596
Test name
Test status
Simulation time 174190145 ps
CPU time 1.71 seconds
Started Feb 25 01:45:50 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 208428 kb
Host smart-42d8f110-95fb-45f7-a032-936cd5af8f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251174022 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.251174022
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.736441535
Short name T114
Test name
Test status
Simulation time 71780591 ps
CPU time 0.83 seconds
Started Feb 25 01:45:43 PM PST 24
Finished Feb 25 01:45:43 PM PST 24
Peak memory 200004 kb
Host smart-6ac8f875-14e7-4967-8e49-978fb26f52d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736441535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.736441535
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4166923857
Short name T51
Test name
Test status
Simulation time 124161129 ps
CPU time 1.22 seconds
Started Feb 25 01:45:49 PM PST 24
Finished Feb 25 01:45:52 PM PST 24
Peak memory 200200 kb
Host smart-e8a377ba-8ad2-4379-bbac-7350eb78dad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166923857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4166923857
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1643000819
Short name T604
Test name
Test status
Simulation time 426121765 ps
CPU time 3.2 seconds
Started Feb 25 01:45:44 PM PST 24
Finished Feb 25 01:45:48 PM PST 24
Peak memory 200204 kb
Host smart-57809751-cc54-4331-9712-5e491abcae88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643000819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1643000819
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3014352357
Short name T593
Test name
Test status
Simulation time 421278149 ps
CPU time 1.72 seconds
Started Feb 25 01:45:51 PM PST 24
Finished Feb 25 01:45:53 PM PST 24
Peak memory 200172 kb
Host smart-73ffdc4b-639c-4c3c-b1cc-e02a89b36877
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014352357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3014352357
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2644082624
Short name T68
Test name
Test status
Simulation time 71200032 ps
CPU time 0.82 seconds
Started Feb 25 02:23:29 PM PST 24
Finished Feb 25 02:23:30 PM PST 24
Peak memory 200424 kb
Host smart-eed3f506-cf79-46aa-abfd-dc53424a9ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644082624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2644082624
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1239006121
Short name T141
Test name
Test status
Simulation time 2356373446 ps
CPU time 7.86 seconds
Started Feb 25 02:23:26 PM PST 24
Finished Feb 25 02:23:34 PM PST 24
Peak memory 222396 kb
Host smart-f2ff4302-3ee3-4c31-bd3e-38bffb54c5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239006121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1239006121
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2889149503
Short name T263
Test name
Test status
Simulation time 244953565 ps
CPU time 1.09 seconds
Started Feb 25 02:23:28 PM PST 24
Finished Feb 25 02:23:29 PM PST 24
Peak memory 217912 kb
Host smart-2598f0e9-0e52-4c18-8ed2-6db3dd8ce983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889149503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2889149503
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1546357950
Short name T443
Test name
Test status
Simulation time 123483730 ps
CPU time 0.78 seconds
Started Feb 25 02:23:15 PM PST 24
Finished Feb 25 02:23:16 PM PST 24
Peak memory 200328 kb
Host smart-b9e3a1e2-2844-4c8c-bf02-9057df7e8c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546357950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1546357950
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.34650209
Short name T305
Test name
Test status
Simulation time 1084923907 ps
CPU time 5.13 seconds
Started Feb 25 02:23:18 PM PST 24
Finished Feb 25 02:23:23 PM PST 24
Peak memory 200764 kb
Host smart-9e81e22b-547c-462d-88a1-428d62eabeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34650209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.34650209
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2018070077
Short name T63
Test name
Test status
Simulation time 8572345903 ps
CPU time 12.27 seconds
Started Feb 25 02:23:25 PM PST 24
Finished Feb 25 02:23:37 PM PST 24
Peak memory 217480 kb
Host smart-262d70d6-528d-4fa9-89ac-7f2300b4731d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018070077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2018070077
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.941995380
Short name T501
Test name
Test status
Simulation time 112276610 ps
CPU time 1.19 seconds
Started Feb 25 02:23:14 PM PST 24
Finished Feb 25 02:23:15 PM PST 24
Peak memory 200624 kb
Host smart-dc32ad8e-3122-44d4-8541-d4e25f354d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941995380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.941995380
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.236057121
Short name T387
Test name
Test status
Simulation time 199124298 ps
CPU time 1.27 seconds
Started Feb 25 02:23:26 PM PST 24
Finished Feb 25 02:23:27 PM PST 24
Peak memory 200500 kb
Host smart-3e0eea3b-3190-445d-bc44-b05780179e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236057121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.236057121
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.159900607
Short name T289
Test name
Test status
Simulation time 135692570 ps
CPU time 1.66 seconds
Started Feb 25 02:23:16 PM PST 24
Finished Feb 25 02:23:18 PM PST 24
Peak memory 200592 kb
Host smart-4a1c6068-b4aa-4f28-a1ce-92023487b006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159900607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.159900607
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1747852597
Short name T233
Test name
Test status
Simulation time 186369461 ps
CPU time 1.13 seconds
Started Feb 25 02:23:14 PM PST 24
Finished Feb 25 02:23:15 PM PST 24
Peak memory 200448 kb
Host smart-21533ceb-27b3-441f-b038-50d0d2fb202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747852597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1747852597
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.886091487
Short name T407
Test name
Test status
Simulation time 61366993 ps
CPU time 0.7 seconds
Started Feb 25 02:23:32 PM PST 24
Finished Feb 25 02:23:32 PM PST 24
Peak memory 200484 kb
Host smart-a21e7ed2-766f-4d58-8153-2bfb941968cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886091487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.886091487
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2345601860
Short name T43
Test name
Test status
Simulation time 1886458224 ps
CPU time 6.98 seconds
Started Feb 25 02:23:27 PM PST 24
Finished Feb 25 02:23:34 PM PST 24
Peak memory 218544 kb
Host smart-4180fd61-8b76-4199-b664-90875a8b75b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345601860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2345601860
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.50942401
Short name T217
Test name
Test status
Simulation time 244106242 ps
CPU time 1.06 seconds
Started Feb 25 02:23:26 PM PST 24
Finished Feb 25 02:23:27 PM PST 24
Peak memory 217988 kb
Host smart-d19bd91a-8ce3-4a34-9f8a-dbc3ce9fe5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50942401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.50942401
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2970175533
Short name T374
Test name
Test status
Simulation time 187987355 ps
CPU time 0.9 seconds
Started Feb 25 02:23:26 PM PST 24
Finished Feb 25 02:23:27 PM PST 24
Peak memory 200308 kb
Host smart-7ae57f4f-124c-4961-9811-5eb77f28815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970175533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2970175533
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1388923681
Short name T460
Test name
Test status
Simulation time 1610204953 ps
CPU time 6.78 seconds
Started Feb 25 02:23:29 PM PST 24
Finished Feb 25 02:23:36 PM PST 24
Peak memory 200824 kb
Host smart-e409b6a9-eb24-43a4-9fd9-5c6c093aeba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388923681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1388923681
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.4279479263
Short name T60
Test name
Test status
Simulation time 8305978298 ps
CPU time 13.5 seconds
Started Feb 25 02:23:27 PM PST 24
Finished Feb 25 02:23:40 PM PST 24
Peak memory 217568 kb
Host smart-ba319171-8b6e-429b-b4b9-91ec7df748f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279479263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.4279479263
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.4149488947
Short name T404
Test name
Test status
Simulation time 177565574 ps
CPU time 1.17 seconds
Started Feb 25 02:23:30 PM PST 24
Finished Feb 25 02:23:31 PM PST 24
Peak memory 200576 kb
Host smart-1a3afd07-a5db-4494-9ee7-819c63b30512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149488947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.4149488947
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1810352888
Short name T488
Test name
Test status
Simulation time 264651802 ps
CPU time 1.61 seconds
Started Feb 25 02:23:25 PM PST 24
Finished Feb 25 02:23:27 PM PST 24
Peak memory 200700 kb
Host smart-8d6ce0c9-6e18-4a7e-b1e0-83cbacedecc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810352888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1810352888
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3431358059
Short name T453
Test name
Test status
Simulation time 11493868056 ps
CPU time 40.23 seconds
Started Feb 25 02:23:28 PM PST 24
Finished Feb 25 02:24:08 PM PST 24
Peak memory 200864 kb
Host smart-8f9f4243-d098-4262-984d-f616bd497cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431358059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3431358059
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2326089133
Short name T414
Test name
Test status
Simulation time 451909641 ps
CPU time 2.62 seconds
Started Feb 25 02:23:27 PM PST 24
Finished Feb 25 02:23:30 PM PST 24
Peak memory 200588 kb
Host smart-28a3e499-9b92-4e6b-a536-885a0f7a479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326089133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2326089133
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.5899295
Short name T406
Test name
Test status
Simulation time 169444974 ps
CPU time 1.05 seconds
Started Feb 25 02:23:28 PM PST 24
Finished Feb 25 02:23:29 PM PST 24
Peak memory 200496 kb
Host smart-3e16d441-9f3d-4398-8a6b-65324d3f5925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5899295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.5899295
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.414747839
Short name T283
Test name
Test status
Simulation time 2366054451 ps
CPU time 9 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:22 PM PST 24
Peak memory 217756 kb
Host smart-2ef92a5d-8545-4b62-96b4-7823def9ebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414747839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.414747839
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2998731360
Short name T149
Test name
Test status
Simulation time 244493663 ps
CPU time 1.08 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:14 PM PST 24
Peak memory 217864 kb
Host smart-cdf917f4-dcc7-4b30-bd65-58cd431cbf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998731360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2998731360
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3624541953
Short name T224
Test name
Test status
Simulation time 157121247 ps
CPU time 0.82 seconds
Started Feb 25 02:24:16 PM PST 24
Finished Feb 25 02:24:17 PM PST 24
Peak memory 200376 kb
Host smart-9e9e2e3f-3167-4afd-9d85-ef190b8359c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624541953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3624541953
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3920933883
Short name T365
Test name
Test status
Simulation time 1191288244 ps
CPU time 4.68 seconds
Started Feb 25 02:24:15 PM PST 24
Finished Feb 25 02:24:20 PM PST 24
Peak memory 200832 kb
Host smart-f6be8259-4a40-4890-a276-8fbae6450eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920933883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3920933883
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2793963665
Short name T313
Test name
Test status
Simulation time 163458736 ps
CPU time 1.11 seconds
Started Feb 25 02:24:16 PM PST 24
Finished Feb 25 02:24:17 PM PST 24
Peak memory 200500 kb
Host smart-67baa6b8-a462-418b-b1c1-faf8745ab400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793963665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2793963665
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.138814063
Short name T377
Test name
Test status
Simulation time 247703504 ps
CPU time 1.46 seconds
Started Feb 25 02:24:08 PM PST 24
Finished Feb 25 02:24:10 PM PST 24
Peak memory 200736 kb
Host smart-43bd91dd-71aa-491f-9fec-892ee83b6227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138814063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.138814063
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1206816065
Short name T334
Test name
Test status
Simulation time 11736374370 ps
CPU time 44.87 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:58 PM PST 24
Peak memory 200880 kb
Host smart-92052d39-fad5-422c-9094-2a41935dacbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206816065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1206816065
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2917926142
Short name T182
Test name
Test status
Simulation time 385619099 ps
CPU time 2.46 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:16 PM PST 24
Peak memory 200584 kb
Host smart-082f53c4-af69-489b-8aa7-61aca761069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917926142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2917926142
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.315929168
Short name T391
Test name
Test status
Simulation time 78107218 ps
CPU time 0.84 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:14 PM PST 24
Peak memory 200496 kb
Host smart-19d61ce5-ccc4-4f6d-bf66-bbe8c744bb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315929168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.315929168
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3916043413
Short name T372
Test name
Test status
Simulation time 87367348 ps
CPU time 0.82 seconds
Started Feb 25 02:24:12 PM PST 24
Finished Feb 25 02:24:13 PM PST 24
Peak memory 200472 kb
Host smart-27d49268-95c4-4026-8269-0953854c7de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916043413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3916043413
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.575647742
Short name T30
Test name
Test status
Simulation time 1231501593 ps
CPU time 6.03 seconds
Started Feb 25 02:24:15 PM PST 24
Finished Feb 25 02:24:21 PM PST 24
Peak memory 218004 kb
Host smart-a065e3c2-79fb-4924-90a5-5a666010d9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575647742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.575647742
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3379348026
Short name T57
Test name
Test status
Simulation time 245290874 ps
CPU time 1.05 seconds
Started Feb 25 02:24:11 PM PST 24
Finished Feb 25 02:24:13 PM PST 24
Peak memory 218020 kb
Host smart-d2e82aa9-3e99-4f7f-ac0f-0397650fbaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379348026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3379348026
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.4229979960
Short name T214
Test name
Test status
Simulation time 124697796 ps
CPU time 0.87 seconds
Started Feb 25 02:24:12 PM PST 24
Finished Feb 25 02:24:13 PM PST 24
Peak memory 200372 kb
Host smart-9dfd59fe-70c2-4705-bd05-57d4193a4a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229979960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.4229979960
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.710588323
Short name T9
Test name
Test status
Simulation time 1196824914 ps
CPU time 5 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:18 PM PST 24
Peak memory 200768 kb
Host smart-6e610db0-e6fa-41a0-b3f5-0d3e97c3fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710588323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.710588323
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3357477484
Short name T244
Test name
Test status
Simulation time 96147957 ps
CPU time 0.97 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:14 PM PST 24
Peak memory 200500 kb
Host smart-57b66b5d-608c-45e8-bf3c-bf941c1ee1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357477484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3357477484
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2467357056
Short name T434
Test name
Test status
Simulation time 111287849 ps
CPU time 1.21 seconds
Started Feb 25 02:24:17 PM PST 24
Finished Feb 25 02:24:18 PM PST 24
Peak memory 200744 kb
Host smart-3c38eed8-a854-4eff-8162-4959adef0f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467357056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2467357056
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3459871128
Short name T413
Test name
Test status
Simulation time 9611777192 ps
CPU time 46.31 seconds
Started Feb 25 02:24:11 PM PST 24
Finished Feb 25 02:24:57 PM PST 24
Peak memory 200888 kb
Host smart-a6f73f9f-66ff-4158-9a05-3a62e201c0f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459871128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3459871128
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.202000419
Short name T248
Test name
Test status
Simulation time 261986447 ps
CPU time 1.82 seconds
Started Feb 25 02:24:12 PM PST 24
Finished Feb 25 02:24:14 PM PST 24
Peak memory 200580 kb
Host smart-0ff26762-a0eb-4215-bc8a-df0c0c3e0789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202000419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.202000419
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1629457460
Short name T234
Test name
Test status
Simulation time 262025780 ps
CPU time 1.55 seconds
Started Feb 25 02:24:16 PM PST 24
Finished Feb 25 02:24:18 PM PST 24
Peak memory 200528 kb
Host smart-3b8c7293-e639-4996-9308-f2270e9453ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629457460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1629457460
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4055541871
Short name T353
Test name
Test status
Simulation time 60617993 ps
CPU time 0.72 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:24 PM PST 24
Peak memory 200476 kb
Host smart-c0c449cb-83b9-45a9-8611-8bae5d15cd0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055541871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4055541871
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.295933389
Short name T423
Test name
Test status
Simulation time 1885972525 ps
CPU time 7.38 seconds
Started Feb 25 02:24:21 PM PST 24
Finished Feb 25 02:24:28 PM PST 24
Peak memory 218004 kb
Host smart-723bb0e3-2c5b-4dd0-9f62-f34d1e9bbf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295933389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.295933389
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1748838490
Short name T523
Test name
Test status
Simulation time 243655803 ps
CPU time 1.13 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:27 PM PST 24
Peak memory 217988 kb
Host smart-f37a2945-73a0-4f54-88ca-70b367b89c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748838490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1748838490
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3152871007
Short name T277
Test name
Test status
Simulation time 1776300986 ps
CPU time 6.69 seconds
Started Feb 25 02:24:12 PM PST 24
Finished Feb 25 02:24:19 PM PST 24
Peak memory 200776 kb
Host smart-562419be-1935-4e83-8878-777b036126c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152871007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3152871007
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3777989745
Short name T176
Test name
Test status
Simulation time 100581250 ps
CPU time 1 seconds
Started Feb 25 02:24:13 PM PST 24
Finished Feb 25 02:24:14 PM PST 24
Peak memory 200460 kb
Host smart-163cb4c3-207b-4d8c-89b2-c1e43f770a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777989745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3777989745
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3293488500
Short name T78
Test name
Test status
Simulation time 116897939 ps
CPU time 1.17 seconds
Started Feb 25 02:24:16 PM PST 24
Finished Feb 25 02:24:17 PM PST 24
Peak memory 200704 kb
Host smart-aba9f5d2-438c-443f-8736-e7306c78c2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293488500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3293488500
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3591166603
Short name T282
Test name
Test status
Simulation time 2065373523 ps
CPU time 10.28 seconds
Started Feb 25 02:24:23 PM PST 24
Finished Feb 25 02:24:33 PM PST 24
Peak memory 200740 kb
Host smart-7ae59703-155a-4625-aebd-50ee6b1c0500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591166603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3591166603
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2014141583
Short name T100
Test name
Test status
Simulation time 495916012 ps
CPU time 2.72 seconds
Started Feb 25 02:24:16 PM PST 24
Finished Feb 25 02:24:19 PM PST 24
Peak memory 200556 kb
Host smart-4d558c33-7195-42be-b8c0-cfcf1e853223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014141583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2014141583
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2755420055
Short name T200
Test name
Test status
Simulation time 89458164 ps
CPU time 0.9 seconds
Started Feb 25 02:24:17 PM PST 24
Finished Feb 25 02:24:18 PM PST 24
Peak memory 200504 kb
Host smart-d388a687-4bfd-4fb3-862d-4bf9861ff591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755420055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2755420055
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.328098587
Short name T193
Test name
Test status
Simulation time 64701835 ps
CPU time 0.75 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200488 kb
Host smart-3fc5e307-9f82-455d-93e9-ddf179251e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328098587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.328098587
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3376524502
Short name T273
Test name
Test status
Simulation time 1882929455 ps
CPU time 7.26 seconds
Started Feb 25 02:24:21 PM PST 24
Finished Feb 25 02:24:29 PM PST 24
Peak memory 219024 kb
Host smart-0d9e2083-819a-4d72-8c0e-0f65ab5819c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376524502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3376524502
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1528661275
Short name T181
Test name
Test status
Simulation time 244782004 ps
CPU time 1.11 seconds
Started Feb 25 02:24:23 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 217988 kb
Host smart-5d3043ee-2518-4a60-a5e1-69600bbda5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528661275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1528661275
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.4000261242
Short name T18
Test name
Test status
Simulation time 140533906 ps
CPU time 0.86 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200372 kb
Host smart-a74f73b0-1ffa-4989-aedf-7dfd246840f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000261242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4000261242
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3352209848
Short name T242
Test name
Test status
Simulation time 1013215171 ps
CPU time 5.5 seconds
Started Feb 25 02:24:23 PM PST 24
Finished Feb 25 02:24:29 PM PST 24
Peak memory 200740 kb
Host smart-b25cd2a1-cbe2-479e-91b5-3eb7323d74f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352209848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3352209848
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.79062571
Short name T205
Test name
Test status
Simulation time 170154364 ps
CPU time 1.16 seconds
Started Feb 25 02:24:22 PM PST 24
Finished Feb 25 02:24:23 PM PST 24
Peak memory 200568 kb
Host smart-9ae1d1eb-e07d-462b-9ff2-82c13826ccde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79062571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.79062571
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3150849295
Short name T136
Test name
Test status
Simulation time 127156289 ps
CPU time 1.17 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200700 kb
Host smart-d9ac3ce5-8853-48e9-a342-7e0a87a0ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150849295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3150849295
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2772333645
Short name T471
Test name
Test status
Simulation time 8613558744 ps
CPU time 34.64 seconds
Started Feb 25 02:24:20 PM PST 24
Finished Feb 25 02:24:55 PM PST 24
Peak memory 200900 kb
Host smart-5b58ac03-ccda-464a-be44-eef7a9509ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772333645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2772333645
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.7637669
Short name T280
Test name
Test status
Simulation time 544210608 ps
CPU time 2.91 seconds
Started Feb 25 02:24:23 PM PST 24
Finished Feb 25 02:24:26 PM PST 24
Peak memory 200612 kb
Host smart-5b14b97d-6fe9-403b-bdfa-2b3b263653da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7637669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.7637669
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3473919826
Short name T180
Test name
Test status
Simulation time 149317487 ps
CPU time 1.15 seconds
Started Feb 25 02:24:27 PM PST 24
Finished Feb 25 02:24:28 PM PST 24
Peak memory 200496 kb
Host smart-ef7eb128-c3b7-4c8d-8784-84b0eb348b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473919826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3473919826
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3891912463
Short name T179
Test name
Test status
Simulation time 58496783 ps
CPU time 0.72 seconds
Started Feb 25 02:24:21 PM PST 24
Finished Feb 25 02:24:22 PM PST 24
Peak memory 200488 kb
Host smart-4e55b6b6-b48c-4469-a448-4d3abd5c8736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891912463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3891912463
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2635494824
Short name T321
Test name
Test status
Simulation time 1886702577 ps
CPU time 7.48 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:32 PM PST 24
Peak memory 221516 kb
Host smart-7d98b95c-f12a-4480-95f7-51b4ba6447d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635494824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2635494824
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2868855948
Short name T459
Test name
Test status
Simulation time 244080279 ps
CPU time 1.07 seconds
Started Feb 25 02:24:21 PM PST 24
Finished Feb 25 02:24:23 PM PST 24
Peak memory 217936 kb
Host smart-102c3858-dad9-4465-afd3-6943df2046e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868855948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2868855948
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1712318313
Short name T186
Test name
Test status
Simulation time 105118408 ps
CPU time 0.74 seconds
Started Feb 25 02:24:23 PM PST 24
Finished Feb 25 02:24:24 PM PST 24
Peak memory 200384 kb
Host smart-5f65a8f6-ce1e-4fd9-b1b1-4e01f3e85a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712318313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1712318313
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1926312604
Short name T538
Test name
Test status
Simulation time 1560298787 ps
CPU time 6.57 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:31 PM PST 24
Peak memory 200732 kb
Host smart-8b59b67b-7ade-4dad-9a82-edcadc9edba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926312604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1926312604
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.467306210
Short name T247
Test name
Test status
Simulation time 98689774 ps
CPU time 0.99 seconds
Started Feb 25 02:24:23 PM PST 24
Finished Feb 25 02:24:24 PM PST 24
Peak memory 200496 kb
Host smart-e7afe169-805f-4ad7-92ae-7b2af4dafa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467306210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.467306210
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2168514451
Short name T344
Test name
Test status
Simulation time 193151917 ps
CPU time 1.51 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:27 PM PST 24
Peak memory 200708 kb
Host smart-3ebea028-34b8-4251-a917-f41ec4f7db04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168514451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2168514451
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.4059589659
Short name T94
Test name
Test status
Simulation time 1304744548 ps
CPU time 6 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:31 PM PST 24
Peak memory 200752 kb
Host smart-175ac056-b264-46dd-9fa6-f931a7cce8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059589659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4059589659
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3429135481
Short name T268
Test name
Test status
Simulation time 389822162 ps
CPU time 2.57 seconds
Started Feb 25 02:24:21 PM PST 24
Finished Feb 25 02:24:23 PM PST 24
Peak memory 200624 kb
Host smart-37c1c68b-227d-45aa-adda-d77cb9bf158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429135481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3429135481
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2510390456
Short name T439
Test name
Test status
Simulation time 112152053 ps
CPU time 0.95 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200536 kb
Host smart-320e7c11-3f92-4de4-a247-2663cabeb077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510390456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2510390456
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3475804790
Short name T173
Test name
Test status
Simulation time 68037845 ps
CPU time 0.73 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:27 PM PST 24
Peak memory 200476 kb
Host smart-4eb7a842-a88c-4e74-808b-14e560dad7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475804790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3475804790
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3716452368
Short name T487
Test name
Test status
Simulation time 2370386350 ps
CPU time 8.56 seconds
Started Feb 25 02:24:23 PM PST 24
Finished Feb 25 02:24:32 PM PST 24
Peak memory 217796 kb
Host smart-5d6b09f3-62a5-4715-a4c4-db844b4fedc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716452368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3716452368
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1480582737
Short name T498
Test name
Test status
Simulation time 244910550 ps
CPU time 1.1 seconds
Started Feb 25 02:24:22 PM PST 24
Finished Feb 25 02:24:24 PM PST 24
Peak memory 217956 kb
Host smart-18e3ac99-cefd-4a71-8ce2-a66b0510c1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480582737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1480582737
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1964282033
Short name T170
Test name
Test status
Simulation time 173415880 ps
CPU time 0.85 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:27 PM PST 24
Peak memory 200364 kb
Host smart-64d19161-4018-4983-9eb7-177602a4d7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964282033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1964282033
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.673910815
Short name T8
Test name
Test status
Simulation time 1268782595 ps
CPU time 5.26 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:30 PM PST 24
Peak memory 200796 kb
Host smart-f3641d73-122d-4bfc-add5-d17c75b9715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673910815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.673910815
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1907447831
Short name T431
Test name
Test status
Simulation time 106535007 ps
CPU time 1.05 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:26 PM PST 24
Peak memory 200540 kb
Host smart-306100c1-0187-4edf-8137-1120fb2eda15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907447831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1907447831
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3826298829
Short name T169
Test name
Test status
Simulation time 119446784 ps
CPU time 1.16 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:26 PM PST 24
Peak memory 200752 kb
Host smart-26dac1fa-bf2d-4279-8c35-fe636e5bcf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826298829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3826298829
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.647224465
Short name T401
Test name
Test status
Simulation time 10247692825 ps
CPU time 37.18 seconds
Started Feb 25 02:24:22 PM PST 24
Finished Feb 25 02:25:00 PM PST 24
Peak memory 200860 kb
Host smart-d19f6dd3-cc2d-4a40-a1a6-d12395b98a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647224465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.647224465
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2648324668
Short name T241
Test name
Test status
Simulation time 140237677 ps
CPU time 1.72 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:28 PM PST 24
Peak memory 200552 kb
Host smart-037b2d0c-b52d-43f2-928e-d05a0d321ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648324668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2648324668
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2464378814
Short name T456
Test name
Test status
Simulation time 89107592 ps
CPU time 0.87 seconds
Started Feb 25 02:24:21 PM PST 24
Finished Feb 25 02:24:22 PM PST 24
Peak memory 200500 kb
Host smart-8777f836-2ce0-4614-9bdb-f93abd7085f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464378814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2464378814
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2784735297
Short name T335
Test name
Test status
Simulation time 64735298 ps
CPU time 0.71 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200492 kb
Host smart-fac39de0-5c38-4aa0-88f0-57d6583a51db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784735297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2784735297
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1932593987
Short name T491
Test name
Test status
Simulation time 2354839582 ps
CPU time 9.26 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:34 PM PST 24
Peak memory 219412 kb
Host smart-2d336770-42bc-4c09-9091-9ac5e7e0a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932593987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1932593987
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.30420526
Short name T211
Test name
Test status
Simulation time 243655772 ps
CPU time 1.13 seconds
Started Feb 25 02:24:25 PM PST 24
Finished Feb 25 02:24:26 PM PST 24
Peak memory 217984 kb
Host smart-803d6a1a-c683-4b76-a3f0-101ee51f3a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30420526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.30420526
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.716474477
Short name T294
Test name
Test status
Simulation time 200941326 ps
CPU time 0.87 seconds
Started Feb 25 02:24:23 PM PST 24
Finished Feb 25 02:24:24 PM PST 24
Peak memory 200328 kb
Host smart-f9f3e254-87ff-4a5b-9917-2fd6e3b917e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716474477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.716474477
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2412949498
Short name T535
Test name
Test status
Simulation time 1448288653 ps
CPU time 5.65 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:32 PM PST 24
Peak memory 200800 kb
Host smart-4fba3d3b-cc79-4f5d-acfa-6871157354ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412949498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2412949498
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2903177316
Short name T38
Test name
Test status
Simulation time 164495402 ps
CPU time 1.27 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:27 PM PST 24
Peak memory 200504 kb
Host smart-915533ab-90b0-4fed-8924-87d08fc8bae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903177316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2903177316
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2231438755
Short name T140
Test name
Test status
Simulation time 236708277 ps
CPU time 1.47 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200720 kb
Host smart-f30cd51a-5b23-45f6-beb7-c6b1ef4c8142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231438755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2231438755
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2334238071
Short name T364
Test name
Test status
Simulation time 1851668480 ps
CPU time 6.88 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:31 PM PST 24
Peak memory 200724 kb
Host smart-7d051130-b742-4ed9-9b81-6db331eb4121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334238071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2334238071
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1763338330
Short name T518
Test name
Test status
Simulation time 274619979 ps
CPU time 1.77 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:28 PM PST 24
Peak memory 200288 kb
Host smart-1403c070-19d6-4668-a7c8-3933017450cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763338330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1763338330
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3869525090
Short name T171
Test name
Test status
Simulation time 168492242 ps
CPU time 1.13 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200500 kb
Host smart-24c8f56b-19c8-4afa-b009-b6da0d8e47d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869525090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3869525090
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2640602139
Short name T312
Test name
Test status
Simulation time 65539146 ps
CPU time 0.74 seconds
Started Feb 25 02:24:41 PM PST 24
Finished Feb 25 02:24:42 PM PST 24
Peak memory 200496 kb
Host smart-869d26fe-995a-49b4-bd96-7eaf6ec97ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640602139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2640602139
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2494441796
Short name T304
Test name
Test status
Simulation time 1876546629 ps
CPU time 7.78 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:34 PM PST 24
Peak memory 217436 kb
Host smart-1baa32e1-41c3-4a00-a7e4-0bf62663ff4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494441796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2494441796
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.906132313
Short name T227
Test name
Test status
Simulation time 244953841 ps
CPU time 1.05 seconds
Started Feb 25 02:24:40 PM PST 24
Finished Feb 25 02:24:41 PM PST 24
Peak memory 217788 kb
Host smart-e4555649-f1ba-4294-954e-2b752aa5e00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906132313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.906132313
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.779271643
Short name T527
Test name
Test status
Simulation time 173662287 ps
CPU time 0.82 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200384 kb
Host smart-94ee5b7f-1941-4c13-a5c4-381df8b20098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779271643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.779271643
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.804139016
Short name T260
Test name
Test status
Simulation time 1423883468 ps
CPU time 5.89 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:30 PM PST 24
Peak memory 200788 kb
Host smart-bd83023a-220c-4355-849d-c50154505f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804139016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.804139016
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.104254739
Short name T433
Test name
Test status
Simulation time 176691121 ps
CPU time 1.12 seconds
Started Feb 25 02:24:26 PM PST 24
Finished Feb 25 02:24:27 PM PST 24
Peak memory 200208 kb
Host smart-5c8b49b9-f217-4c16-8a6c-b9fd7feacffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104254739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.104254739
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1012388937
Short name T330
Test name
Test status
Simulation time 109706597 ps
CPU time 1.17 seconds
Started Feb 25 02:24:27 PM PST 24
Finished Feb 25 02:24:28 PM PST 24
Peak memory 200736 kb
Host smart-b3e8775e-9eaf-482f-90f2-31bc509ba38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012388937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1012388937
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1099569512
Short name T462
Test name
Test status
Simulation time 2137124931 ps
CPU time 10.66 seconds
Started Feb 25 02:24:34 PM PST 24
Finished Feb 25 02:24:45 PM PST 24
Peak memory 200792 kb
Host smart-7cd918e9-7b68-4917-b073-67d2c961f79e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099569512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1099569512
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2231161324
Short name T525
Test name
Test status
Simulation time 126901161 ps
CPU time 1.71 seconds
Started Feb 25 02:24:28 PM PST 24
Finished Feb 25 02:24:30 PM PST 24
Peak memory 200516 kb
Host smart-489f1fdb-5a1c-4049-a58f-473f59fcc7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231161324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2231161324
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3316586010
Short name T532
Test name
Test status
Simulation time 146112151 ps
CPU time 0.99 seconds
Started Feb 25 02:24:24 PM PST 24
Finished Feb 25 02:24:25 PM PST 24
Peak memory 200500 kb
Host smart-4fb55983-5f76-4132-8b71-9a6f253b6c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316586010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3316586010
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2662640807
Short name T288
Test name
Test status
Simulation time 61689777 ps
CPU time 0.75 seconds
Started Feb 25 02:24:34 PM PST 24
Finished Feb 25 02:24:35 PM PST 24
Peak memory 200476 kb
Host smart-3049c6f3-2548-4fb7-ae46-e7aa8a93b0fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662640807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2662640807
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2016545568
Short name T450
Test name
Test status
Simulation time 1907221574 ps
CPU time 7.43 seconds
Started Feb 25 02:24:40 PM PST 24
Finished Feb 25 02:24:47 PM PST 24
Peak memory 218548 kb
Host smart-30ac0c26-4514-4565-922e-8234c1323865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016545568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2016545568
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3820055452
Short name T230
Test name
Test status
Simulation time 243913243 ps
CPU time 1.16 seconds
Started Feb 25 02:24:42 PM PST 24
Finished Feb 25 02:24:43 PM PST 24
Peak memory 217872 kb
Host smart-5206ff17-e646-4e12-b048-0022daa4bdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820055452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3820055452
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2731911266
Short name T437
Test name
Test status
Simulation time 170942425 ps
CPU time 0.85 seconds
Started Feb 25 02:24:32 PM PST 24
Finished Feb 25 02:24:34 PM PST 24
Peak memory 200408 kb
Host smart-db31b83f-e556-4770-8e24-8e50edbe29be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731911266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2731911266
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3134427100
Short name T343
Test name
Test status
Simulation time 1245281292 ps
CPU time 5.46 seconds
Started Feb 25 02:24:42 PM PST 24
Finished Feb 25 02:24:47 PM PST 24
Peak memory 200496 kb
Host smart-504284d2-487d-4c18-93f0-a80bdc726b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134427100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3134427100
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1009163743
Short name T358
Test name
Test status
Simulation time 103784952 ps
CPU time 1.03 seconds
Started Feb 25 02:24:42 PM PST 24
Finished Feb 25 02:24:43 PM PST 24
Peak memory 200544 kb
Host smart-8e67f89c-5766-440f-9962-371ad3589920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009163743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1009163743
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.141316882
Short name T183
Test name
Test status
Simulation time 112202254 ps
CPU time 1.09 seconds
Started Feb 25 02:24:41 PM PST 24
Finished Feb 25 02:24:42 PM PST 24
Peak memory 200724 kb
Host smart-c682bf8a-d76a-4c49-aa78-5e20de55136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141316882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.141316882
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.584581797
Short name T112
Test name
Test status
Simulation time 11347408892 ps
CPU time 36.23 seconds
Started Feb 25 02:24:33 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200852 kb
Host smart-f717a0ac-bf5f-47f4-8ef0-bdc81ca9f00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584581797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.584581797
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.68411562
Short name T213
Test name
Test status
Simulation time 117735732 ps
CPU time 1.57 seconds
Started Feb 25 02:24:41 PM PST 24
Finished Feb 25 02:24:42 PM PST 24
Peak memory 200580 kb
Host smart-1a22cf22-947e-46fa-aa04-86c77f910d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68411562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.68411562
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.4193990552
Short name T452
Test name
Test status
Simulation time 290205474 ps
CPU time 1.6 seconds
Started Feb 25 02:24:32 PM PST 24
Finished Feb 25 02:24:35 PM PST 24
Peak memory 200680 kb
Host smart-91a2899d-b146-4695-abaa-7fbcb3e276c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193990552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4193990552
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3161907765
Short name T104
Test name
Test status
Simulation time 62909217 ps
CPU time 0.74 seconds
Started Feb 25 02:24:39 PM PST 24
Finished Feb 25 02:24:40 PM PST 24
Peak memory 200488 kb
Host smart-5d4c5111-f166-4610-b8c1-a5c53bf6319f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161907765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3161907765
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3687040293
Short name T416
Test name
Test status
Simulation time 246280765 ps
CPU time 1.02 seconds
Started Feb 25 02:24:37 PM PST 24
Finished Feb 25 02:24:39 PM PST 24
Peak memory 217980 kb
Host smart-5af3bca4-12f9-490d-9ba4-6df01cfcbd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687040293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3687040293
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.4268410032
Short name T510
Test name
Test status
Simulation time 130082048 ps
CPU time 0.78 seconds
Started Feb 25 02:24:33 PM PST 24
Finished Feb 25 02:24:34 PM PST 24
Peak memory 200376 kb
Host smart-dac9fdcf-5c2b-4616-9849-3b110283ae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268410032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.4268410032
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3151500700
Short name T237
Test name
Test status
Simulation time 1097996201 ps
CPU time 5.59 seconds
Started Feb 25 02:24:34 PM PST 24
Finished Feb 25 02:24:40 PM PST 24
Peak memory 200812 kb
Host smart-6ec2d516-5c7b-43c1-839c-a3dcbd2015cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151500700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3151500700
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.707026120
Short name T223
Test name
Test status
Simulation time 102124101 ps
CPU time 0.99 seconds
Started Feb 25 02:24:44 PM PST 24
Finished Feb 25 02:24:45 PM PST 24
Peak memory 200512 kb
Host smart-4695a827-8591-49f4-abba-6eed3a8c56da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707026120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.707026120
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2078588968
Short name T204
Test name
Test status
Simulation time 117067191 ps
CPU time 1.18 seconds
Started Feb 25 02:24:40 PM PST 24
Finished Feb 25 02:24:41 PM PST 24
Peak memory 200708 kb
Host smart-1009cdad-9c22-48e3-b548-a3a721e4d53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078588968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2078588968
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2839789524
Short name T386
Test name
Test status
Simulation time 1177536625 ps
CPU time 5.5 seconds
Started Feb 25 02:24:42 PM PST 24
Finished Feb 25 02:24:47 PM PST 24
Peak memory 200784 kb
Host smart-41084569-1353-44a1-8724-f0e2ec40dde2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839789524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2839789524
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4089947826
Short name T314
Test name
Test status
Simulation time 383536370 ps
CPU time 2.15 seconds
Started Feb 25 02:24:31 PM PST 24
Finished Feb 25 02:24:34 PM PST 24
Peak memory 200556 kb
Host smart-87027408-e8c3-4ce6-848c-abf495679ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089947826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4089947826
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3815269963
Short name T155
Test name
Test status
Simulation time 68328458 ps
CPU time 0.81 seconds
Started Feb 25 02:24:41 PM PST 24
Finished Feb 25 02:24:42 PM PST 24
Peak memory 200648 kb
Host smart-946c10bc-ab75-4943-9097-14f876f25dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815269963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3815269963
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2352694409
Short name T403
Test name
Test status
Simulation time 74822098 ps
CPU time 0.78 seconds
Started Feb 25 02:23:32 PM PST 24
Finished Feb 25 02:23:33 PM PST 24
Peak memory 200432 kb
Host smart-33195457-9534-423e-a36d-df30d0ac97c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352694409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2352694409
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2876474692
Short name T495
Test name
Test status
Simulation time 1228866649 ps
CPU time 5.67 seconds
Started Feb 25 02:23:36 PM PST 24
Finished Feb 25 02:23:42 PM PST 24
Peak memory 217384 kb
Host smart-28f02ef1-19f4-41ed-9cb5-36a089bda390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876474692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2876474692
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.604605568
Short name T189
Test name
Test status
Simulation time 243996319 ps
CPU time 1.1 seconds
Started Feb 25 02:23:34 PM PST 24
Finished Feb 25 02:23:35 PM PST 24
Peak memory 217872 kb
Host smart-16157c4b-2af9-49c7-a8f2-4e5f297192e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604605568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.604605568
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4102213233
Short name T420
Test name
Test status
Simulation time 119200733 ps
CPU time 0.79 seconds
Started Feb 25 02:23:27 PM PST 24
Finished Feb 25 02:23:28 PM PST 24
Peak memory 200320 kb
Host smart-d463de01-96f1-4169-b9f1-8c68e6569990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102213233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4102213233
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1286506386
Short name T99
Test name
Test status
Simulation time 866621503 ps
CPU time 4.53 seconds
Started Feb 25 02:23:26 PM PST 24
Finished Feb 25 02:23:30 PM PST 24
Peak memory 200784 kb
Host smart-7f1dc1c1-5851-4d52-823a-e57494ac116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286506386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1286506386
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.578185955
Short name T59
Test name
Test status
Simulation time 10234864010 ps
CPU time 16.05 seconds
Started Feb 25 02:23:34 PM PST 24
Finished Feb 25 02:23:50 PM PST 24
Peak memory 217552 kb
Host smart-13ab5865-2573-4fb2-8a9e-00c7e4829ca2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578185955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.578185955
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2648481184
Short name T226
Test name
Test status
Simulation time 105373621 ps
CPU time 1.01 seconds
Started Feb 25 02:23:33 PM PST 24
Finished Feb 25 02:23:34 PM PST 24
Peak memory 200512 kb
Host smart-b61542e1-3236-4e4d-8966-0089310c7b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648481184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2648481184
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.608517523
Short name T383
Test name
Test status
Simulation time 124779628 ps
CPU time 1.14 seconds
Started Feb 25 02:23:25 PM PST 24
Finished Feb 25 02:23:26 PM PST 24
Peak memory 200732 kb
Host smart-b7f7a6b0-bc40-42b9-bce1-84070ced3e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608517523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.608517523
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2553536387
Short name T373
Test name
Test status
Simulation time 1229532730 ps
CPU time 6.51 seconds
Started Feb 25 02:23:38 PM PST 24
Finished Feb 25 02:23:45 PM PST 24
Peak memory 200796 kb
Host smart-f45d92d3-a9d4-4d27-9631-4a1dbebe6c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553536387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2553536387
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1939945923
Short name T159
Test name
Test status
Simulation time 260109917 ps
CPU time 1.78 seconds
Started Feb 25 02:23:35 PM PST 24
Finished Feb 25 02:23:37 PM PST 24
Peak memory 200560 kb
Host smart-f28846d6-2d65-4e77-8585-0140d17fdeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939945923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1939945923
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.783334473
Short name T502
Test name
Test status
Simulation time 192778325 ps
CPU time 1.2 seconds
Started Feb 25 02:23:26 PM PST 24
Finished Feb 25 02:23:27 PM PST 24
Peak memory 200500 kb
Host smart-2aa1890a-a40d-4df6-bd13-80419a6f1dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783334473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.783334473
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1496458950
Short name T428
Test name
Test status
Simulation time 64655724 ps
CPU time 0.74 seconds
Started Feb 25 02:24:39 PM PST 24
Finished Feb 25 02:24:39 PM PST 24
Peak memory 200492 kb
Host smart-5a6e928f-7786-4122-ad1a-acff9f56ee93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496458950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1496458950
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2381962031
Short name T336
Test name
Test status
Simulation time 2183753299 ps
CPU time 8.14 seconds
Started Feb 25 02:24:42 PM PST 24
Finished Feb 25 02:24:51 PM PST 24
Peak memory 218108 kb
Host smart-642ff0ec-171e-4a80-8058-ef6a3078c2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381962031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2381962031
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.431713738
Short name T497
Test name
Test status
Simulation time 245029854 ps
CPU time 1.04 seconds
Started Feb 25 02:24:41 PM PST 24
Finished Feb 25 02:24:42 PM PST 24
Peak memory 217972 kb
Host smart-d97c4a82-ec89-4bf3-b888-06949a73b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431713738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.431713738
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.220203862
Short name T13
Test name
Test status
Simulation time 138247896 ps
CPU time 0.81 seconds
Started Feb 25 02:24:47 PM PST 24
Finished Feb 25 02:24:48 PM PST 24
Peak memory 200364 kb
Host smart-36c05763-1964-4325-997d-c2ffb3e4f7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220203862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.220203862
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1540425255
Short name T411
Test name
Test status
Simulation time 1092209929 ps
CPU time 4.99 seconds
Started Feb 25 02:24:48 PM PST 24
Finished Feb 25 02:24:53 PM PST 24
Peak memory 200800 kb
Host smart-ff5bfcc4-171c-41c9-ab49-d4f455daa4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540425255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1540425255
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2163362136
Short name T468
Test name
Test status
Simulation time 174538961 ps
CPU time 1.15 seconds
Started Feb 25 02:24:42 PM PST 24
Finished Feb 25 02:24:43 PM PST 24
Peak memory 200160 kb
Host smart-9c3f656d-473a-4ce4-9377-865329cef6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163362136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2163362136
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.577490305
Short name T138
Test name
Test status
Simulation time 240107182 ps
CPU time 1.5 seconds
Started Feb 25 02:24:42 PM PST 24
Finished Feb 25 02:24:44 PM PST 24
Peak memory 200728 kb
Host smart-3818a07b-5f19-4ff0-9b53-d39cf110b048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577490305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.577490305
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3508118670
Short name T380
Test name
Test status
Simulation time 5609164327 ps
CPU time 20.7 seconds
Started Feb 25 02:24:44 PM PST 24
Finished Feb 25 02:25:05 PM PST 24
Peak memory 200908 kb
Host smart-1db39d01-573f-4aa6-944d-891e6673579b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508118670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3508118670
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2617744752
Short name T503
Test name
Test status
Simulation time 122155223 ps
CPU time 1.56 seconds
Started Feb 25 02:24:45 PM PST 24
Finished Feb 25 02:24:46 PM PST 24
Peak memory 200564 kb
Host smart-73bfdd50-16a9-4c66-b072-68037d408e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617744752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2617744752
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2166288466
Short name T477
Test name
Test status
Simulation time 146790297 ps
CPU time 1.18 seconds
Started Feb 25 02:24:45 PM PST 24
Finished Feb 25 02:24:46 PM PST 24
Peak memory 200496 kb
Host smart-470bf942-9746-4367-899e-f4e2c2150a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166288466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2166288466
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1607636000
Short name T485
Test name
Test status
Simulation time 72201230 ps
CPU time 0.79 seconds
Started Feb 25 02:24:53 PM PST 24
Finished Feb 25 02:24:54 PM PST 24
Peak memory 200476 kb
Host smart-4a5fcd5b-b71d-41af-9eea-8429d681ecf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607636000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1607636000
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3752501925
Short name T436
Test name
Test status
Simulation time 1896671584 ps
CPU time 7.68 seconds
Started Feb 25 02:24:51 PM PST 24
Finished Feb 25 02:24:59 PM PST 24
Peak memory 221696 kb
Host smart-d55e49f3-4436-46aa-a2c3-20dbc5de0e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752501925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3752501925
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.634169125
Short name T36
Test name
Test status
Simulation time 243792290 ps
CPU time 1.07 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:24:55 PM PST 24
Peak memory 217944 kb
Host smart-363eb7c9-79aa-4180-a8a7-81743bac3bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634169125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.634169125
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2432961616
Short name T418
Test name
Test status
Simulation time 133332812 ps
CPU time 0.79 seconds
Started Feb 25 02:24:41 PM PST 24
Finished Feb 25 02:24:42 PM PST 24
Peak memory 200312 kb
Host smart-e94ded53-6ce7-4f93-ba6e-fb407631eaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432961616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2432961616
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3889681575
Short name T232
Test name
Test status
Simulation time 1631209342 ps
CPU time 5.85 seconds
Started Feb 25 02:24:45 PM PST 24
Finished Feb 25 02:24:51 PM PST 24
Peak memory 200812 kb
Host smart-ebb20822-1e52-42b5-b7c9-488616f0d7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889681575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3889681575
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2139697555
Short name T536
Test name
Test status
Simulation time 179608014 ps
CPU time 1.14 seconds
Started Feb 25 02:24:55 PM PST 24
Finished Feb 25 02:24:56 PM PST 24
Peak memory 200544 kb
Host smart-1aefc492-34e3-4e53-b657-da03033e544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139697555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2139697555
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1359102187
Short name T384
Test name
Test status
Simulation time 121650249 ps
CPU time 1.23 seconds
Started Feb 25 02:24:41 PM PST 24
Finished Feb 25 02:24:42 PM PST 24
Peak memory 200728 kb
Host smart-15f7caa8-9422-4994-8592-8cfa9159ead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359102187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1359102187
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.752439217
Short name T271
Test name
Test status
Simulation time 5962943598 ps
CPU time 29.15 seconds
Started Feb 25 02:24:51 PM PST 24
Finished Feb 25 02:25:20 PM PST 24
Peak memory 200872 kb
Host smart-824a5988-d011-47fc-ae66-e2e1cf06ba3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752439217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.752439217
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1217389610
Short name T329
Test name
Test status
Simulation time 382120833 ps
CPU time 2.52 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:24:56 PM PST 24
Peak memory 200544 kb
Host smart-c3105122-03a0-4c03-a021-9fd8ad11e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217389610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1217389610
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.4083490605
Short name T258
Test name
Test status
Simulation time 81488782 ps
CPU time 0.75 seconds
Started Feb 25 02:24:38 PM PST 24
Finished Feb 25 02:24:39 PM PST 24
Peak memory 200500 kb
Host smart-0b86755a-347f-42fd-93c8-b6fd98f8c72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083490605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.4083490605
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1684806912
Short name T35
Test name
Test status
Simulation time 77079407 ps
CPU time 0.79 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:24:55 PM PST 24
Peak memory 200480 kb
Host smart-43e678dd-204e-4b61-b831-c89188292b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684806912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1684806912
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2534211439
Short name T32
Test name
Test status
Simulation time 1227633821 ps
CPU time 5.87 seconds
Started Feb 25 02:24:52 PM PST 24
Finished Feb 25 02:24:58 PM PST 24
Peak memory 218108 kb
Host smart-ad7b6f2a-3c82-40f1-8e91-15b306567eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534211439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2534211439
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2649810061
Short name T210
Test name
Test status
Simulation time 244369120 ps
CPU time 1.03 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:24:55 PM PST 24
Peak memory 217896 kb
Host smart-cc6487c9-cfee-48dd-b0ed-9a19130433a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649810061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2649810061
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.44517587
Short name T163
Test name
Test status
Simulation time 133902441 ps
CPU time 0.75 seconds
Started Feb 25 02:24:51 PM PST 24
Finished Feb 25 02:24:52 PM PST 24
Peak memory 200392 kb
Host smart-dcccaca8-7a73-4237-a213-290cbcdff733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44517587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.44517587
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3464900217
Short name T245
Test name
Test status
Simulation time 1249628422 ps
CPU time 5.83 seconds
Started Feb 25 02:24:56 PM PST 24
Finished Feb 25 02:25:01 PM PST 24
Peak memory 200808 kb
Host smart-1c3b3054-1a70-49e6-af28-4dde33c95171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464900217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3464900217
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1788602580
Short name T466
Test name
Test status
Simulation time 97285344 ps
CPU time 0.98 seconds
Started Feb 25 02:24:51 PM PST 24
Finished Feb 25 02:24:52 PM PST 24
Peak memory 200500 kb
Host smart-0ede7819-6e47-49a3-8a00-11a84edc0d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788602580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1788602580
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.817669499
Short name T526
Test name
Test status
Simulation time 235825627 ps
CPU time 1.46 seconds
Started Feb 25 02:24:52 PM PST 24
Finished Feb 25 02:24:54 PM PST 24
Peak memory 200796 kb
Host smart-f5ef9f2d-63c4-40aa-8836-bb02a403d781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817669499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.817669499
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2550642458
Short name T111
Test name
Test status
Simulation time 7001970765 ps
CPU time 36.06 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:25:30 PM PST 24
Peak memory 200892 kb
Host smart-4dbd9a20-fecc-4dc4-b52c-01ef1110c581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550642458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2550642458
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3672820995
Short name T164
Test name
Test status
Simulation time 301900797 ps
CPU time 2.05 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:24:56 PM PST 24
Peak memory 200552 kb
Host smart-526006f2-6acf-4843-a275-e7242acaffda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672820995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3672820995
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.644755913
Short name T397
Test name
Test status
Simulation time 217857174 ps
CPU time 1.34 seconds
Started Feb 25 02:24:52 PM PST 24
Finished Feb 25 02:24:54 PM PST 24
Peak memory 200516 kb
Host smart-7c4468ea-35b7-4dbe-a759-edb6b35579d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644755913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.644755913
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2441034337
Short name T421
Test name
Test status
Simulation time 71119036 ps
CPU time 0.76 seconds
Started Feb 25 02:24:58 PM PST 24
Finished Feb 25 02:24:59 PM PST 24
Peak memory 200476 kb
Host smart-e1b21c7c-f0f0-448f-aa9d-9d89900b6e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441034337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2441034337
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2937627851
Short name T243
Test name
Test status
Simulation time 2342377450 ps
CPU time 8.85 seconds
Started Feb 25 02:24:56 PM PST 24
Finished Feb 25 02:25:06 PM PST 24
Peak memory 222472 kb
Host smart-102c5d3a-995e-4d6f-8a88-ca1bc4a1b2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937627851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2937627851
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.370423982
Short name T366
Test name
Test status
Simulation time 244403016 ps
CPU time 1.03 seconds
Started Feb 25 02:25:00 PM PST 24
Finished Feb 25 02:25:01 PM PST 24
Peak memory 217972 kb
Host smart-6d0d2adc-a2c1-4a96-b075-1856dd04c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370423982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.370423982
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.896843500
Short name T15
Test name
Test status
Simulation time 177822984 ps
CPU time 0.83 seconds
Started Feb 25 02:24:55 PM PST 24
Finished Feb 25 02:24:56 PM PST 24
Peak memory 200344 kb
Host smart-0de4a64d-83d4-4ad8-8434-6062e026adc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896843500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.896843500
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.460635025
Short name T130
Test name
Test status
Simulation time 2142886686 ps
CPU time 8.41 seconds
Started Feb 25 02:24:56 PM PST 24
Finished Feb 25 02:25:05 PM PST 24
Peak memory 200752 kb
Host smart-d85a4cd7-1ab2-489c-ad5f-6409fa1d8e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460635025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.460635025
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2021518206
Short name T65
Test name
Test status
Simulation time 168744940 ps
CPU time 1.26 seconds
Started Feb 25 02:25:00 PM PST 24
Finished Feb 25 02:25:02 PM PST 24
Peak memory 200488 kb
Host smart-7cf69482-8b4b-456b-aca7-0b4ff95ea1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021518206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2021518206
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.374073771
Short name T81
Test name
Test status
Simulation time 235780827 ps
CPU time 1.42 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:24:56 PM PST 24
Peak memory 200716 kb
Host smart-526205f8-22a3-4753-b41c-3b2f6a683c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374073771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.374073771
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1725151141
Short name T395
Test name
Test status
Simulation time 7275679472 ps
CPU time 31.66 seconds
Started Feb 25 02:24:53 PM PST 24
Finished Feb 25 02:25:25 PM PST 24
Peak memory 200780 kb
Host smart-daecb0c9-4002-4347-be7b-22900054642d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725151141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1725151141
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3679067797
Short name T76
Test name
Test status
Simulation time 110855743 ps
CPU time 1.38 seconds
Started Feb 25 02:24:52 PM PST 24
Finished Feb 25 02:24:54 PM PST 24
Peak memory 200568 kb
Host smart-6906439b-ab4c-406a-82f7-f48eab1a8692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679067797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3679067797
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3785474994
Short name T166
Test name
Test status
Simulation time 159950817 ps
CPU time 1.31 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:24:55 PM PST 24
Peak memory 200668 kb
Host smart-94c86120-abdc-43b6-ac33-9d258a86593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785474994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3785474994
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.4071023015
Short name T392
Test name
Test status
Simulation time 67620425 ps
CPU time 0.82 seconds
Started Feb 25 02:25:03 PM PST 24
Finished Feb 25 02:25:04 PM PST 24
Peak memory 200480 kb
Host smart-ffaaa7f2-393d-4b41-a5e5-3462eb6aab18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071023015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.4071023015
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1761500287
Short name T500
Test name
Test status
Simulation time 1882048702 ps
CPU time 7.48 seconds
Started Feb 25 02:24:53 PM PST 24
Finished Feb 25 02:25:01 PM PST 24
Peak memory 218544 kb
Host smart-b97f32ad-976a-4587-86a4-c6a2bd1a659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761500287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1761500287
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3325690748
Short name T426
Test name
Test status
Simulation time 243951025 ps
CPU time 1.03 seconds
Started Feb 25 02:24:53 PM PST 24
Finished Feb 25 02:24:55 PM PST 24
Peak memory 217956 kb
Host smart-84012f54-f599-4838-82be-24183dcc78e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325690748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3325690748
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.280529894
Short name T534
Test name
Test status
Simulation time 78411129 ps
CPU time 0.76 seconds
Started Feb 25 02:24:56 PM PST 24
Finished Feb 25 02:24:57 PM PST 24
Peak memory 200328 kb
Host smart-8426a6a4-9e53-48b4-ae5f-8216e8f662ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280529894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.280529894
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2724619376
Short name T129
Test name
Test status
Simulation time 1412658880 ps
CPU time 5.37 seconds
Started Feb 25 02:25:00 PM PST 24
Finished Feb 25 02:25:05 PM PST 24
Peak memory 200820 kb
Host smart-3355b5f1-cf66-4361-93d0-b141031bce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724619376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2724619376
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3820202407
Short name T505
Test name
Test status
Simulation time 147245145 ps
CPU time 1.09 seconds
Started Feb 25 02:24:53 PM PST 24
Finished Feb 25 02:24:54 PM PST 24
Peak memory 200504 kb
Host smart-c8d34a19-b913-4af8-a91a-add8729097a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820202407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3820202407
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4008593678
Short name T476
Test name
Test status
Simulation time 200782288 ps
CPU time 1.32 seconds
Started Feb 25 02:24:52 PM PST 24
Finished Feb 25 02:24:54 PM PST 24
Peak memory 200744 kb
Host smart-80f8a886-75aa-4160-baed-f4dbbbcae3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008593678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4008593678
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3501157534
Short name T302
Test name
Test status
Simulation time 5241191130 ps
CPU time 24.51 seconds
Started Feb 25 02:24:54 PM PST 24
Finished Feb 25 02:25:18 PM PST 24
Peak memory 200904 kb
Host smart-4a625906-40eb-4571-b84d-575f2abae831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501157534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3501157534
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1798295419
Short name T240
Test name
Test status
Simulation time 128901362 ps
CPU time 1.75 seconds
Started Feb 25 02:24:57 PM PST 24
Finished Feb 25 02:24:59 PM PST 24
Peak memory 200556 kb
Host smart-77df77be-1360-46f4-a785-03ac778b0059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798295419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1798295419
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.915274778
Short name T541
Test name
Test status
Simulation time 217157989 ps
CPU time 1.31 seconds
Started Feb 25 02:24:53 PM PST 24
Finished Feb 25 02:24:55 PM PST 24
Peak memory 200516 kb
Host smart-309e50dc-86d5-4eac-9894-42975cf01ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915274778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.915274778
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.366641098
Short name T190
Test name
Test status
Simulation time 79998132 ps
CPU time 0.77 seconds
Started Feb 25 02:25:06 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 200384 kb
Host smart-9a43a69d-5f0d-4325-ac29-f2df30a1279b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366641098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.366641098
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1192785549
Short name T49
Test name
Test status
Simulation time 2359666003 ps
CPU time 8.55 seconds
Started Feb 25 02:24:59 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 218616 kb
Host smart-ed689acd-7bdb-4c18-82a8-4e8fdf566e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192785549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1192785549
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1316519396
Short name T448
Test name
Test status
Simulation time 244069741 ps
CPU time 1.1 seconds
Started Feb 25 02:25:04 PM PST 24
Finished Feb 25 02:25:06 PM PST 24
Peak memory 217860 kb
Host smart-9c2c7cfe-8ac3-4217-9bcf-cd564973130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316519396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1316519396
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3618283622
Short name T195
Test name
Test status
Simulation time 192073066 ps
CPU time 0.95 seconds
Started Feb 25 02:25:03 PM PST 24
Finished Feb 25 02:25:05 PM PST 24
Peak memory 200404 kb
Host smart-57ea6b0a-bd2f-44ef-9abf-b6499706c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618283622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3618283622
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1705325332
Short name T95
Test name
Test status
Simulation time 792153093 ps
CPU time 4.03 seconds
Started Feb 25 02:25:06 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200828 kb
Host smart-f27c4283-40e5-4f4b-a6e6-e1d34c091804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705325332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1705325332
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3148871962
Short name T194
Test name
Test status
Simulation time 186985861 ps
CPU time 1.31 seconds
Started Feb 25 02:25:00 PM PST 24
Finished Feb 25 02:25:02 PM PST 24
Peak memory 200508 kb
Host smart-d98140a3-f7c5-4e0d-922f-7c327837ab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148871962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3148871962
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.199699272
Short name T269
Test name
Test status
Simulation time 206027130 ps
CPU time 1.52 seconds
Started Feb 25 02:25:05 PM PST 24
Finished Feb 25 02:25:07 PM PST 24
Peak memory 200700 kb
Host smart-216bc0ce-acfe-4064-baa4-460e2670d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199699272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.199699272
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1505744425
Short name T131
Test name
Test status
Simulation time 2721843174 ps
CPU time 10.05 seconds
Started Feb 25 02:25:00 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200924 kb
Host smart-3e568f3a-fea9-4ef0-93bf-7a719d6aea52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505744425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1505744425
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3118435617
Short name T66
Test name
Test status
Simulation time 144448748 ps
CPU time 1.92 seconds
Started Feb 25 02:25:00 PM PST 24
Finished Feb 25 02:25:02 PM PST 24
Peak memory 200616 kb
Host smart-7ef0ff49-403c-4afd-a27a-97b476f11c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118435617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3118435617
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2600536089
Short name T175
Test name
Test status
Simulation time 80652412 ps
CPU time 0.79 seconds
Started Feb 25 02:24:59 PM PST 24
Finished Feb 25 02:25:00 PM PST 24
Peak memory 200504 kb
Host smart-032333cc-dfcc-45d9-8a4d-a7db28f1227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600536089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2600536089
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3053852286
Short name T356
Test name
Test status
Simulation time 77829592 ps
CPU time 0.8 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200476 kb
Host smart-2259062f-4580-447e-ba03-82922b377421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053852286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3053852286
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3994910884
Short name T24
Test name
Test status
Simulation time 1224037987 ps
CPU time 5.72 seconds
Started Feb 25 02:24:59 PM PST 24
Finished Feb 25 02:25:05 PM PST 24
Peak memory 222560 kb
Host smart-fc56f258-d430-461a-a7f3-e3ed1aec752b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994910884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3994910884
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3320448823
Short name T71
Test name
Test status
Simulation time 244245435 ps
CPU time 1.01 seconds
Started Feb 25 02:25:08 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 217984 kb
Host smart-6bcf0077-f91a-43d8-8f37-aa05567fd75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320448823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3320448823
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2534526526
Short name T20
Test name
Test status
Simulation time 141318614 ps
CPU time 0.77 seconds
Started Feb 25 02:25:00 PM PST 24
Finished Feb 25 02:25:01 PM PST 24
Peak memory 200372 kb
Host smart-8c842b8e-c8ac-4d70-a73d-020872ae815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534526526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2534526526
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.152272562
Short name T368
Test name
Test status
Simulation time 1393717863 ps
CPU time 5.54 seconds
Started Feb 25 02:25:06 PM PST 24
Finished Feb 25 02:25:12 PM PST 24
Peak memory 200684 kb
Host smart-3b6e7217-528c-444e-b1e5-a17ff9ae6341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152272562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.152272562
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.624760890
Short name T300
Test name
Test status
Simulation time 176150754 ps
CPU time 1.15 seconds
Started Feb 25 02:25:05 PM PST 24
Finished Feb 25 02:25:06 PM PST 24
Peak memory 200492 kb
Host smart-e0d755fb-1c0e-48e0-8104-61f95beadf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624760890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.624760890
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.978901519
Short name T399
Test name
Test status
Simulation time 233540721 ps
CPU time 1.52 seconds
Started Feb 25 02:25:06 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 200684 kb
Host smart-307e170f-78cb-4392-802b-f68c7277a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978901519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.978901519
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.909173950
Short name T482
Test name
Test status
Simulation time 6436864990 ps
CPU time 29.67 seconds
Started Feb 25 02:25:08 PM PST 24
Finished Feb 25 02:25:39 PM PST 24
Peak memory 200864 kb
Host smart-741937f7-e11c-40de-9b20-18d801663fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909173950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.909173950
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.851827748
Short name T303
Test name
Test status
Simulation time 472286402 ps
CPU time 2.56 seconds
Started Feb 25 02:25:06 PM PST 24
Finished Feb 25 02:25:09 PM PST 24
Peak memory 200636 kb
Host smart-fadd3737-ceaa-4c9a-8db3-1687f86a2b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851827748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.851827748
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3279030599
Short name T298
Test name
Test status
Simulation time 157115246 ps
CPU time 1.16 seconds
Started Feb 25 02:25:06 PM PST 24
Finished Feb 25 02:25:07 PM PST 24
Peak memory 200500 kb
Host smart-5021b8b9-66cd-4d33-97cb-03f3ebc7edae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279030599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3279030599
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.526507772
Short name T346
Test name
Test status
Simulation time 83864739 ps
CPU time 0.79 seconds
Started Feb 25 02:25:08 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200488 kb
Host smart-ea4e53da-bde4-4ca3-977a-31e1f9b527bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526507772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.526507772
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.4018260067
Short name T285
Test name
Test status
Simulation time 1222754156 ps
CPU time 6.42 seconds
Started Feb 25 02:25:06 PM PST 24
Finished Feb 25 02:25:13 PM PST 24
Peak memory 217476 kb
Host smart-ae1cea57-6b1b-4b66-b9d2-14f015a2cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018260067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.4018260067
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3762359569
Short name T225
Test name
Test status
Simulation time 243860743 ps
CPU time 1.11 seconds
Started Feb 25 02:25:03 PM PST 24
Finished Feb 25 02:25:04 PM PST 24
Peak memory 217976 kb
Host smart-6f6c5a50-d6fc-4547-afaa-9d5dc0169e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762359569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3762359569
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3311850812
Short name T14
Test name
Test status
Simulation time 252238051 ps
CPU time 0.95 seconds
Started Feb 25 02:25:03 PM PST 24
Finished Feb 25 02:25:05 PM PST 24
Peak memory 200380 kb
Host smart-aabfb89f-f739-4fc4-bd08-4d46bab04a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311850812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3311850812
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2267758865
Short name T519
Test name
Test status
Simulation time 2052793086 ps
CPU time 8.1 seconds
Started Feb 25 02:25:00 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 200788 kb
Host smart-5d9140f6-370e-47f7-8359-5c8a5183e9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267758865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2267758865
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1547065310
Short name T492
Test name
Test status
Simulation time 103367325 ps
CPU time 1.01 seconds
Started Feb 25 02:24:59 PM PST 24
Finished Feb 25 02:25:00 PM PST 24
Peak memory 200508 kb
Host smart-ba13645e-4c21-4f05-919d-bcd0ec4750e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547065310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1547065310
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2081585234
Short name T301
Test name
Test status
Simulation time 196402563 ps
CPU time 1.36 seconds
Started Feb 25 02:25:06 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 200760 kb
Host smart-26156bb0-3691-4195-b577-9e9fbe98bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081585234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2081585234
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1794476260
Short name T97
Test name
Test status
Simulation time 5563207009 ps
CPU time 18.35 seconds
Started Feb 25 02:25:05 PM PST 24
Finished Feb 25 02:25:23 PM PST 24
Peak memory 200896 kb
Host smart-01afd7ba-21c1-44fb-8c06-fb93078b5e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794476260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1794476260
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1959205176
Short name T506
Test name
Test status
Simulation time 345323214 ps
CPU time 2.29 seconds
Started Feb 25 02:25:05 PM PST 24
Finished Feb 25 02:25:07 PM PST 24
Peak memory 200556 kb
Host smart-8ff64e83-cabc-4043-9dad-5caa4f77c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959205176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1959205176
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2153362412
Short name T357
Test name
Test status
Simulation time 59619890 ps
CPU time 0.73 seconds
Started Feb 25 02:25:07 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 200472 kb
Host smart-9b558848-a8c5-49e9-81b1-e98644cd0afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153362412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2153362412
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2500897410
Short name T33
Test name
Test status
Simulation time 1220083257 ps
CPU time 5.69 seconds
Started Feb 25 02:25:07 PM PST 24
Finished Feb 25 02:25:13 PM PST 24
Peak memory 222036 kb
Host smart-6f677d81-0361-41e0-b37d-b22c9e8f2d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500897410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2500897410
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3282464400
Short name T272
Test name
Test status
Simulation time 244113235 ps
CPU time 1.14 seconds
Started Feb 25 02:25:08 PM PST 24
Finished Feb 25 02:25:09 PM PST 24
Peak memory 217956 kb
Host smart-e6a78631-200f-4052-99bd-53976145ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282464400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3282464400
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1503296621
Short name T17
Test name
Test status
Simulation time 99862176 ps
CPU time 0.84 seconds
Started Feb 25 02:25:15 PM PST 24
Finished Feb 25 02:25:17 PM PST 24
Peak memory 200368 kb
Host smart-d677086b-0ba3-4ca1-82f0-97ce8482a010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503296621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1503296621
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4008659194
Short name T270
Test name
Test status
Simulation time 1221292884 ps
CPU time 5.46 seconds
Started Feb 25 02:25:11 PM PST 24
Finished Feb 25 02:25:17 PM PST 24
Peak memory 200764 kb
Host smart-cb9c511f-febc-456d-98b6-66ac26d481d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008659194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4008659194
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3524737480
Short name T322
Test name
Test status
Simulation time 102196507 ps
CPU time 0.94 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:11 PM PST 24
Peak memory 200508 kb
Host smart-ad52a62a-b331-4cc3-a258-b02305c7ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524737480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3524737480
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.4185116524
Short name T531
Test name
Test status
Simulation time 194162912 ps
CPU time 1.41 seconds
Started Feb 25 02:25:11 PM PST 24
Finished Feb 25 02:25:13 PM PST 24
Peak memory 200756 kb
Host smart-a34bf53f-cb53-4cd9-8216-e9622b179c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185116524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.4185116524
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.4119044087
Short name T388
Test name
Test status
Simulation time 218523508 ps
CPU time 1.6 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:12 PM PST 24
Peak memory 200700 kb
Host smart-4605eb0b-3764-447c-b6bb-dc54e1cc7359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119044087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4119044087
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.783797509
Short name T220
Test name
Test status
Simulation time 542037918 ps
CPU time 2.93 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:12 PM PST 24
Peak memory 200608 kb
Host smart-d2e9bc38-ab6d-4c38-89c9-323e3f1e7d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783797509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.783797509
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.960588817
Short name T264
Test name
Test status
Simulation time 74772005 ps
CPU time 0.8 seconds
Started Feb 25 02:25:07 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 200524 kb
Host smart-d7f7f958-3c64-473e-bc5e-78c2ab1b806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960588817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.960588817
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1332864656
Short name T2
Test name
Test status
Simulation time 84195991 ps
CPU time 0.77 seconds
Started Feb 25 02:25:08 PM PST 24
Finished Feb 25 02:25:09 PM PST 24
Peak memory 200476 kb
Host smart-10b92f24-d15b-44e6-a7ca-fd2787518393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332864656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1332864656
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3838430441
Short name T287
Test name
Test status
Simulation time 1222657849 ps
CPU time 5.76 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:15 PM PST 24
Peak memory 218564 kb
Host smart-6d1f9ac1-5c68-4a46-9b38-6079a5384fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838430441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3838430441
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1951753673
Short name T319
Test name
Test status
Simulation time 244773798 ps
CPU time 1.06 seconds
Started Feb 25 02:25:11 PM PST 24
Finished Feb 25 02:25:12 PM PST 24
Peak memory 217964 kb
Host smart-5e1a10d8-39d3-4918-b4c8-fda79b971417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951753673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1951753673
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3283839218
Short name T202
Test name
Test status
Simulation time 191783076 ps
CPU time 0.9 seconds
Started Feb 25 02:25:15 PM PST 24
Finished Feb 25 02:25:17 PM PST 24
Peak memory 200368 kb
Host smart-9877635d-3804-4bf5-aa06-a59c68d537b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283839218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3283839218
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.511979601
Short name T261
Test name
Test status
Simulation time 1364092385 ps
CPU time 5.43 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:15 PM PST 24
Peak memory 200756 kb
Host smart-2eb83e40-4caf-4158-987a-56d71d6a8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511979601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.511979601
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2426556680
Short name T463
Test name
Test status
Simulation time 112412463 ps
CPU time 1.03 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200464 kb
Host smart-f5782eca-5e60-4958-a64b-78790a13d129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426556680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2426556680
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3780125600
Short name T381
Test name
Test status
Simulation time 200989201 ps
CPU time 1.34 seconds
Started Feb 25 02:25:07 PM PST 24
Finished Feb 25 02:25:08 PM PST 24
Peak memory 200828 kb
Host smart-c49e375c-7987-40d8-a57f-fb6cd5d502bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780125600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3780125600
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.848504506
Short name T430
Test name
Test status
Simulation time 7127707940 ps
CPU time 26.88 seconds
Started Feb 25 02:25:14 PM PST 24
Finished Feb 25 02:25:41 PM PST 24
Peak memory 200884 kb
Host smart-18a9e957-2508-4f8a-8839-97268830e232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848504506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.848504506
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.904935524
Short name T435
Test name
Test status
Simulation time 317066549 ps
CPU time 2.1 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:11 PM PST 24
Peak memory 200616 kb
Host smart-7dbcd632-76d7-48d8-98ab-4ae4a4d7c039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904935524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.904935524
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3189510498
Short name T12
Test name
Test status
Simulation time 83855302 ps
CPU time 0.81 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200536 kb
Host smart-6fa8e569-0542-4679-880d-273046ffc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189510498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3189510498
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3194645065
Short name T218
Test name
Test status
Simulation time 66619257 ps
CPU time 0.77 seconds
Started Feb 25 02:23:39 PM PST 24
Finished Feb 25 02:23:40 PM PST 24
Peak memory 200476 kb
Host smart-655b439f-8d3e-4f0f-aa0a-e221b2b5b418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194645065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3194645065
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1838335698
Short name T480
Test name
Test status
Simulation time 1229549805 ps
CPU time 5.39 seconds
Started Feb 25 02:23:32 PM PST 24
Finished Feb 25 02:23:38 PM PST 24
Peak memory 217380 kb
Host smart-265fc17e-599f-469c-9c43-4120035169e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838335698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1838335698
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.4184680987
Short name T444
Test name
Test status
Simulation time 244032483 ps
CPU time 1.14 seconds
Started Feb 25 02:23:32 PM PST 24
Finished Feb 25 02:23:33 PM PST 24
Peak memory 217952 kb
Host smart-d6783a48-b0c9-44de-93e6-452278da996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184680987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.4184680987
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2738916298
Short name T473
Test name
Test status
Simulation time 88494975 ps
CPU time 0.71 seconds
Started Feb 25 02:23:38 PM PST 24
Finished Feb 25 02:23:39 PM PST 24
Peak memory 200364 kb
Host smart-f800693a-7ac9-42d1-85ac-97651f4c72d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738916298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2738916298
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3968869915
Short name T108
Test name
Test status
Simulation time 1381289449 ps
CPU time 5.48 seconds
Started Feb 25 02:23:32 PM PST 24
Finished Feb 25 02:23:37 PM PST 24
Peak memory 200772 kb
Host smart-6f905afc-eaa3-4cc4-a826-8062cc8ede6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968869915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3968869915
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1867740720
Short name T64
Test name
Test status
Simulation time 16516788200 ps
CPU time 29.3 seconds
Started Feb 25 02:23:38 PM PST 24
Finished Feb 25 02:24:08 PM PST 24
Peak memory 218688 kb
Host smart-28665c93-8a7f-4075-ab04-b9524e6f512c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867740720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1867740720
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4213579444
Short name T469
Test name
Test status
Simulation time 156282214 ps
CPU time 1.15 seconds
Started Feb 25 02:23:38 PM PST 24
Finished Feb 25 02:23:40 PM PST 24
Peak memory 200492 kb
Host smart-ec3cb2c4-f01e-4259-b0b2-5d7249df0adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213579444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4213579444
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.262633719
Short name T347
Test name
Test status
Simulation time 201327062 ps
CPU time 1.3 seconds
Started Feb 25 02:23:33 PM PST 24
Finished Feb 25 02:23:34 PM PST 24
Peak memory 200716 kb
Host smart-32ef3978-36e4-4968-a11a-065e94288e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262633719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.262633719
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.277099100
Short name T398
Test name
Test status
Simulation time 136314026 ps
CPU time 1.07 seconds
Started Feb 25 02:23:36 PM PST 24
Finished Feb 25 02:23:38 PM PST 24
Peak memory 200512 kb
Host smart-6befa4a5-b7ca-4b19-b37c-bab614b76415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277099100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.277099100
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2578111195
Short name T102
Test name
Test status
Simulation time 350902159 ps
CPU time 2.28 seconds
Started Feb 25 02:23:33 PM PST 24
Finished Feb 25 02:23:36 PM PST 24
Peak memory 200516 kb
Host smart-d97972ab-7093-4ec2-b640-e8670b6c3579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578111195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2578111195
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1610354865
Short name T400
Test name
Test status
Simulation time 166022952 ps
CPU time 1.13 seconds
Started Feb 25 02:23:38 PM PST 24
Finished Feb 25 02:23:40 PM PST 24
Peak memory 200496 kb
Host smart-00dfc3ba-fc74-4b75-a55a-2d577be06401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610354865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1610354865
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.974603807
Short name T320
Test name
Test status
Simulation time 68521655 ps
CPU time 0.73 seconds
Started Feb 25 02:25:14 PM PST 24
Finished Feb 25 02:25:15 PM PST 24
Peak memory 200496 kb
Host smart-607c94eb-854e-4489-82c8-b1c9c3f57b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974603807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.974603807
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1892366206
Short name T27
Test name
Test status
Simulation time 1881970746 ps
CPU time 6.92 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:17 PM PST 24
Peak memory 217348 kb
Host smart-dcf0bac2-669f-41f3-86ce-f70e9ffd05aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892366206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1892366206
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3914788932
Short name T332
Test name
Test status
Simulation time 245365449 ps
CPU time 1.07 seconds
Started Feb 25 02:25:11 PM PST 24
Finished Feb 25 02:25:12 PM PST 24
Peak memory 217884 kb
Host smart-9bc7d26f-5046-4bfd-8026-7833a2419f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914788932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3914788932
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1324433537
Short name T481
Test name
Test status
Simulation time 192118581 ps
CPU time 0.85 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:11 PM PST 24
Peak memory 200384 kb
Host smart-aa982307-3ed6-4150-bc20-93dc98300245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324433537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1324433537
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1435208441
Short name T422
Test name
Test status
Simulation time 1526660635 ps
CPU time 6.15 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:16 PM PST 24
Peak memory 200760 kb
Host smart-8a69192a-06de-493b-9ebe-1f38d43432e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435208441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1435208441
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2637871985
Short name T238
Test name
Test status
Simulation time 104041134 ps
CPU time 0.95 seconds
Started Feb 25 02:25:07 PM PST 24
Finished Feb 25 02:25:09 PM PST 24
Peak memory 200520 kb
Host smart-8bdc402f-d545-4560-8b6d-a07b15523404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637871985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2637871985
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3964222912
Short name T458
Test name
Test status
Simulation time 226539741 ps
CPU time 1.61 seconds
Started Feb 25 02:25:11 PM PST 24
Finished Feb 25 02:25:12 PM PST 24
Peak memory 200712 kb
Host smart-cc3d9edd-6cde-4e4c-ad55-6931919d78ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964222912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3964222912
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1126614877
Short name T75
Test name
Test status
Simulation time 4775488128 ps
CPU time 17.98 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:28 PM PST 24
Peak memory 200840 kb
Host smart-3d34cd92-8f32-4be8-8aab-7fbb623e5265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126614877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1126614877
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4221696204
Short name T197
Test name
Test status
Simulation time 142454784 ps
CPU time 1.86 seconds
Started Feb 25 02:25:15 PM PST 24
Finished Feb 25 02:25:17 PM PST 24
Peak memory 200540 kb
Host smart-908638a8-095f-4902-a0e2-451b1c20c4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221696204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4221696204
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2422144346
Short name T235
Test name
Test status
Simulation time 137193449 ps
CPU time 1.05 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200456 kb
Host smart-3794cccf-87ec-4f09-a5a5-1575622ad514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422144346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2422144346
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3738022743
Short name T278
Test name
Test status
Simulation time 67479698 ps
CPU time 0.74 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:11 PM PST 24
Peak memory 200472 kb
Host smart-e250dc43-1ddd-4efd-9b52-e018d761b6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738022743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3738022743
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.633849171
Short name T48
Test name
Test status
Simulation time 2349343739 ps
CPU time 8.71 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:18 PM PST 24
Peak memory 217824 kb
Host smart-e973c2f0-296b-44ee-b943-ced12086a904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633849171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.633849171
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2410029134
Short name T203
Test name
Test status
Simulation time 244992399 ps
CPU time 1.06 seconds
Started Feb 25 02:25:09 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 217880 kb
Host smart-c3726557-e70e-4731-a382-1c3e8ee8484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410029134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2410029134
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.387656992
Short name T425
Test name
Test status
Simulation time 154318737 ps
CPU time 0.87 seconds
Started Feb 25 02:25:16 PM PST 24
Finished Feb 25 02:25:17 PM PST 24
Peak memory 200368 kb
Host smart-10ca88aa-995b-47c6-87e8-bda3211398c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387656992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.387656992
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.4222415466
Short name T229
Test name
Test status
Simulation time 867626228 ps
CPU time 4.37 seconds
Started Feb 25 02:25:11 PM PST 24
Finished Feb 25 02:25:16 PM PST 24
Peak memory 200820 kb
Host smart-1ca5dbc4-266e-4159-ac2d-132c9cbb846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222415466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4222415466
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4124047056
Short name T369
Test name
Test status
Simulation time 158035905 ps
CPU time 1.16 seconds
Started Feb 25 02:25:15 PM PST 24
Finished Feb 25 02:25:17 PM PST 24
Peak memory 200504 kb
Host smart-3a5352b1-baa3-4411-85dc-b0de8d703713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124047056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4124047056
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2990285307
Short name T161
Test name
Test status
Simulation time 107909395 ps
CPU time 1.2 seconds
Started Feb 25 02:25:12 PM PST 24
Finished Feb 25 02:25:14 PM PST 24
Peak memory 200756 kb
Host smart-3b63b4a6-5e8f-4133-a471-fe5bb5e60286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990285307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2990285307
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3218178619
Short name T354
Test name
Test status
Simulation time 11128620697 ps
CPU time 47.5 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:58 PM PST 24
Peak memory 200884 kb
Host smart-01923b04-4d1d-4ef3-80d2-28e6b51af556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218178619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3218178619
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2465731623
Short name T528
Test name
Test status
Simulation time 137323924 ps
CPU time 1.7 seconds
Started Feb 25 02:25:11 PM PST 24
Finished Feb 25 02:25:12 PM PST 24
Peak memory 200588 kb
Host smart-fe86b349-0f89-4427-9b0f-07a83476807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465731623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2465731623
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2407721922
Short name T323
Test name
Test status
Simulation time 119113221 ps
CPU time 1.03 seconds
Started Feb 25 02:25:08 PM PST 24
Finished Feb 25 02:25:10 PM PST 24
Peak memory 200504 kb
Host smart-169b0199-a51e-4415-a137-5b6f1b200215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407721922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2407721922
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1097397785
Short name T201
Test name
Test status
Simulation time 69330610 ps
CPU time 0.77 seconds
Started Feb 25 02:25:31 PM PST 24
Finished Feb 25 02:25:32 PM PST 24
Peak memory 200488 kb
Host smart-f35c2cb6-4932-495d-b15e-eba3e4ca4a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097397785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1097397785
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3206617326
Short name T26
Test name
Test status
Simulation time 2366431778 ps
CPU time 8.33 seconds
Started Feb 25 02:25:15 PM PST 24
Finished Feb 25 02:25:23 PM PST 24
Peak memory 217840 kb
Host smart-cf6be9de-6293-4ba0-8096-11f753b9eb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206617326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3206617326
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1713721116
Short name T279
Test name
Test status
Simulation time 244120089 ps
CPU time 1.08 seconds
Started Feb 25 02:25:14 PM PST 24
Finished Feb 25 02:25:15 PM PST 24
Peak memory 217968 kb
Host smart-7d93809f-e14f-4c2a-8e03-631db8beb8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713721116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1713721116
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1017685360
Short name T16
Test name
Test status
Simulation time 113118745 ps
CPU time 0.82 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:11 PM PST 24
Peak memory 200380 kb
Host smart-b7518f17-556d-4be7-88b0-32cd7d259370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017685360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1017685360
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1922387736
Short name T308
Test name
Test status
Simulation time 905001902 ps
CPU time 4.72 seconds
Started Feb 25 02:25:15 PM PST 24
Finished Feb 25 02:25:20 PM PST 24
Peak memory 200748 kb
Host smart-8244ae08-ccd0-472e-a240-3655976b3912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922387736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1922387736
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.995439733
Short name T206
Test name
Test status
Simulation time 147202120 ps
CPU time 1.12 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:12 PM PST 24
Peak memory 200508 kb
Host smart-1f48c626-cb1f-4b17-b3ae-cfb44302f7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995439733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.995439733
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2168805171
Short name T479
Test name
Test status
Simulation time 108989166 ps
CPU time 1.17 seconds
Started Feb 25 02:25:14 PM PST 24
Finished Feb 25 02:25:15 PM PST 24
Peak memory 200756 kb
Host smart-27e7882a-9bd5-4234-93a6-e7613c641964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168805171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2168805171
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2877053436
Short name T345
Test name
Test status
Simulation time 301042925 ps
CPU time 2.27 seconds
Started Feb 25 02:25:15 PM PST 24
Finished Feb 25 02:25:17 PM PST 24
Peak memory 200588 kb
Host smart-53754754-e804-4d8f-a03d-8cf049b65331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877053436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2877053436
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.4070356703
Short name T101
Test name
Test status
Simulation time 76952842 ps
CPU time 0.8 seconds
Started Feb 25 02:25:10 PM PST 24
Finished Feb 25 02:25:11 PM PST 24
Peak memory 200508 kb
Host smart-e0e69ff4-54b5-4ee0-b150-9c28469c493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070356703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.4070356703
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3465096610
Short name T394
Test name
Test status
Simulation time 113567358 ps
CPU time 0.85 seconds
Started Feb 25 02:25:27 PM PST 24
Finished Feb 25 02:25:28 PM PST 24
Peak memory 200476 kb
Host smart-6579b602-bb25-410c-81d2-4a10def273e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465096610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3465096610
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.270126110
Short name T341
Test name
Test status
Simulation time 243774609 ps
CPU time 1.05 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 217868 kb
Host smart-0d6aee2a-8a36-42d7-9e27-a8b167bd530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270126110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.270126110
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.624329311
Short name T19
Test name
Test status
Simulation time 209536063 ps
CPU time 0.94 seconds
Started Feb 25 02:25:32 PM PST 24
Finished Feb 25 02:25:33 PM PST 24
Peak memory 200372 kb
Host smart-2283e303-4368-4532-973f-a764ffc9aee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624329311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.624329311
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.12631489
Short name T484
Test name
Test status
Simulation time 1295133807 ps
CPU time 5.87 seconds
Started Feb 25 02:25:39 PM PST 24
Finished Feb 25 02:25:46 PM PST 24
Peak memory 200792 kb
Host smart-d2ae083a-4593-46db-9517-fe28142eb365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12631489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.12631489
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3178816411
Short name T160
Test name
Test status
Simulation time 154655440 ps
CPU time 1.1 seconds
Started Feb 25 02:25:28 PM PST 24
Finished Feb 25 02:25:29 PM PST 24
Peak memory 200504 kb
Host smart-14a3d4fc-6f02-4b72-8e6b-5fe95579615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178816411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3178816411
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.753775611
Short name T351
Test name
Test status
Simulation time 194195047 ps
CPU time 1.37 seconds
Started Feb 25 02:25:42 PM PST 24
Finished Feb 25 02:25:44 PM PST 24
Peak memory 200700 kb
Host smart-4f5880c6-b882-46d3-9c97-ffc2ffd3a887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753775611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.753775611
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3698861109
Short name T299
Test name
Test status
Simulation time 6740260137 ps
CPU time 28.65 seconds
Started Feb 25 02:25:24 PM PST 24
Finished Feb 25 02:25:53 PM PST 24
Peak memory 200864 kb
Host smart-9d7f75bb-a5f6-4be3-b324-54f9e31f9937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698861109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3698861109
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3833541867
Short name T231
Test name
Test status
Simulation time 335329278 ps
CPU time 2.46 seconds
Started Feb 25 02:25:30 PM PST 24
Finished Feb 25 02:25:33 PM PST 24
Peak memory 200568 kb
Host smart-23ae35ed-941b-4612-bb56-ddca8d810de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833541867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3833541867
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.891927495
Short name T106
Test name
Test status
Simulation time 82651662 ps
CPU time 0.86 seconds
Started Feb 25 02:25:40 PM PST 24
Finished Feb 25 02:25:41 PM PST 24
Peak memory 200500 kb
Host smart-846a467c-c03c-4910-94fe-c2cda3fc2481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891927495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.891927495
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3895848512
Short name T315
Test name
Test status
Simulation time 62746233 ps
CPU time 0.74 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:42 PM PST 24
Peak memory 200492 kb
Host smart-313cb086-0fe1-4059-8e5f-478ba680c333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895848512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3895848512
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3153087960
Short name T239
Test name
Test status
Simulation time 245040964 ps
CPU time 1.05 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:42 PM PST 24
Peak memory 217932 kb
Host smart-db21bb38-1216-46c4-b36d-64867d733cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153087960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3153087960
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3079402942
Short name T199
Test name
Test status
Simulation time 207163938 ps
CPU time 0.9 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200372 kb
Host smart-2cbbf92f-0ed7-4c49-9936-30765012a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079402942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3079402942
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.697111610
Short name T512
Test name
Test status
Simulation time 1777886143 ps
CPU time 7.97 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:51 PM PST 24
Peak memory 200764 kb
Host smart-33e2dad3-6132-45b1-924d-abad851229fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697111610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.697111610
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.28812202
Short name T143
Test name
Test status
Simulation time 101907162 ps
CPU time 1 seconds
Started Feb 25 02:25:30 PM PST 24
Finished Feb 25 02:25:31 PM PST 24
Peak memory 200512 kb
Host smart-0f77c9ea-ca46-483e-bad6-94c387d75fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28812202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.28812202
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2976717954
Short name T188
Test name
Test status
Simulation time 108028969 ps
CPU time 1.19 seconds
Started Feb 25 02:25:25 PM PST 24
Finished Feb 25 02:25:26 PM PST 24
Peak memory 200732 kb
Host smart-7756c1e3-567a-4523-abf9-91cfee4410c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976717954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2976717954
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.561202432
Short name T465
Test name
Test status
Simulation time 373700004 ps
CPU time 2.32 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:44 PM PST 24
Peak memory 200628 kb
Host smart-eafbc3ee-e299-4b61-8b2c-487cd99e1719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561202432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.561202432
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3967313485
Short name T77
Test name
Test status
Simulation time 122035759 ps
CPU time 1.18 seconds
Started Feb 25 02:25:25 PM PST 24
Finished Feb 25 02:25:26 PM PST 24
Peak memory 200532 kb
Host smart-e4550b00-4aef-4118-ac50-7fa900a4dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967313485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3967313485
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2743150738
Short name T363
Test name
Test status
Simulation time 78446146 ps
CPU time 0.75 seconds
Started Feb 25 02:25:32 PM PST 24
Finished Feb 25 02:25:33 PM PST 24
Peak memory 200460 kb
Host smart-07522664-ff45-4eb4-9098-168b91e91da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743150738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2743150738
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3506598952
Short name T31
Test name
Test status
Simulation time 2166088717 ps
CPU time 8.62 seconds
Started Feb 25 02:25:40 PM PST 24
Finished Feb 25 02:25:49 PM PST 24
Peak memory 218084 kb
Host smart-b982e20c-e7ca-4dbe-b133-23131dff77f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506598952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3506598952
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4105795987
Short name T478
Test name
Test status
Simulation time 244360024 ps
CPU time 1.03 seconds
Started Feb 25 02:25:40 PM PST 24
Finished Feb 25 02:25:42 PM PST 24
Peak memory 218000 kb
Host smart-7aeec7bb-666b-4bad-94bb-8bcd24f5da77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105795987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4105795987
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.632973388
Short name T337
Test name
Test status
Simulation time 99024982 ps
CPU time 0.82 seconds
Started Feb 25 02:25:40 PM PST 24
Finished Feb 25 02:25:41 PM PST 24
Peak memory 200384 kb
Host smart-cbfefe76-7909-4012-b21d-7e66c15c5cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632973388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.632973388
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.347131279
Short name T132
Test name
Test status
Simulation time 1645992618 ps
CPU time 6.52 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:48 PM PST 24
Peak memory 200684 kb
Host smart-bc3fc4d2-f2d9-4be5-b5ba-667978f8ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347131279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.347131279
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1154800117
Short name T174
Test name
Test status
Simulation time 111406155 ps
CPU time 1.06 seconds
Started Feb 25 02:25:25 PM PST 24
Finished Feb 25 02:25:26 PM PST 24
Peak memory 200524 kb
Host smart-6294e44a-7e32-4539-83e2-a5b54485887e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154800117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1154800117
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4026983347
Short name T316
Test name
Test status
Simulation time 206912086 ps
CPU time 1.35 seconds
Started Feb 25 02:25:26 PM PST 24
Finished Feb 25 02:25:28 PM PST 24
Peak memory 200796 kb
Host smart-07cd3c78-63b0-46a1-8fae-59164a7c9270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026983347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4026983347
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2422551643
Short name T133
Test name
Test status
Simulation time 160446884 ps
CPU time 1.14 seconds
Started Feb 25 02:25:40 PM PST 24
Finished Feb 25 02:25:41 PM PST 24
Peak memory 200500 kb
Host smart-4fdc08b9-83df-4032-856f-88ea1efdbbfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422551643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2422551643
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2198039545
Short name T362
Test name
Test status
Simulation time 124824960 ps
CPU time 1.6 seconds
Started Feb 25 02:25:26 PM PST 24
Finished Feb 25 02:25:28 PM PST 24
Peak memory 200564 kb
Host smart-4771abb4-493f-4a06-b981-776187daf11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198039545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2198039545
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3027697392
Short name T221
Test name
Test status
Simulation time 131817610 ps
CPU time 1.01 seconds
Started Feb 25 02:25:40 PM PST 24
Finished Feb 25 02:25:42 PM PST 24
Peak memory 200504 kb
Host smart-7775c717-ce11-4a76-94d9-6db7be9152b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027697392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3027697392
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2304042000
Short name T185
Test name
Test status
Simulation time 68530226 ps
CPU time 0.72 seconds
Started Feb 25 02:25:39 PM PST 24
Finished Feb 25 02:25:41 PM PST 24
Peak memory 200368 kb
Host smart-4b05f450-023d-4b51-81ca-c172e02d51c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304042000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2304042000
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3133756300
Short name T457
Test name
Test status
Simulation time 1208549355 ps
CPU time 6.03 seconds
Started Feb 25 02:25:40 PM PST 24
Finished Feb 25 02:25:46 PM PST 24
Peak memory 230324 kb
Host smart-01994346-30ce-4b98-b86e-8c862064cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133756300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3133756300
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3959700684
Short name T69
Test name
Test status
Simulation time 244457942 ps
CPU time 1.07 seconds
Started Feb 25 02:25:45 PM PST 24
Finished Feb 25 02:25:46 PM PST 24
Peak memory 217872 kb
Host smart-635092c3-5bf8-46a7-9d59-fa9fcd66cbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959700684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3959700684
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1194093798
Short name T475
Test name
Test status
Simulation time 96898014 ps
CPU time 0.75 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200360 kb
Host smart-f8097e5b-8b99-497c-8e7f-d3c94e69234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194093798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1194093798
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.184972545
Short name T438
Test name
Test status
Simulation time 1362757001 ps
CPU time 5.42 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:50 PM PST 24
Peak memory 200772 kb
Host smart-7079c612-f242-414d-9ec8-f5350f178338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184972545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.184972545
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3074677702
Short name T509
Test name
Test status
Simulation time 185237975 ps
CPU time 1.22 seconds
Started Feb 25 02:25:39 PM PST 24
Finished Feb 25 02:25:41 PM PST 24
Peak memory 200524 kb
Host smart-b1815608-2d8f-45b3-81df-3788bc2ff96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074677702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3074677702
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1569099774
Short name T511
Test name
Test status
Simulation time 258787540 ps
CPU time 1.64 seconds
Started Feb 25 02:25:32 PM PST 24
Finished Feb 25 02:25:34 PM PST 24
Peak memory 200684 kb
Host smart-0a473656-feb1-4cd5-bda4-fd59f7f5a56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569099774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1569099774
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3219261455
Short name T21
Test name
Test status
Simulation time 2316091132 ps
CPU time 10.82 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:25:57 PM PST 24
Peak memory 200868 kb
Host smart-7b1f5e98-f141-45c7-98aa-65aef294fb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219261455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3219261455
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3425840003
Short name T515
Test name
Test status
Simulation time 358708031 ps
CPU time 2.22 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:45 PM PST 24
Peak memory 200560 kb
Host smart-ecac1cc7-9386-40e5-900c-a51a3b700c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425840003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3425840003
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3081402700
Short name T148
Test name
Test status
Simulation time 112275430 ps
CPU time 1.04 seconds
Started Feb 25 02:25:42 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200648 kb
Host smart-494a6ab7-06c7-4fd1-b32c-e34dca2dddcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081402700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3081402700
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2137395935
Short name T187
Test name
Test status
Simulation time 83656680 ps
CPU time 0.84 seconds
Started Feb 25 02:25:42 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200460 kb
Host smart-a060c05e-d25e-4453-9165-d3b2c8b96952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137395935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2137395935
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1559115862
Short name T292
Test name
Test status
Simulation time 1899545476 ps
CPU time 7.42 seconds
Started Feb 25 02:25:34 PM PST 24
Finished Feb 25 02:25:42 PM PST 24
Peak memory 222600 kb
Host smart-abef6e15-624d-4c1e-846f-9f263be36adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559115862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1559115862
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3248643019
Short name T165
Test name
Test status
Simulation time 244250616 ps
CPU time 1.1 seconds
Started Feb 25 02:25:42 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 217996 kb
Host smart-5be06f11-31c0-4ea6-bd39-b0b680cb8612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248643019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3248643019
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.586276497
Short name T405
Test name
Test status
Simulation time 188320985 ps
CPU time 0.86 seconds
Started Feb 25 02:25:42 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200368 kb
Host smart-fbb6fd0c-9f5c-4704-8a79-8b50872d0974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586276497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.586276497
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1623719367
Short name T408
Test name
Test status
Simulation time 1973255805 ps
CPU time 7.31 seconds
Started Feb 25 02:25:31 PM PST 24
Finished Feb 25 02:25:39 PM PST 24
Peak memory 200788 kb
Host smart-9d92f5e1-fd37-4772-ae33-a0f467e8773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623719367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1623719367
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1113938817
Short name T168
Test name
Test status
Simulation time 173401547 ps
CPU time 1.18 seconds
Started Feb 25 02:25:34 PM PST 24
Finished Feb 25 02:25:35 PM PST 24
Peak memory 200508 kb
Host smart-d1663248-825f-48b6-bea6-32303a2dd82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113938817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1113938817
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.717691535
Short name T446
Test name
Test status
Simulation time 226941426 ps
CPU time 1.51 seconds
Started Feb 25 02:25:40 PM PST 24
Finished Feb 25 02:25:42 PM PST 24
Peak memory 200728 kb
Host smart-43eb4936-f745-4720-ae74-e74b4abd4d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717691535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.717691535
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2527395235
Short name T361
Test name
Test status
Simulation time 166496199 ps
CPU time 1.21 seconds
Started Feb 25 02:25:35 PM PST 24
Finished Feb 25 02:25:37 PM PST 24
Peak memory 200408 kb
Host smart-8030c84b-fb04-4c71-9571-f2dfaee1a82c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527395235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2527395235
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1028521709
Short name T489
Test name
Test status
Simulation time 127776335 ps
CPU time 1.64 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200548 kb
Host smart-60f9a023-83d4-4576-8bdd-714611fd7cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028521709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1028521709
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1639893297
Short name T222
Test name
Test status
Simulation time 140775898 ps
CPU time 1.07 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:48 PM PST 24
Peak memory 200536 kb
Host smart-3d29b825-c116-41c4-8d3d-af0853ba67c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639893297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1639893297
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2937344520
Short name T522
Test name
Test status
Simulation time 65615801 ps
CPU time 0.73 seconds
Started Feb 25 02:25:36 PM PST 24
Finished Feb 25 02:25:38 PM PST 24
Peak memory 200476 kb
Host smart-f0b7d0d8-7d97-482f-a0da-bb4f9490836f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937344520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2937344520
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2359995972
Short name T483
Test name
Test status
Simulation time 2368256393 ps
CPU time 9.11 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:53 PM PST 24
Peak memory 218420 kb
Host smart-ea7a1c44-19e1-4cc9-a5a5-6c0da09f4f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359995972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2359995972
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1555797204
Short name T103
Test name
Test status
Simulation time 243619126 ps
CPU time 1.13 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:45 PM PST 24
Peak memory 217616 kb
Host smart-79cf303b-12aa-4457-8bc3-d96a477929e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555797204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1555797204
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.462975616
Short name T286
Test name
Test status
Simulation time 156659752 ps
CPU time 0.81 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200528 kb
Host smart-95e77d1a-8090-46da-a334-19220595e267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462975616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.462975616
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2659811482
Short name T470
Test name
Test status
Simulation time 1197989784 ps
CPU time 5.7 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:49 PM PST 24
Peak memory 200800 kb
Host smart-434a87df-5a68-4259-a347-8c1a2066207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659811482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2659811482
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2691037279
Short name T153
Test name
Test status
Simulation time 179691066 ps
CPU time 1.18 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200500 kb
Host smart-bef1cb55-6935-4b19-a6c0-59ca55503546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691037279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2691037279
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1138799865
Short name T513
Test name
Test status
Simulation time 260155779 ps
CPU time 1.62 seconds
Started Feb 25 02:25:45 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200712 kb
Host smart-6efa491c-441b-4e54-b61a-7c549649efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138799865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1138799865
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.52615980
Short name T98
Test name
Test status
Simulation time 6580287276 ps
CPU time 22.98 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:26:09 PM PST 24
Peak memory 200892 kb
Host smart-24d00d2d-8528-469a-a433-141424ddc85a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52615980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.52615980
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2357865740
Short name T382
Test name
Test status
Simulation time 118998809 ps
CPU time 1.52 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:42 PM PST 24
Peak memory 200628 kb
Host smart-2130a3c8-88da-4d83-a2cf-8dd34225256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357865740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2357865740
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2787547446
Short name T454
Test name
Test status
Simulation time 65817472 ps
CPU time 0.79 seconds
Started Feb 25 02:25:42 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200500 kb
Host smart-faaf1d59-ad29-4cc6-8b2b-480aebed41ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787547446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2787547446
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3932469153
Short name T259
Test name
Test status
Simulation time 70870872 ps
CPU time 0.76 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200496 kb
Host smart-31fda3b7-5d85-47fd-a16a-ac5cb460362d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932469153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3932469153
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1712556921
Short name T375
Test name
Test status
Simulation time 2367671603 ps
CPU time 9.05 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 218676 kb
Host smart-0cff071b-c92e-4333-8605-ee612b8da31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712556921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1712556921
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.317446136
Short name T378
Test name
Test status
Simulation time 244863589 ps
CPU time 1.12 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 217944 kb
Host smart-92039c61-3d52-421a-bfae-162d5b7a7dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317446136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.317446136
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3777412513
Short name T537
Test name
Test status
Simulation time 195124703 ps
CPU time 0.85 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:42 PM PST 24
Peak memory 200368 kb
Host smart-69dede1a-b01d-4601-9a25-bc0ed2eb7871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777412513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3777412513
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1084022389
Short name T464
Test name
Test status
Simulation time 1545668158 ps
CPU time 5.64 seconds
Started Feb 25 02:25:42 PM PST 24
Finished Feb 25 02:25:48 PM PST 24
Peak memory 200792 kb
Host smart-79e4e819-e547-4aa7-927c-96df009bfc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084022389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1084022389
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3762975207
Short name T151
Test name
Test status
Simulation time 99986511 ps
CPU time 0.99 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:48 PM PST 24
Peak memory 200540 kb
Host smart-73f74480-4e3b-47c2-9c0a-84c2f227b96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762975207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3762975207
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.986404564
Short name T42
Test name
Test status
Simulation time 206540644 ps
CPU time 1.42 seconds
Started Feb 25 02:25:34 PM PST 24
Finished Feb 25 02:25:36 PM PST 24
Peak memory 200796 kb
Host smart-40b438a5-f505-41b4-b6e4-90153623514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986404564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.986404564
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2577945495
Short name T496
Test name
Test status
Simulation time 6167706303 ps
CPU time 27.89 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:26:14 PM PST 24
Peak memory 200896 kb
Host smart-7ba50cc1-6ed8-4c9c-a430-bd752a52f96c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577945495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2577945495
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.847567966
Short name T417
Test name
Test status
Simulation time 496369750 ps
CPU time 2.7 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:50 PM PST 24
Peak memory 200588 kb
Host smart-a8f3e08e-ee42-41e7-90f9-abd7b401cf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847567966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.847567966
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1981756688
Short name T7
Test name
Test status
Simulation time 213742222 ps
CPU time 1.29 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:45 PM PST 24
Peak memory 200524 kb
Host smart-58206011-f903-4f05-87d8-e96ec34182d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981756688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1981756688
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1496242693
Short name T530
Test name
Test status
Simulation time 79155182 ps
CPU time 0.75 seconds
Started Feb 25 02:23:42 PM PST 24
Finished Feb 25 02:23:43 PM PST 24
Peak memory 200484 kb
Host smart-8feb9e35-4312-4a60-85bb-83c405739b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496242693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1496242693
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2821913131
Short name T154
Test name
Test status
Simulation time 244194092 ps
CPU time 1.07 seconds
Started Feb 25 02:23:34 PM PST 24
Finished Feb 25 02:23:36 PM PST 24
Peak memory 217940 kb
Host smart-0b94e9a2-1de2-424e-85c6-0ad1df092430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821913131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2821913131
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3899990600
Short name T216
Test name
Test status
Simulation time 95530928 ps
CPU time 0.73 seconds
Started Feb 25 02:23:33 PM PST 24
Finished Feb 25 02:23:33 PM PST 24
Peak memory 200384 kb
Host smart-34b278b1-a310-4dbe-9859-e314797e9169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899990600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3899990600
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2495191886
Short name T274
Test name
Test status
Simulation time 1500632804 ps
CPU time 5.97 seconds
Started Feb 25 02:23:31 PM PST 24
Finished Feb 25 02:23:37 PM PST 24
Peak memory 200744 kb
Host smart-9340b6c5-9347-43b4-b3d5-35c8899d2de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495191886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2495191886
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1437342496
Short name T267
Test name
Test status
Simulation time 97067661 ps
CPU time 0.97 seconds
Started Feb 25 02:23:37 PM PST 24
Finished Feb 25 02:23:38 PM PST 24
Peak memory 200500 kb
Host smart-fc82bec4-c1a4-4a0c-a92f-8b87623cf330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437342496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1437342496
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1733304519
Short name T11
Test name
Test status
Simulation time 126079005 ps
CPU time 1.2 seconds
Started Feb 25 02:23:35 PM PST 24
Finished Feb 25 02:23:36 PM PST 24
Peak memory 200656 kb
Host smart-964f9f8c-92b2-42d9-ad6e-a0265753e421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733304519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1733304519
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1077779781
Short name T110
Test name
Test status
Simulation time 17225464075 ps
CPU time 57.22 seconds
Started Feb 25 02:23:44 PM PST 24
Finished Feb 25 02:24:41 PM PST 24
Peak memory 200904 kb
Host smart-80992056-c8ab-465c-8079-5d75b709c217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077779781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1077779781
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1589610481
Short name T409
Test name
Test status
Simulation time 392498583 ps
CPU time 2.39 seconds
Started Feb 25 02:23:37 PM PST 24
Finished Feb 25 02:23:40 PM PST 24
Peak memory 200588 kb
Host smart-772a7b65-52ea-4ba7-b497-c38ea264377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589610481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1589610481
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.816401206
Short name T472
Test name
Test status
Simulation time 62032761 ps
CPU time 0.73 seconds
Started Feb 25 02:23:33 PM PST 24
Finished Feb 25 02:23:34 PM PST 24
Peak memory 200500 kb
Host smart-4af4174b-db9d-4000-9431-98e773760412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816401206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.816401206
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4105613216
Short name T370
Test name
Test status
Simulation time 79355076 ps
CPU time 0.77 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:45 PM PST 24
Peak memory 200480 kb
Host smart-5dcc641c-14a4-4a1b-98ca-5ce592b4ab63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105613216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4105613216
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.5334345
Short name T47
Test name
Test status
Simulation time 1883335263 ps
CPU time 7.54 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 217412 kb
Host smart-0e820a5a-a495-4489-a6a2-12316ffc9a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5334345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.5334345
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.114968818
Short name T309
Test name
Test status
Simulation time 245371626 ps
CPU time 1.13 seconds
Started Feb 25 02:25:45 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 217872 kb
Host smart-2d65b118-482d-454a-a3ce-ba4aa0def1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114968818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.114968818
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.885278761
Short name T350
Test name
Test status
Simulation time 109195046 ps
CPU time 0.75 seconds
Started Feb 25 02:25:45 PM PST 24
Finished Feb 25 02:25:46 PM PST 24
Peak memory 200272 kb
Host smart-84b29a9f-211f-4529-9e29-77244716a6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885278761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.885278761
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4203530238
Short name T92
Test name
Test status
Simulation time 768075718 ps
CPU time 4.34 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200816 kb
Host smart-f1e77f5a-58f3-4738-9b04-4df856826645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203530238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4203530238
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2032433745
Short name T355
Test name
Test status
Simulation time 150449772 ps
CPU time 1.06 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:44 PM PST 24
Peak memory 200496 kb
Host smart-a10761b2-096a-401e-b769-0e9777d18c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032433745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2032433745
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1042254004
Short name T208
Test name
Test status
Simulation time 187327928 ps
CPU time 1.29 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:46 PM PST 24
Peak memory 200756 kb
Host smart-1da25563-c561-4487-92d3-e18e8ea22956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042254004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1042254004
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2060238534
Short name T445
Test name
Test status
Simulation time 133947025 ps
CPU time 1.71 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200564 kb
Host smart-3c3a15fb-8158-45ac-8f63-da6a9d700795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060238534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2060238534
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.419288001
Short name T249
Test name
Test status
Simulation time 222822678 ps
CPU time 1.42 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:45 PM PST 24
Peak memory 200544 kb
Host smart-46ae6057-ee8b-4939-8be8-5234ab127c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419288001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.419288001
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3139553041
Short name T198
Test name
Test status
Simulation time 86664461 ps
CPU time 0.83 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:44 PM PST 24
Peak memory 200488 kb
Host smart-e4a19691-5884-4bc8-a1ef-f25ff6dbd6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139553041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3139553041
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2630898018
Short name T29
Test name
Test status
Simulation time 1891747092 ps
CPU time 6.99 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:54 PM PST 24
Peak memory 222680 kb
Host smart-7bcdcfd5-916a-473a-809d-330490598428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630898018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2630898018
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1957033744
Short name T367
Test name
Test status
Simulation time 244403517 ps
CPU time 1.07 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 217964 kb
Host smart-df84adb2-9442-4c0f-bed4-aefb7d635f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957033744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1957033744
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.786122320
Short name T467
Test name
Test status
Simulation time 111526185 ps
CPU time 0.73 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:45 PM PST 24
Peak memory 200384 kb
Host smart-a853462d-8244-464c-8599-0751d5ec6eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786122320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.786122320
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3747080592
Short name T310
Test name
Test status
Simulation time 773905472 ps
CPU time 3.86 seconds
Started Feb 25 02:25:45 PM PST 24
Finished Feb 25 02:25:49 PM PST 24
Peak memory 200816 kb
Host smart-280c746c-5263-4b7d-8f8d-9e097b19e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747080592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3747080592
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4056480182
Short name T34
Test name
Test status
Simulation time 149615321 ps
CPU time 1.12 seconds
Started Feb 25 02:25:41 PM PST 24
Finished Feb 25 02:25:43 PM PST 24
Peak memory 200480 kb
Host smart-8c9e8c04-ad29-41df-8214-c0e334a40d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056480182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4056480182
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1208940610
Short name T348
Test name
Test status
Simulation time 196275635 ps
CPU time 1.48 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:49 PM PST 24
Peak memory 200708 kb
Host smart-114c4a75-5a8b-4a1c-b6d9-deff5e2babc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208940610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1208940610
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3739791907
Short name T96
Test name
Test status
Simulation time 4701518915 ps
CPU time 17.03 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:26:02 PM PST 24
Peak memory 200908 kb
Host smart-05fd5a75-d6ad-4850-b899-fa24067b8a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739791907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3739791907
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2271796049
Short name T325
Test name
Test status
Simulation time 133525918 ps
CPU time 1.69 seconds
Started Feb 25 02:25:45 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200584 kb
Host smart-7c0f4fa0-7065-40b5-a344-d232187ce33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271796049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2271796049
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3199848967
Short name T427
Test name
Test status
Simulation time 104665870 ps
CPU time 1.01 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200500 kb
Host smart-13cd273d-c059-4823-aceb-416a8757d992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199848967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3199848967
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.4033158313
Short name T516
Test name
Test status
Simulation time 71580543 ps
CPU time 0.78 seconds
Started Feb 25 02:25:48 PM PST 24
Finished Feb 25 02:25:49 PM PST 24
Peak memory 200504 kb
Host smart-cff5cc3b-d5a0-4aa2-ba99-c0eccec98d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033158313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.4033158313
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.349597824
Short name T281
Test name
Test status
Simulation time 1234915527 ps
CPU time 5.58 seconds
Started Feb 25 02:25:53 PM PST 24
Finished Feb 25 02:25:58 PM PST 24
Peak memory 221456 kb
Host smart-7ac08193-c6c8-427c-92fa-9468e7ab0447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349597824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.349597824
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1586820038
Short name T486
Test name
Test status
Simulation time 243952434 ps
CPU time 1.06 seconds
Started Feb 25 02:25:49 PM PST 24
Finished Feb 25 02:25:50 PM PST 24
Peak memory 218028 kb
Host smart-aaf6f1ad-d995-4a3b-9946-4a9c2f6dfd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586820038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1586820038
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3502807684
Short name T167
Test name
Test status
Simulation time 149235534 ps
CPU time 0.8 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200328 kb
Host smart-49d15f98-d074-44bc-9f58-2559914afe9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502807684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3502807684
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.4175753877
Short name T440
Test name
Test status
Simulation time 1731460355 ps
CPU time 7.32 seconds
Started Feb 25 02:25:48 PM PST 24
Finished Feb 25 02:25:56 PM PST 24
Peak memory 200748 kb
Host smart-3c8e20ca-c061-4322-8e28-49d789960ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175753877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.4175753877
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2113350478
Short name T396
Test name
Test status
Simulation time 152316948 ps
CPU time 1.13 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:49 PM PST 24
Peak memory 200540 kb
Host smart-86b376d1-af8d-4234-a9c2-5edfc6ca1c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113350478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2113350478
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.388539934
Short name T139
Test name
Test status
Simulation time 245565864 ps
CPU time 1.48 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:49 PM PST 24
Peak memory 200648 kb
Host smart-f97785fe-f05d-426a-a2fc-5d4412762c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388539934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.388539934
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.755691584
Short name T379
Test name
Test status
Simulation time 4052766293 ps
CPU time 14.87 seconds
Started Feb 25 02:25:52 PM PST 24
Finished Feb 25 02:26:07 PM PST 24
Peak memory 200864 kb
Host smart-6c8e33ff-3e24-4f66-beca-3c61e8929b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755691584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.755691584
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1646515287
Short name T39
Test name
Test status
Simulation time 474493875 ps
CPU time 2.74 seconds
Started Feb 25 02:25:43 PM PST 24
Finished Feb 25 02:25:46 PM PST 24
Peak memory 200312 kb
Host smart-c7734711-c80b-4250-b41c-e57733bde961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646515287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1646515287
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2065202524
Short name T442
Test name
Test status
Simulation time 161083080 ps
CPU time 1.16 seconds
Started Feb 25 02:25:44 PM PST 24
Finished Feb 25 02:25:45 PM PST 24
Peak memory 200516 kb
Host smart-8c610627-4eab-492f-bbb6-6579edc232a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065202524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2065202524
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.637903407
Short name T61
Test name
Test status
Simulation time 65367007 ps
CPU time 0.71 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200480 kb
Host smart-87b7cd82-2eb1-45e2-9adb-7bbdc2db40bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637903407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.637903407
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2583947813
Short name T257
Test name
Test status
Simulation time 1224999457 ps
CPU time 5.42 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:57 PM PST 24
Peak memory 221592 kb
Host smart-c9d19e89-e785-4020-94cd-fe3998717f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583947813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2583947813
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2687440823
Short name T23
Test name
Test status
Simulation time 244991697 ps
CPU time 1.11 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 217968 kb
Host smart-2e4223c5-0d10-429e-8565-b704bef34bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687440823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2687440823
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.648046697
Short name T324
Test name
Test status
Simulation time 197827133 ps
CPU time 0.83 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:51 PM PST 24
Peak memory 200364 kb
Host smart-85818066-52a8-45b4-99a5-0d2d3179b8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648046697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.648046697
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.4208783009
Short name T402
Test name
Test status
Simulation time 1662260998 ps
CPU time 7.08 seconds
Started Feb 25 02:25:48 PM PST 24
Finished Feb 25 02:25:55 PM PST 24
Peak memory 200816 kb
Host smart-1e8a8057-1e62-4cfa-9187-2124aee14a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208783009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4208783009
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1735842636
Short name T265
Test name
Test status
Simulation time 104287518 ps
CPU time 1.04 seconds
Started Feb 25 02:25:49 PM PST 24
Finished Feb 25 02:25:50 PM PST 24
Peak memory 200660 kb
Host smart-7a46e424-e363-4c27-ac8b-bb4096e9af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735842636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1735842636
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1781342287
Short name T73
Test name
Test status
Simulation time 234201454 ps
CPU time 1.42 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 200704 kb
Host smart-d77f6d53-f415-4050-9c76-c96d76eb0adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781342287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1781342287
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3342746195
Short name T291
Test name
Test status
Simulation time 1365090243 ps
CPU time 6.14 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:57 PM PST 24
Peak memory 200800 kb
Host smart-9969b661-7654-4ab1-89a1-ffe233cdc355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342746195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3342746195
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.974807497
Short name T191
Test name
Test status
Simulation time 390526829 ps
CPU time 2.15 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:53 PM PST 24
Peak memory 200624 kb
Host smart-3e84abce-3d3e-4bac-affc-725f121e18e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974807497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.974807497
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.907587118
Short name T41
Test name
Test status
Simulation time 130249851 ps
CPU time 1.09 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:51 PM PST 24
Peak memory 200516 kb
Host smart-3552fe28-9080-4828-978e-c03d478fd674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907587118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.907587118
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.40280039
Short name T415
Test name
Test status
Simulation time 68779009 ps
CPU time 0.74 seconds
Started Feb 25 02:25:48 PM PST 24
Finished Feb 25 02:25:49 PM PST 24
Peak memory 200488 kb
Host smart-e0c46671-ac62-4d65-81ad-02278229d458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.40280039
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.4045144246
Short name T28
Test name
Test status
Simulation time 1225741446 ps
CPU time 5.68 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:57 PM PST 24
Peak memory 218004 kb
Host smart-792cf4da-51ec-47e8-aa25-a6a77b0725d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045144246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4045144246
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2418223637
Short name T246
Test name
Test status
Simulation time 244165795 ps
CPU time 1.15 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 217916 kb
Host smart-418d73db-33fe-4aad-9400-d018745ad5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418223637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2418223637
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3181377285
Short name T333
Test name
Test status
Simulation time 135028050 ps
CPU time 0.86 seconds
Started Feb 25 02:25:52 PM PST 24
Finished Feb 25 02:25:53 PM PST 24
Peak memory 200360 kb
Host smart-15eda893-220d-4eb9-a747-ad5dbcf7272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181377285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3181377285
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2445341508
Short name T352
Test name
Test status
Simulation time 1650674661 ps
CPU time 5.81 seconds
Started Feb 25 02:25:52 PM PST 24
Finished Feb 25 02:25:58 PM PST 24
Peak memory 200804 kb
Host smart-3a479004-f8ac-42b1-87dc-c4d11225bc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445341508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2445341508
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1301166894
Short name T529
Test name
Test status
Simulation time 184583234 ps
CPU time 1.21 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 200520 kb
Host smart-22bb5844-ffe7-4dd8-ac14-13931af23264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301166894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1301166894
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.185672665
Short name T339
Test name
Test status
Simulation time 115077270 ps
CPU time 1.14 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 200736 kb
Host smart-293dc0f8-1f75-4e53-bd07-5b605e374b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185672665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.185672665
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2291149644
Short name T340
Test name
Test status
Simulation time 1715927788 ps
CPU time 7.3 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:58 PM PST 24
Peak memory 200776 kb
Host smart-220ba159-be03-437f-b2f9-0a218df62a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291149644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2291149644
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3794068535
Short name T236
Test name
Test status
Simulation time 326192636 ps
CPU time 2.09 seconds
Started Feb 25 02:25:48 PM PST 24
Finished Feb 25 02:25:50 PM PST 24
Peak memory 200592 kb
Host smart-624a9dc9-bac6-49d2-b256-d8f747c52d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794068535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3794068535
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4151722634
Short name T178
Test name
Test status
Simulation time 131998158 ps
CPU time 0.98 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:25:47 PM PST 24
Peak memory 200520 kb
Host smart-c1316726-0dec-4c0a-9120-067c57c94edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151722634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4151722634
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4016995057
Short name T192
Test name
Test status
Simulation time 82707492 ps
CPU time 0.78 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 200472 kb
Host smart-d19861ed-1daf-498c-bd10-e65c864256e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016995057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4016995057
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1688283354
Short name T45
Test name
Test status
Simulation time 1894793738 ps
CPU time 8.88 seconds
Started Feb 25 02:25:49 PM PST 24
Finished Feb 25 02:25:58 PM PST 24
Peak memory 217968 kb
Host smart-26231eed-f17c-4735-95bc-303924a61001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688283354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1688283354
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2021756412
Short name T521
Test name
Test status
Simulation time 244864326 ps
CPU time 1.08 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 217924 kb
Host smart-54912d83-26de-4689-b8a8-4af5878bc490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021756412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2021756412
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1840612131
Short name T306
Test name
Test status
Simulation time 100237751 ps
CPU time 0.74 seconds
Started Feb 25 02:25:47 PM PST 24
Finished Feb 25 02:25:48 PM PST 24
Peak memory 200328 kb
Host smart-0cf79a45-3a77-41fd-a467-9a835606cbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840612131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1840612131
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1748116033
Short name T338
Test name
Test status
Simulation time 989039404 ps
CPU time 5.06 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:56 PM PST 24
Peak memory 200788 kb
Host smart-8a986682-475a-488e-810f-45559fe92608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748116033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1748116033
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.701901080
Short name T172
Test name
Test status
Simulation time 144694386 ps
CPU time 1.18 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 200492 kb
Host smart-26b4a1a0-004a-481c-a0d3-20a50c0e9726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701901080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.701901080
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1139668648
Short name T451
Test name
Test status
Simulation time 117985095 ps
CPU time 1.12 seconds
Started Feb 25 02:25:46 PM PST 24
Finished Feb 25 02:25:48 PM PST 24
Peak memory 200708 kb
Host smart-46f99e88-1466-4250-8fcc-b0f07dec5d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139668648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1139668648
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1403093916
Short name T207
Test name
Test status
Simulation time 6443748312 ps
CPU time 25.66 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:26:18 PM PST 24
Peak memory 200892 kb
Host smart-38362789-47dd-4641-8303-431092aad7e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403093916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1403093916
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3941098751
Short name T40
Test name
Test status
Simulation time 113616693 ps
CPU time 1.54 seconds
Started Feb 25 02:25:53 PM PST 24
Finished Feb 25 02:25:54 PM PST 24
Peak memory 200556 kb
Host smart-a08d3ffc-9bbd-4638-b392-adb1ff5e52ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941098751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3941098751
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1408509057
Short name T507
Test name
Test status
Simulation time 88954707 ps
CPU time 0.8 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:53 PM PST 24
Peak memory 200500 kb
Host smart-dabc7eaf-6ffe-40f4-909e-80648aed96bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408509057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1408509057
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3894489095
Short name T37
Test name
Test status
Simulation time 96747340 ps
CPU time 0.85 seconds
Started Feb 25 02:25:58 PM PST 24
Finished Feb 25 02:25:59 PM PST 24
Peak memory 200492 kb
Host smart-acca5604-c196-4b1d-b6ee-b1740157313f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894489095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3894489095
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.928873694
Short name T349
Test name
Test status
Simulation time 1221781899 ps
CPU time 6.01 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:56 PM PST 24
Peak memory 222140 kb
Host smart-dc73e506-064c-461e-a6fa-93f1e0af15c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928873694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.928873694
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3459337383
Short name T499
Test name
Test status
Simulation time 244082463 ps
CPU time 1.15 seconds
Started Feb 25 02:25:55 PM PST 24
Finished Feb 25 02:25:57 PM PST 24
Peak memory 217860 kb
Host smart-01590244-1fc7-44e5-a357-e950a39bf5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459337383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3459337383
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2558866152
Short name T389
Test name
Test status
Simulation time 165451144 ps
CPU time 0.87 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 200380 kb
Host smart-9e45c24e-08d6-491d-9ad5-4f27a7ef8602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558866152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2558866152
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.832831264
Short name T429
Test name
Test status
Simulation time 905830157 ps
CPU time 4.73 seconds
Started Feb 25 02:25:48 PM PST 24
Finished Feb 25 02:25:53 PM PST 24
Peak memory 200752 kb
Host smart-c5e3e35a-4096-443f-ad14-00dcfbcb8a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832831264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.832831264
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.621796654
Short name T539
Test name
Test status
Simulation time 149116194 ps
CPU time 1.08 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 200492 kb
Host smart-67e0d67e-43e5-4f4a-9bf1-5f8c614a4d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621796654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.621796654
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4130932960
Short name T514
Test name
Test status
Simulation time 115736196 ps
CPU time 1.22 seconds
Started Feb 25 02:25:52 PM PST 24
Finished Feb 25 02:25:54 PM PST 24
Peak memory 200708 kb
Host smart-78a80325-3a94-4e87-a980-7124f4c45e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130932960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4130932960
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.287195796
Short name T328
Test name
Test status
Simulation time 7076129458 ps
CPU time 32.21 seconds
Started Feb 25 02:25:55 PM PST 24
Finished Feb 25 02:26:28 PM PST 24
Peak memory 200896 kb
Host smart-fc2cd227-ff8f-4b2e-9778-6c546f0cd2de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287195796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.287195796
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2007041691
Short name T184
Test name
Test status
Simulation time 128409017 ps
CPU time 1.56 seconds
Started Feb 25 02:25:51 PM PST 24
Finished Feb 25 02:25:54 PM PST 24
Peak memory 200552 kb
Host smart-e725401d-492c-426c-979b-348780c5effc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007041691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2007041691
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.646675567
Short name T72
Test name
Test status
Simulation time 235746275 ps
CPU time 1.5 seconds
Started Feb 25 02:25:50 PM PST 24
Finished Feb 25 02:25:52 PM PST 24
Peak memory 200724 kb
Host smart-c7b6686e-f846-4d90-bdac-cc12a7daa302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646675567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.646675567
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1761149669
Short name T134
Test name
Test status
Simulation time 73866820 ps
CPU time 0.75 seconds
Started Feb 25 02:25:59 PM PST 24
Finished Feb 25 02:26:00 PM PST 24
Peak memory 200492 kb
Host smart-8c8df1fe-8ef3-41d7-b8f4-a88ce977f81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761149669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1761149669
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.778247080
Short name T50
Test name
Test status
Simulation time 1224589327 ps
CPU time 5.46 seconds
Started Feb 25 02:25:56 PM PST 24
Finished Feb 25 02:26:01 PM PST 24
Peak memory 217444 kb
Host smart-418c4bdc-592d-47ee-a556-9687b3dc45ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778247080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.778247080
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2551333808
Short name T152
Test name
Test status
Simulation time 243856708 ps
CPU time 1.13 seconds
Started Feb 25 02:26:00 PM PST 24
Finished Feb 25 02:26:01 PM PST 24
Peak memory 217912 kb
Host smart-6b7b33ef-3cce-4a80-8e20-e3c4f01fba8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551333808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2551333808
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3313621499
Short name T215
Test name
Test status
Simulation time 170780879 ps
CPU time 0.93 seconds
Started Feb 25 02:26:01 PM PST 24
Finished Feb 25 02:26:02 PM PST 24
Peak memory 200384 kb
Host smart-601bd13f-fed3-47fe-8cb6-f83275b4f7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313621499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3313621499
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2409495828
Short name T449
Test name
Test status
Simulation time 1917787689 ps
CPU time 7.18 seconds
Started Feb 25 02:26:02 PM PST 24
Finished Feb 25 02:26:09 PM PST 24
Peak memory 200788 kb
Host smart-d7722d0d-4ed8-4bf7-bb26-5e55f0a17b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409495828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2409495828
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.801600832
Short name T275
Test name
Test status
Simulation time 150774764 ps
CPU time 1.17 seconds
Started Feb 25 02:25:59 PM PST 24
Finished Feb 25 02:26:00 PM PST 24
Peak memory 200508 kb
Host smart-492715e0-28ca-461a-8ca9-70515acb957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801600832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.801600832
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2402809697
Short name T461
Test name
Test status
Simulation time 113159264 ps
CPU time 1.23 seconds
Started Feb 25 02:26:03 PM PST 24
Finished Feb 25 02:26:04 PM PST 24
Peak memory 200736 kb
Host smart-393ec6e4-0f43-44f2-b404-6d95cf2e14de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402809697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2402809697
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1203629898
Short name T109
Test name
Test status
Simulation time 4349070717 ps
CPU time 22 seconds
Started Feb 25 02:25:54 PM PST 24
Finished Feb 25 02:26:17 PM PST 24
Peak memory 200768 kb
Host smart-2d6f7c96-1b81-4095-96a7-f55faae65493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203629898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1203629898
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.4192413788
Short name T70
Test name
Test status
Simulation time 269031725 ps
CPU time 2.05 seconds
Started Feb 25 02:25:56 PM PST 24
Finished Feb 25 02:25:59 PM PST 24
Peak memory 200560 kb
Host smart-f726302e-8f54-42b5-976f-d703b37b78da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192413788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4192413788
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2243597845
Short name T524
Test name
Test status
Simulation time 67910605 ps
CPU time 0.76 seconds
Started Feb 25 02:26:02 PM PST 24
Finished Feb 25 02:26:03 PM PST 24
Peak memory 200496 kb
Host smart-1fe9fe02-3ff4-4869-b219-a36d4f00d1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243597845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2243597845
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2798721523
Short name T424
Test name
Test status
Simulation time 67907179 ps
CPU time 0.81 seconds
Started Feb 25 02:26:05 PM PST 24
Finished Feb 25 02:26:05 PM PST 24
Peak memory 200476 kb
Host smart-6b0bd585-eabc-4ea9-bc3b-9d0d5fef1782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798721523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2798721523
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3218567488
Short name T307
Test name
Test status
Simulation time 2368500124 ps
CPU time 8.85 seconds
Started Feb 25 02:25:58 PM PST 24
Finished Feb 25 02:26:07 PM PST 24
Peak memory 218664 kb
Host smart-68eed883-0829-47bf-91cb-f22877a32e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218567488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3218567488
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3063114
Short name T254
Test name
Test status
Simulation time 244327117 ps
CPU time 1.08 seconds
Started Feb 25 02:26:00 PM PST 24
Finished Feb 25 02:26:01 PM PST 24
Peak memory 217988 kb
Host smart-8c038de9-98bc-4945-9217-0a026886a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3063114
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3974225318
Short name T311
Test name
Test status
Simulation time 226987766 ps
CPU time 0.91 seconds
Started Feb 25 02:25:55 PM PST 24
Finished Feb 25 02:25:56 PM PST 24
Peak memory 200384 kb
Host smart-7d51e066-7dc3-4122-bcca-c4d8d0113d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974225318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3974225318
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2721259029
Short name T290
Test name
Test status
Simulation time 1517843590 ps
CPU time 6.2 seconds
Started Feb 25 02:25:55 PM PST 24
Finished Feb 25 02:26:02 PM PST 24
Peak memory 200820 kb
Host smart-af94e224-f536-411b-bfd8-a7dd7164dfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721259029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2721259029
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1741890565
Short name T3
Test name
Test status
Simulation time 101904493 ps
CPU time 1 seconds
Started Feb 25 02:26:02 PM PST 24
Finished Feb 25 02:26:03 PM PST 24
Peak memory 200500 kb
Host smart-9b8c67aa-b4e1-4324-bbc2-bb7a28feb6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741890565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1741890565
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3867159719
Short name T455
Test name
Test status
Simulation time 256660846 ps
CPU time 1.72 seconds
Started Feb 25 02:26:02 PM PST 24
Finished Feb 25 02:26:04 PM PST 24
Peak memory 200700 kb
Host smart-d0518ffd-72e2-4c07-997a-419e7479381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867159719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3867159719
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2109290469
Short name T252
Test name
Test status
Simulation time 5272290895 ps
CPU time 22.93 seconds
Started Feb 25 02:25:57 PM PST 24
Finished Feb 25 02:26:20 PM PST 24
Peak memory 200856 kb
Host smart-076ffb5a-3784-4307-80fa-f99a0003a3ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109290469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2109290469
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2730271126
Short name T67
Test name
Test status
Simulation time 389375237 ps
CPU time 2.34 seconds
Started Feb 25 02:25:57 PM PST 24
Finished Feb 25 02:26:00 PM PST 24
Peak memory 200604 kb
Host smart-61d76be2-4966-43bf-a9a5-fdb23b006b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730271126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2730271126
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3174000466
Short name T490
Test name
Test status
Simulation time 266156833 ps
CPU time 1.56 seconds
Started Feb 25 02:26:02 PM PST 24
Finished Feb 25 02:26:04 PM PST 24
Peak memory 200496 kb
Host smart-8f5dff75-7780-4351-be35-831f2be20d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174000466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3174000466
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.402743895
Short name T296
Test name
Test status
Simulation time 82411460 ps
CPU time 0.78 seconds
Started Feb 25 02:25:57 PM PST 24
Finished Feb 25 02:25:58 PM PST 24
Peak memory 200492 kb
Host smart-99e87358-ae16-477a-8c88-c5b252c767e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402743895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.402743895
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1610501898
Short name T494
Test name
Test status
Simulation time 1217464591 ps
CPU time 6.11 seconds
Started Feb 25 02:26:04 PM PST 24
Finished Feb 25 02:26:11 PM PST 24
Peak memory 218548 kb
Host smart-9f790c9d-96d6-40f6-b0d8-f87da0fae1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610501898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1610501898
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4055725586
Short name T219
Test name
Test status
Simulation time 244280739 ps
CPU time 1.09 seconds
Started Feb 25 02:25:54 PM PST 24
Finished Feb 25 02:25:56 PM PST 24
Peak memory 217972 kb
Host smart-99c3bfe5-93e8-405c-8dec-e8e9ba208448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055725586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4055725586
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.475704895
Short name T327
Test name
Test status
Simulation time 127902298 ps
CPU time 0.75 seconds
Started Feb 25 02:25:55 PM PST 24
Finished Feb 25 02:25:56 PM PST 24
Peak memory 200372 kb
Host smart-e7d6729a-4d06-46fe-8acd-090250a4eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475704895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.475704895
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3950760237
Short name T359
Test name
Test status
Simulation time 1547716707 ps
CPU time 6.42 seconds
Started Feb 25 02:25:58 PM PST 24
Finished Feb 25 02:26:05 PM PST 24
Peak memory 200788 kb
Host smart-a7e7e444-8daf-413b-9062-b5454316e0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950760237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3950760237
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1665506535
Short name T276
Test name
Test status
Simulation time 151661630 ps
CPU time 1.14 seconds
Started Feb 25 02:25:56 PM PST 24
Finished Feb 25 02:25:57 PM PST 24
Peak memory 200504 kb
Host smart-94015374-9ff4-41de-8509-773299a56ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665506535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1665506535
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.187108981
Short name T284
Test name
Test status
Simulation time 193233876 ps
CPU time 1.4 seconds
Started Feb 25 02:25:55 PM PST 24
Finished Feb 25 02:25:57 PM PST 24
Peak memory 200688 kb
Host smart-06317bb0-f87a-4818-97c6-985872dd89c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187108981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.187108981
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1454914117
Short name T447
Test name
Test status
Simulation time 206536805 ps
CPU time 1.25 seconds
Started Feb 25 02:26:04 PM PST 24
Finished Feb 25 02:26:06 PM PST 24
Peak memory 200504 kb
Host smart-4b0010ea-9578-4e2b-8f67-08a675b35c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454914117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1454914117
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2180269818
Short name T251
Test name
Test status
Simulation time 355875252 ps
CPU time 2.16 seconds
Started Feb 25 02:25:56 PM PST 24
Finished Feb 25 02:25:58 PM PST 24
Peak memory 200560 kb
Host smart-69e2da6a-992e-4da9-a07b-89753d12442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180269818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2180269818
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1178767249
Short name T441
Test name
Test status
Simulation time 117529760 ps
CPU time 1.13 seconds
Started Feb 25 02:25:59 PM PST 24
Finished Feb 25 02:26:00 PM PST 24
Peak memory 200516 kb
Host smart-7544db07-15a1-4b0f-82f8-27f22b0fcf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178767249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1178767249
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3404865016
Short name T156
Test name
Test status
Simulation time 68282584 ps
CPU time 0.77 seconds
Started Feb 25 02:23:42 PM PST 24
Finished Feb 25 02:23:42 PM PST 24
Peak memory 200520 kb
Host smart-4f9d6467-a227-4c26-a01d-234855eb5f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404865016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3404865016
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1844271218
Short name T293
Test name
Test status
Simulation time 2149885500 ps
CPU time 8.92 seconds
Started Feb 25 02:23:42 PM PST 24
Finished Feb 25 02:23:51 PM PST 24
Peak memory 218072 kb
Host smart-7682e6d1-5468-4fa9-a2f3-905ba6064fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844271218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1844271218
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1614276695
Short name T177
Test name
Test status
Simulation time 243906275 ps
CPU time 1.07 seconds
Started Feb 25 02:23:43 PM PST 24
Finished Feb 25 02:23:44 PM PST 24
Peak memory 217984 kb
Host smart-37c34d9c-4bd0-46d7-b62d-682e9e9d77b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614276695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1614276695
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.704200305
Short name T295
Test name
Test status
Simulation time 159203392 ps
CPU time 0.8 seconds
Started Feb 25 02:23:44 PM PST 24
Finished Feb 25 02:23:45 PM PST 24
Peak memory 200372 kb
Host smart-cecc9494-a9df-4350-b93b-31b0fc645b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704200305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.704200305
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.4058434997
Short name T228
Test name
Test status
Simulation time 1191336926 ps
CPU time 5.02 seconds
Started Feb 25 02:23:43 PM PST 24
Finished Feb 25 02:23:48 PM PST 24
Peak memory 200800 kb
Host smart-d175f0d8-76cb-470e-9ca0-115aa4177181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058434997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.4058434997
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3788832486
Short name T533
Test name
Test status
Simulation time 144361875 ps
CPU time 1.04 seconds
Started Feb 25 02:23:42 PM PST 24
Finished Feb 25 02:23:43 PM PST 24
Peak memory 200504 kb
Host smart-4478b5f7-568a-4fc0-9ae1-d7649e6e304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788832486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3788832486
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.638816699
Short name T212
Test name
Test status
Simulation time 185690629 ps
CPU time 1.35 seconds
Started Feb 25 02:23:44 PM PST 24
Finished Feb 25 02:23:45 PM PST 24
Peak memory 200744 kb
Host smart-d9b58f31-9802-4928-b747-5f48c5c045df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638816699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.638816699
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1910185256
Short name T253
Test name
Test status
Simulation time 4083305063 ps
CPU time 16.08 seconds
Started Feb 25 02:23:44 PM PST 24
Finished Feb 25 02:24:00 PM PST 24
Peak memory 200900 kb
Host smart-1b156d83-7b63-4003-b3fb-99d36033dd46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910185256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1910185256
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.4067954665
Short name T79
Test name
Test status
Simulation time 385707582 ps
CPU time 2.25 seconds
Started Feb 25 02:23:41 PM PST 24
Finished Feb 25 02:23:44 PM PST 24
Peak memory 200552 kb
Host smart-dfd9f298-daf6-4212-8b61-f5091a7d5da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067954665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.4067954665
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.623764167
Short name T317
Test name
Test status
Simulation time 120570689 ps
CPU time 1.1 seconds
Started Feb 25 02:23:42 PM PST 24
Finished Feb 25 02:23:43 PM PST 24
Peak memory 200516 kb
Host smart-d3ce081d-dd04-4eec-ac1b-b75196fa924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623764167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.623764167
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3598322167
Short name T504
Test name
Test status
Simulation time 72202265 ps
CPU time 0.74 seconds
Started Feb 25 02:23:56 PM PST 24
Finished Feb 25 02:23:57 PM PST 24
Peak memory 200464 kb
Host smart-52a835f6-4f59-49e3-95f2-9be43e832967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598322167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3598322167
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1858609179
Short name T46
Test name
Test status
Simulation time 2339298037 ps
CPU time 8.43 seconds
Started Feb 25 02:23:56 PM PST 24
Finished Feb 25 02:24:04 PM PST 24
Peak memory 222492 kb
Host smart-9349bf22-1acf-400d-a9c1-b9a000a75978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858609179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1858609179
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2013507581
Short name T158
Test name
Test status
Simulation time 245081025 ps
CPU time 1.04 seconds
Started Feb 25 02:23:55 PM PST 24
Finished Feb 25 02:23:56 PM PST 24
Peak memory 217868 kb
Host smart-983b568d-0c6c-4717-8c0c-d16139e41bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013507581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2013507581
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2205614930
Short name T209
Test name
Test status
Simulation time 167024889 ps
CPU time 0.83 seconds
Started Feb 25 02:23:44 PM PST 24
Finished Feb 25 02:23:45 PM PST 24
Peak memory 200404 kb
Host smart-a81ffeaa-f48d-410a-a025-54bdee948058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205614930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2205614930
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.918444824
Short name T196
Test name
Test status
Simulation time 846402662 ps
CPU time 4.29 seconds
Started Feb 25 02:23:40 PM PST 24
Finished Feb 25 02:23:44 PM PST 24
Peak memory 200748 kb
Host smart-1243cd1e-3f92-4a9a-831e-e2eccf91fd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918444824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.918444824
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3966198967
Short name T256
Test name
Test status
Simulation time 180408523 ps
CPU time 1.24 seconds
Started Feb 25 02:23:57 PM PST 24
Finished Feb 25 02:23:58 PM PST 24
Peak memory 200500 kb
Host smart-ec6f3576-5c49-416e-838e-685ab5649710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966198967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3966198967
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2267796693
Short name T157
Test name
Test status
Simulation time 125906389 ps
CPU time 1.15 seconds
Started Feb 25 02:23:42 PM PST 24
Finished Feb 25 02:23:43 PM PST 24
Peak memory 200748 kb
Host smart-5315b559-7e85-4179-82ee-ebbecf1fceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267796693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2267796693
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1082863597
Short name T390
Test name
Test status
Simulation time 7520712382 ps
CPU time 37.94 seconds
Started Feb 25 02:23:59 PM PST 24
Finished Feb 25 02:24:37 PM PST 24
Peak memory 200940 kb
Host smart-7ce94a05-b930-4168-8bb8-eb2d51cfc1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082863597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1082863597
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1665978624
Short name T80
Test name
Test status
Simulation time 116570791 ps
CPU time 1.44 seconds
Started Feb 25 02:23:56 PM PST 24
Finished Feb 25 02:23:57 PM PST 24
Peak memory 200500 kb
Host smart-966ffd3c-8e54-44c2-9e7d-03ad4fb5819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665978624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1665978624
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2510793452
Short name T266
Test name
Test status
Simulation time 99867522 ps
CPU time 0.86 seconds
Started Feb 25 02:23:56 PM PST 24
Finished Feb 25 02:23:57 PM PST 24
Peak memory 200452 kb
Host smart-872b9bd1-e5ba-405e-ac13-0b72b9c8f9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510793452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2510793452
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1355984131
Short name T255
Test name
Test status
Simulation time 66664181 ps
CPU time 0.69 seconds
Started Feb 25 02:24:04 PM PST 24
Finished Feb 25 02:24:05 PM PST 24
Peak memory 200492 kb
Host smart-0a8b0c89-69fe-44e7-852f-d9572073cb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355984131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1355984131
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3210759507
Short name T517
Test name
Test status
Simulation time 1905678347 ps
CPU time 7.29 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:14 PM PST 24
Peak memory 217408 kb
Host smart-67e8c75a-029b-4b4b-bd42-a5400d9632ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210759507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3210759507
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1803521232
Short name T432
Test name
Test status
Simulation time 245027099 ps
CPU time 1.19 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:08 PM PST 24
Peak memory 217940 kb
Host smart-4486304a-f025-4ab0-8519-570f05434302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803521232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1803521232
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.4102052507
Short name T474
Test name
Test status
Simulation time 182859932 ps
CPU time 0.89 seconds
Started Feb 25 02:23:55 PM PST 24
Finished Feb 25 02:23:56 PM PST 24
Peak memory 200368 kb
Host smart-1a2bc95d-994c-4c83-8a16-b0f757962a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102052507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4102052507
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1204285602
Short name T342
Test name
Test status
Simulation time 1454829539 ps
CPU time 5.56 seconds
Started Feb 25 02:23:55 PM PST 24
Finished Feb 25 02:24:01 PM PST 24
Peak memory 200768 kb
Host smart-6571381f-9c62-4ba9-9bb2-070d11f2c0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204285602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1204285602
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.4054545102
Short name T135
Test name
Test status
Simulation time 183623871 ps
CPU time 1.29 seconds
Started Feb 25 02:24:05 PM PST 24
Finished Feb 25 02:24:07 PM PST 24
Peak memory 200524 kb
Host smart-a41a1ba3-5985-46ad-aa4d-3ba66a0c8467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054545102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.4054545102
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1818516795
Short name T162
Test name
Test status
Simulation time 245365663 ps
CPU time 1.47 seconds
Started Feb 25 02:23:55 PM PST 24
Finished Feb 25 02:23:57 PM PST 24
Peak memory 200720 kb
Host smart-d00d69d0-2216-4c8f-a052-49f17a51ba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818516795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1818516795
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2495504550
Short name T113
Test name
Test status
Simulation time 1207712208 ps
CPU time 6.16 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:13 PM PST 24
Peak memory 200740 kb
Host smart-22192b1b-d0a1-4332-97a7-650c5443c662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495504550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2495504550
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.703422873
Short name T371
Test name
Test status
Simulation time 316202542 ps
CPU time 2.06 seconds
Started Feb 25 02:24:07 PM PST 24
Finished Feb 25 02:24:09 PM PST 24
Peak memory 200592 kb
Host smart-8ed09735-22e1-4ccb-8335-94bc675026e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703422873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.703422873
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3498605862
Short name T250
Test name
Test status
Simulation time 136333065 ps
CPU time 1.05 seconds
Started Feb 25 02:23:56 PM PST 24
Finished Feb 25 02:23:58 PM PST 24
Peak memory 200472 kb
Host smart-64ccadb3-824b-402c-ae3d-1a2a6a365f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498605862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3498605862
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1052517021
Short name T331
Test name
Test status
Simulation time 52698411 ps
CPU time 0.69 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:07 PM PST 24
Peak memory 200436 kb
Host smart-8217c6d4-a473-412d-9f71-035528f7a470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052517021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1052517021
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2804728158
Short name T410
Test name
Test status
Simulation time 1897716601 ps
CPU time 7.49 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:14 PM PST 24
Peak memory 217452 kb
Host smart-d6728b81-ece8-4d62-bba1-eee7ff641105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804728158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2804728158
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2771696287
Short name T360
Test name
Test status
Simulation time 245817721 ps
CPU time 1.04 seconds
Started Feb 25 02:24:07 PM PST 24
Finished Feb 25 02:24:09 PM PST 24
Peak memory 217984 kb
Host smart-18d26737-0632-488a-bc41-9d250636c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771696287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2771696287
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1849063824
Short name T262
Test name
Test status
Simulation time 184568065 ps
CPU time 0.9 seconds
Started Feb 25 02:24:05 PM PST 24
Finished Feb 25 02:24:06 PM PST 24
Peak memory 200384 kb
Host smart-763d9df7-5e4b-4d2d-a595-cc42068755ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849063824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1849063824
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2809809092
Short name T412
Test name
Test status
Simulation time 1884462663 ps
CPU time 7.66 seconds
Started Feb 25 02:24:09 PM PST 24
Finished Feb 25 02:24:17 PM PST 24
Peak memory 200732 kb
Host smart-458dee10-4f2f-43f7-9fd9-fc7ec29ce3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809809092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2809809092
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2065978632
Short name T393
Test name
Test status
Simulation time 137281094 ps
CPU time 1.16 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:08 PM PST 24
Peak memory 200436 kb
Host smart-0cbce58d-f72e-47bc-b05a-a852e54a7061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065978632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2065978632
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3236128050
Short name T376
Test name
Test status
Simulation time 186605932 ps
CPU time 1.39 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:08 PM PST 24
Peak memory 200728 kb
Host smart-543fad75-62e0-4520-b509-6f7ad9544a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236128050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3236128050
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.355851173
Short name T326
Test name
Test status
Simulation time 4107444273 ps
CPU time 22.23 seconds
Started Feb 25 02:24:07 PM PST 24
Finished Feb 25 02:24:30 PM PST 24
Peak memory 200808 kb
Host smart-9c202f23-ba39-4543-8e11-fd1591e001d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355851173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.355851173
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2948427386
Short name T137
Test name
Test status
Simulation time 107078737 ps
CPU time 0.88 seconds
Started Feb 25 02:24:04 PM PST 24
Finished Feb 25 02:24:06 PM PST 24
Peak memory 200504 kb
Host smart-9406d670-1b90-450f-9549-0f5063becc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948427386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2948427386
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.25107066
Short name T318
Test name
Test status
Simulation time 68899110 ps
CPU time 0.81 seconds
Started Feb 25 02:24:07 PM PST 24
Finished Feb 25 02:24:08 PM PST 24
Peak memory 200380 kb
Host smart-1e44330b-4318-47ea-9653-93a443f9eb8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25107066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.25107066
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2491712913
Short name T493
Test name
Test status
Simulation time 1902012833 ps
CPU time 7.38 seconds
Started Feb 25 02:24:07 PM PST 24
Finished Feb 25 02:24:15 PM PST 24
Peak memory 218572 kb
Host smart-29621e8a-b401-4235-baf1-029c33afa88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491712913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2491712913
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3585989434
Short name T540
Test name
Test status
Simulation time 244024393 ps
CPU time 1.03 seconds
Started Feb 25 02:24:04 PM PST 24
Finished Feb 25 02:24:06 PM PST 24
Peak memory 217868 kb
Host smart-efa8f359-075c-42aa-b1ce-8b8de58c9f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585989434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3585989434
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3710809052
Short name T10
Test name
Test status
Simulation time 182613271 ps
CPU time 0.84 seconds
Started Feb 25 02:24:07 PM PST 24
Finished Feb 25 02:24:08 PM PST 24
Peak memory 200376 kb
Host smart-2bec5bc7-5358-4c29-b3f5-124a54ae8260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710809052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3710809052
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3752213267
Short name T520
Test name
Test status
Simulation time 1114030213 ps
CPU time 5.34 seconds
Started Feb 25 02:24:05 PM PST 24
Finished Feb 25 02:24:11 PM PST 24
Peak memory 200784 kb
Host smart-d8f44eca-cc6c-48de-89ac-41ed18c501f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752213267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3752213267
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1642720317
Short name T419
Test name
Test status
Simulation time 186993056 ps
CPU time 1.26 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:08 PM PST 24
Peak memory 200468 kb
Host smart-4fa04f64-9b2f-497d-b668-4c17e76f2799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642720317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1642720317
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2928665088
Short name T508
Test name
Test status
Simulation time 261736430 ps
CPU time 1.52 seconds
Started Feb 25 02:24:07 PM PST 24
Finished Feb 25 02:24:09 PM PST 24
Peak memory 200716 kb
Host smart-e53d52f7-e032-4f27-aecb-7b508d6697d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928665088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2928665088
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1890237414
Short name T297
Test name
Test status
Simulation time 2234250444 ps
CPU time 9.91 seconds
Started Feb 25 02:24:06 PM PST 24
Finished Feb 25 02:24:17 PM PST 24
Peak memory 200804 kb
Host smart-778c501d-da78-4cad-bfde-8f50e7cb4d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890237414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1890237414
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1435937286
Short name T385
Test name
Test status
Simulation time 275864702 ps
CPU time 1.9 seconds
Started Feb 25 02:24:05 PM PST 24
Finished Feb 25 02:24:07 PM PST 24
Peak memory 200500 kb
Host smart-114ce33f-2a56-4ef1-9623-ac02e308a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435937286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1435937286
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.4059800024
Short name T74
Test name
Test status
Simulation time 123749737 ps
CPU time 1.06 seconds
Started Feb 25 02:24:08 PM PST 24
Finished Feb 25 02:24:09 PM PST 24
Peak memory 200504 kb
Host smart-5887a9d8-39e6-4617-8d79-d9459bf485be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059800024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.4059800024
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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