Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	616411	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

371467

1

T1

28

T3

1274

T4

1084

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	526754	1			T1	36		T2	1		T3	1891
values[0x0]	230013	1			T1	15		T3	674		T4	860
values[0x1]	231111	1			T1	25		T3	680		T4	840

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	517101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

470777

1

T1

34

T3

1614

T4

1408

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3344	1			T3	17		T4	11		T5	3
valid_sources[0x01]	2931	1			T3	10		T4	19		T6	2
valid_sources[0x02]	3421	1			T3	12		T4	11		T5	3
valid_sources[0x03]	5117	1			T3	12		T4	16		T5	4
valid_sources[0x04]	4112	1			T3	17		T4	12		T5	2
valid_sources[0x05]	3187	1			T3	14		T4	14		T5	4
valid_sources[0x06]	3668	1			T3	17		T4	16		T5	3
valid_sources[0x07]	3928	1			T3	19		T4	15		T5	1
valid_sources[0x08]	3770	1			T3	11		T4	14		T5	1
valid_sources[0x09]	3622	1			T3	12		T4	7		T5	7
valid_sources[0x0a]	4801	1			T3	19		T4	17		T5	1
valid_sources[0x0b]	3579	1			T1	3		T3	10		T4	10
valid_sources[0x0c]	3874	1			T3	9		T4	20		T5	3
valid_sources[0x0d]	4139	1			T1	1		T3	12		T4	10
valid_sources[0x0e]	3473	1			T3	8		T4	14		T5	3
valid_sources[0x0f]	3974	1			T3	8		T4	12		T5	3
valid_sources[0x10]	3347	1			T3	13		T4	19		T5	3
valid_sources[0x11]	4405	1			T3	10		T4	7		T5	7
valid_sources[0x12]	3716	1			T3	11		T4	13		T6	19
valid_sources[0x13]	3662	1			T3	10		T4	7		T5	3
valid_sources[0x14]	3268	1			T3	9		T4	11		T5	5
valid_sources[0x15]	4513	1			T3	17		T4	8		T5	1
valid_sources[0x16]	4041	1			T3	10		T4	8		T5	3
valid_sources[0x17]	3095	1			T2	1		T3	10		T4	9
valid_sources[0x18]	3298	1			T3	11		T4	11		T5	1
valid_sources[0x19]	5420	1			T3	19		T4	4		T5	5
valid_sources[0x1a]	3020	1			T3	12		T4	16		T5	4
valid_sources[0x1b]	3286	1			T3	9		T4	8		T5	1
valid_sources[0x1c]	4161	1			T1	2		T3	11		T4	11
valid_sources[0x1d]	3600	1			T1	5		T3	13		T4	22
valid_sources[0x1e]	3038	1			T3	15		T4	10		T5	3
valid_sources[0x1f]	3894	1			T3	11		T4	9		T5	3
valid_sources[0x20]	3769	1			T3	11		T4	20		T5	2
valid_sources[0x21]	3555	1			T3	8		T4	6		T5	1
valid_sources[0x22]	3582	1			T3	16		T4	10		T5	4
valid_sources[0x23]	7411	1			T3	15		T4	20		T6	5
valid_sources[0x24]	3481	1			T1	4		T3	14		T4	12
valid_sources[0x25]	4432	1			T3	12		T4	9		T5	1
valid_sources[0x26]	3799	1			T3	11		T4	24		T5	4
valid_sources[0x27]	3823	1			T3	14		T4	10		T5	3
valid_sources[0x28]	3807	1			T3	7		T4	15		T5	1
valid_sources[0x29]	4060	1			T3	11		T4	11		T5	2
valid_sources[0x2a]	3527	1			T3	15		T4	5		T5	3
valid_sources[0x2b]	3872	1			T3	15		T4	10		T5	4
valid_sources[0x2c]	3608	1			T3	12		T4	12		T5	5
valid_sources[0x2d]	3992	1			T3	15		T4	14		T5	6
valid_sources[0x2e]	3808	1			T3	10		T4	6		T5	5
valid_sources[0x2f]	3629	1			T3	14		T4	19		T6	4
valid_sources[0x30]	2977	1			T3	17		T4	8		T5	1
valid_sources[0x31]	3633	1			T3	6		T4	12		T5	1
valid_sources[0x32]	3498	1			T3	8		T4	15		T5	3
valid_sources[0x33]	4433	1			T3	8		T4	9		T5	5
valid_sources[0x34]	3760	1			T1	9		T3	15		T4	14
valid_sources[0x35]	3721	1			T3	11		T4	12		T5	5
valid_sources[0x36]	3547	1			T3	20		T4	14		T5	2
valid_sources[0x37]	3715	1			T3	12		T4	8		T5	3
valid_sources[0x38]	3666	1			T3	11		T4	6		T5	3
valid_sources[0x39]	3240	1			T3	11		T4	12		T6	26
valid_sources[0x3a]	3210	1			T3	12		T4	8		T5	1
valid_sources[0x3b]	3296	1			T1	1		T3	9		T4	14
valid_sources[0x3c]	3670	1			T3	8		T4	11		T5	1
valid_sources[0x3d]	5175	1			T3	6		T4	9		T5	4
valid_sources[0x3e]	3139	1			T3	22		T4	10		T5	3
valid_sources[0x3f]	3011	1			T3	8		T4	14		T5	2
valid_sources[0x40]	3272	1			T3	19		T4	8		T5	1
valid_sources[0x41]	3407	1			T3	16		T4	14		T5	2
valid_sources[0x42]	3423	1			T1	1		T3	14		T4	16
valid_sources[0x43]	7730	1			T3	14		T4	9		T5	3
valid_sources[0x44]	3388	1			T3	9		T4	15		T5	2
valid_sources[0x45]	3473	1			T3	15		T4	13		T5	1
valid_sources[0x46]	3685	1			T3	19		T4	14		T5	5
valid_sources[0x47]	3651	1			T3	17		T4	11		T5	2
valid_sources[0x48]	3668	1			T1	3		T3	10		T4	16
valid_sources[0x49]	3962	1			T3	15		T4	18		T5	4
valid_sources[0x4a]	4756	1			T1	1		T3	12		T4	19
valid_sources[0x4b]	3841	1			T3	16		T4	18		T5	5
valid_sources[0x4c]	3863	1			T3	10		T4	15		T5	2
valid_sources[0x4d]	4207	1			T3	14		T4	5		T5	2
valid_sources[0x4e]	4623	1			T3	3		T4	16		T5	4
valid_sources[0x4f]	3393	1			T1	1		T3	14		T4	7
valid_sources[0x50]	4400	1			T3	9		T4	13		T5	1
valid_sources[0x51]	3383	1			T3	12		T4	17		T5	5
valid_sources[0x52]	3541	1			T3	9		T4	13		T5	2
valid_sources[0x53]	3665	1			T3	12		T4	11		T5	2
valid_sources[0x54]	3347	1			T3	11		T4	13		T5	5
valid_sources[0x55]	3211	1			T3	8		T4	12		T5	2
valid_sources[0x56]	3579	1			T3	13		T4	15		T5	1
valid_sources[0x57]	4051	1			T3	14		T4	9		T5	4
valid_sources[0x58]	3815	1			T3	8		T4	23		T5	6
valid_sources[0x59]	3945	1			T3	10		T4	9		T5	3
valid_sources[0x5a]	4249	1			T3	16		T4	12		T5	3
valid_sources[0x5b]	3550	1			T3	16		T4	14		T5	4
valid_sources[0x5c]	3862	1			T1	11		T3	10		T4	19
valid_sources[0x5d]	3458	1			T3	10		T4	9		T5	4
valid_sources[0x5e]	4539	1			T3	15		T4	10		T5	2
valid_sources[0x5f]	3358	1			T3	7		T4	10		T5	3
valid_sources[0x60]	4031	1			T3	9		T4	9		T5	2
valid_sources[0x61]	6360	1			T3	13		T4	11		T5	5
valid_sources[0x62]	2983	1			T3	14		T4	19		T5	4
valid_sources[0x63]	3687	1			T3	15		T4	19		T5	4
valid_sources[0x64]	3118	1			T3	14		T4	9		T5	5
valid_sources[0x65]	3294	1			T3	11		T4	19		T7	2
valid_sources[0x66]	3652	1			T3	12		T4	12		T5	2
valid_sources[0x67]	6934	1			T3	14		T4	9		T5	4
valid_sources[0x68]	4121	1			T3	14		T4	11		T5	2
valid_sources[0x69]	5288	1			T3	13		T4	25		T5	2
valid_sources[0x6a]	3873	1			T3	21		T4	17		T5	1
valid_sources[0x6b]	4051	1			T3	12		T4	11		T5	3
valid_sources[0x6c]	3640	1			T3	12		T4	22		T5	5
valid_sources[0x6d]	3459	1			T3	12		T4	12		T5	1
valid_sources[0x6e]	3620	1			T3	15		T4	14		T5	2
valid_sources[0x6f]	3543	1			T3	12		T4	16		T5	3
valid_sources[0x70]	4063	1			T1	3		T3	15		T4	10
valid_sources[0x71]	3664	1			T3	20		T4	9		T5	2
valid_sources[0x72]	3378	1			T3	11		T4	6		T5	1
valid_sources[0x73]	3423	1			T3	10		T4	20		T5	2
valid_sources[0x74]	3587	1			T3	10		T4	9		T5	3
valid_sources[0x75]	4256	1			T3	14		T4	24		T5	5
valid_sources[0x76]	3495	1			T3	10		T4	21		T5	3
valid_sources[0x77]	3232	1			T1	1		T3	11		T4	14
valid_sources[0x78]	3922	1			T3	14		T4	18		T5	3
valid_sources[0x79]	3365	1			T3	14		T4	15		T5	4
valid_sources[0x7a]	3516	1			T3	11		T4	8		T5	2
valid_sources[0x7b]	3486	1			T1	12		T3	9		T4	10
valid_sources[0x7c]	3104	1			T3	15		T4	11		T5	1
valid_sources[0x7d]	4271	1			T3	18		T4	9		T5	2
valid_sources[0x7e]	3361	1			T3	13		T4	11		T5	3
valid_sources[0x7f]	3475	1			T3	22		T4	13		T5	2
valid_sources[0x80]	5348	1			T3	11		T4	6		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

247619

1

T1

19

T3

921

T4

661

values[0x0]

all_enables

biggest_size

80685

1

T1

4

T3

243

T4

292

values[0x1]

all_enables

biggest_size

43163

1

T1

5

T3

110

T4

131