Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13663050	14120	0	0
gen_assertions[0].RstEnOn_A	13663050	1076	0	0
gen_assertions[0].RstNOff_A	13663050	14120	0	0
gen_assertions[0].RstNOn_A	13663050	1076	0	0
gen_assertions[1].RstEnOff_A	54650604	12871	0	0
gen_assertions[1].RstEnOn_A	54650604	1064	0	0
gen_assertions[1].RstNOff_A	54650604	12871	0	0
gen_assertions[1].RstNOn_A	54650604	1064	0	0
gen_assertions[2].RstEnOff_A	27326524	12904	0	0
gen_assertions[2].RstEnOn_A	27326524	1044	0	0
gen_assertions[2].RstNOff_A	27326524	12904	0	0
gen_assertions[2].RstNOn_A	27326524	1044	0	0
gen_assertions[3].RstEnOff_A	27326471	12956	0	0
gen_assertions[3].RstEnOn_A	27326471	1084	0	0
gen_assertions[3].RstNOff_A	27326471	12956	0	0
gen_assertions[3].RstNOn_A	27326471	1084	0	0
gen_assertions[4].RstEnOff_A	1724781	22240	0	0
gen_assertions[4].RstEnOn_A	1724781	1140	0	0
gen_assertions[4].RstNOff_A	1724781	22240	0	0
gen_assertions[4].RstNOn_A	1724781	1140	0	0
gen_assertions[5].RstEnOff_A	13663050	14375	0	0
gen_assertions[5].RstEnOn_A	13663050	1191	0	0
gen_assertions[5].RstNOff_A	13663050	14375	0	0
gen_assertions[5].RstNOn_A	13663050	1191	0	0
gen_assertions[6].RstEnOff_A	13663050	14421	0	0
gen_assertions[6].RstEnOn_A	13663050	1231	0	0
gen_assertions[6].RstNOff_A	13663050	14421	0	0
gen_assertions[6].RstNOn_A	13663050	1231	0	0
gen_assertions[7].RstEnOff_A	13663050	14453	0	0
gen_assertions[7].RstEnOn_A	13663050	1272	0	0
gen_assertions[7].RstNOff_A	13663050	14453	0	0
gen_assertions[7].RstNOn_A	13663050	1272	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	14120	0	0
T1	2470	4	0	0
T2	5300	0	0	0
T3	41233	35	0	0
T4	56237	75	0	0
T5	2679	1	0	0
T6	3331	7	0	0
T7	3865	17	0	0
T8	45098	75	0	0
T9	167901	133	0	0
T10	5078	4	0	0
T11	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	1076	0	0
T1	2470	1	0	0
T2	5300	0	0	0
T3	41233	0	0	0
T4	56237	0	0	0
T5	2679	1	0	0
T6	3331	7	0	0
T7	3865	7	0	0
T8	45098	0	0	0
T9	167901	12	0	0
T10	5078	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T34	0	1	0	0
T57	0	10	0	0
T58	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	14120	0	0
T1	2470	4	0	0
T2	5300	0	0	0
T3	41233	35	0	0
T4	56237	75	0	0
T5	2679	1	0	0
T6	3331	7	0	0
T7	3865	17	0	0
T8	45098	75	0	0
T9	167901	133	0	0
T10	5078	4	0	0
T11	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	1076	0	0
T1	2470	1	0	0
T2	5300	0	0	0
T3	41233	0	0	0
T4	56237	0	0	0
T5	2679	1	0	0
T6	3331	7	0	0
T7	3865	7	0	0
T8	45098	0	0	0
T9	167901	12	0	0
T10	5078	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T34	0	1	0	0
T57	0	10	0	0
T58	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54650604	12871	0	0
T1	9880	4	0	0
T2	21206	0	0	0
T3	164929	28	0	0
T4	224938	67	0	0
T5	10721	1	0	0
T6	13330	6	0	0
T7	15467	16	0	0
T8	180383	70	0	0
T9	671607	126	0	0
T10	20319	4	0	0
T11	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54650604	1064	0	0
T5	10721	1	0	0
T6	13330	6	0	0
T7	15467	8	0	0
T8	180383	0	0	0
T9	671607	17	0	0
T10	20319	0	0	0
T11	11121	0	0	0
T12	27829	0	0	0
T22	6836	0	0	0
T33	158317	0	0	0
T42	0	3	0	0
T57	0	7	0	0
T65	0	2	0	0
T66	0	9	0	0
T67	0	6	0	0
T68	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54650604	12871	0	0
T1	9880	4	0	0
T2	21206	0	0	0
T3	164929	28	0	0
T4	224938	67	0	0
T5	10721	1	0	0
T6	13330	6	0	0
T7	15467	16	0	0
T8	180383	70	0	0
T9	671607	126	0	0
T10	20319	4	0	0
T11	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54650604	1064	0	0
T5	10721	1	0	0
T6	13330	6	0	0
T7	15467	8	0	0
T8	180383	0	0	0
T9	671607	17	0	0
T10	20319	0	0	0
T11	11121	0	0	0
T12	27829	0	0	0
T22	6836	0	0	0
T33	158317	0	0	0
T42	0	3	0	0
T57	0	7	0	0
T65	0	2	0	0
T66	0	9	0	0
T67	0	6	0	0
T68	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326524	12904	0	0
T1	4939	4	0	0
T2	10603	0	0	0
T3	82479	28	0	0
T4	112471	67	0	0
T5	5360	3	0	0
T6	6665	8	0	0
T7	7734	16	0	0
T8	90183	70	0	0
T9	335801	125	0	0
T10	10156	4	0	0
T11	0	2	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326524	1044	0	0
T5	5360	3	0	0
T6	6665	8	0	0
T7	7734	0	0	0
T8	90183	0	0	0
T9	335801	15	0	0
T10	10156	0	0	0
T11	5558	0	0	0
T12	13914	0	0	0
T22	3418	0	0	0
T33	791653	0	0	0
T42	0	5	0	0
T57	0	1	0	0
T65	0	1	0	0
T66	0	9	0	0
T67	0	5	0	0
T68	0	6	0	0
T69	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326524	12904	0	0
T1	4939	4	0	0
T2	10603	0	0	0
T3	82479	28	0	0
T4	112471	67	0	0
T5	5360	3	0	0
T6	6665	8	0	0
T7	7734	16	0	0
T8	90183	70	0	0
T9	335801	125	0	0
T10	10156	4	0	0
T11	0	2	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326524	1044	0	0
T5	5360	3	0	0
T6	6665	8	0	0
T7	7734	0	0	0
T8	90183	0	0	0
T9	335801	15	0	0
T10	10156	0	0	0
T11	5558	0	0	0
T12	13914	0	0	0
T22	3418	0	0	0
T33	791653	0	0	0
T42	0	5	0	0
T57	0	1	0	0
T65	0	1	0	0
T66	0	9	0	0
T67	0	5	0	0
T68	0	6	0	0
T69	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326471	12956	0	0
T1	4939	4	0	0
T2	10603	0	0	0
T3	82465	28	0	0
T4	112453	67	0	0
T5	5360	4	0	0
T6	6665	7	0	0
T7	7734	16	0	0
T8	90184	70	0	0
T9	335836	124	0	0
T10	10157	5	0	0
T11	0	3	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326471	1084	0	0
T5	5360	4	0	0
T6	6665	7	0	0
T7	7734	0	0	0
T8	90184	0	0	0
T9	335836	14	0	0
T10	10157	1	0	0
T11	5561	1	0	0
T12	13914	0	0	0
T22	3418	0	0	0
T33	791644	0	0	0
T42	0	6	0	0
T66	0	6	0	0
T67	0	6	0	0
T68	0	7	0	0
T69	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326471	12956	0	0
T1	4939	4	0	0
T2	10603	0	0	0
T3	82465	28	0	0
T4	112453	67	0	0
T5	5360	4	0	0
T6	6665	7	0	0
T7	7734	16	0	0
T8	90184	70	0	0
T9	335836	124	0	0
T10	10157	5	0	0
T11	0	3	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326471	1084	0	0
T5	5360	4	0	0
T6	6665	7	0	0
T7	7734	0	0	0
T8	90184	0	0	0
T9	335836	14	0	0
T10	10157	1	0	0
T11	5561	1	0	0
T12	13914	0	0	0
T22	3418	0	0	0
T33	791644	0	0	0
T42	0	6	0	0
T66	0	6	0	0
T67	0	6	0	0
T68	0	7	0	0
T69	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	22240	0	0
T1	307	5	0	0
T2	662	2	0	0
T3	5230	61	0	0
T4	7043	98	0	0
T5	333	6	0	0
T6	415	8	0	0
T7	481	18	0	0
T8	5652	86	0	0
T9	21190	206	0	0
T10	633	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	1140	0	0
T5	333	5	0	0
T6	415	7	0	0
T7	481	0	0	0
T8	5652	0	0	0
T9	21190	13	0	0
T10	633	0	0	0
T11	346	0	0	0
T12	868	0	0	0
T22	212	0	0	0
T33	49725	0	0	0
T42	0	7	0	0
T59	0	1	0	0
T66	0	8	0	0
T67	0	8	0	0
T68	0	8	0	0
T69	0	1	0	0
T70	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	22240	0	0
T1	307	5	0	0
T2	662	2	0	0
T3	5230	61	0	0
T4	7043	98	0	0
T5	333	6	0	0
T6	415	8	0	0
T7	481	18	0	0
T8	5652	86	0	0
T9	21190	206	0	0
T10	633	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	1140	0	0
T5	333	5	0	0
T6	415	7	0	0
T7	481	0	0	0
T8	5652	0	0	0
T9	21190	13	0	0
T10	633	0	0	0
T11	346	0	0	0
T12	868	0	0	0
T22	212	0	0	0
T33	49725	0	0	0
T42	0	7	0	0
T59	0	1	0	0
T66	0	8	0	0
T67	0	8	0	0
T68	0	8	0	0
T69	0	1	0	0
T70	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	14375	0	0
T1	2470	4	0	0
T2	5300	0	0	0
T3	41233	35	0	0
T4	56237	75	0	0
T5	2679	6	0	0
T6	3331	9	0	0
T7	3865	17	0	0
T8	45098	75	0	0
T9	167901	135	0	0
T10	5078	4	0	0
T11	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	1191	0	0
T5	2679	6	0	0
T6	3331	9	0	0
T7	3865	0	0	0
T8	45098	0	0	0
T9	167901	15	0	0
T10	5078	0	0	0
T11	2782	0	0	0
T12	6956	0	0	0
T22	1708	0	0	0
T33	395823	0	0	0
T42	0	8	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T66	0	9	0	0
T67	0	8	0	0
T71	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	14375	0	0
T1	2470	4	0	0
T2	5300	0	0	0
T3	41233	35	0	0
T4	56237	75	0	0
T5	2679	6	0	0
T6	3331	9	0	0
T7	3865	17	0	0
T8	45098	75	0	0
T9	167901	135	0	0
T10	5078	4	0	0
T11	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	1191	0	0
T5	2679	6	0	0
T6	3331	9	0	0
T7	3865	0	0	0
T8	45098	0	0	0
T9	167901	15	0	0
T10	5078	0	0	0
T11	2782	0	0	0
T12	6956	0	0	0
T22	1708	0	0	0
T33	395823	0	0	0
T42	0	8	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T66	0	9	0	0
T67	0	8	0	0
T71	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	14421	0	0
T1	2470	4	0	0
T2	5300	0	0	0
T3	41233	35	0	0
T4	56237	75	0	0
T5	2679	7	0	0
T6	3331	11	0	0
T7	3865	17	0	0
T8	45098	75	0	0
T9	167901	132	0	0
T10	5078	4	0	0
T11	0	5	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	1231	0	0
T5	2679	7	0	0
T6	3331	11	0	0
T7	3865	0	0	0
T8	45098	0	0	0
T9	167901	12	0	0
T10	5078	0	0	0
T11	2782	1	0	0
T12	6956	0	0	0
T22	1708	0	0	0
T33	395823	0	0	0
T34	0	1	0	0
T42	0	9	0	0
T66	0	8	0	0
T67	0	9	0	0
T68	0	7	0	0
T72	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	14421	0	0
T1	2470	4	0	0
T2	5300	0	0	0
T3	41233	35	0	0
T4	56237	75	0	0
T5	2679	7	0	0
T6	3331	11	0	0
T7	3865	17	0	0
T8	45098	75	0	0
T9	167901	132	0	0
T10	5078	4	0	0
T11	0	5	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	1231	0	0
T5	2679	7	0	0
T6	3331	11	0	0
T7	3865	0	0	0
T8	45098	0	0	0
T9	167901	12	0	0
T10	5078	0	0	0
T11	2782	1	0	0
T12	6956	0	0	0
T22	1708	0	0	0
T33	395823	0	0	0
T34	0	1	0	0
T42	0	9	0	0
T66	0	8	0	0
T67	0	9	0	0
T68	0	7	0	0
T72	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	14453	0	0
T1	2470	4	0	0
T2	5300	0	0	0
T3	41233	35	0	0
T4	56237	75	0	0
T5	2679	8	0	0
T6	3331	14	0	0
T7	3865	17	0	0
T8	45098	75	0	0
T9	167901	134	0	0
T10	5078	5	0	0
T11	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	1272	0	0
T5	2679	8	0	0
T6	3331	14	0	0
T7	3865	0	0	0
T8	45098	0	0	0
T9	167901	14	0	0
T10	5078	1	0	0
T11	2782	0	0	0
T12	6956	0	0	0
T22	1708	0	0	0
T33	395823	0	0	0
T34	0	1	0	0
T42	0	8	0	0
T59	0	1	0	0
T66	0	7	0	0
T67	0	12	0	0
T71	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	14453	0	0
T1	2470	4	0	0
T2	5300	0	0	0
T3	41233	35	0	0
T4	56237	75	0	0
T5	2679	8	0	0
T6	3331	14	0	0
T7	3865	17	0	0
T8	45098	75	0	0
T9	167901	134	0	0
T10	5078	5	0	0
T11	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	1272	0	0
T5	2679	8	0	0
T6	3331	14	0	0
T7	3865	0	0	0
T8	45098	0	0	0
T9	167901	14	0	0
T10	5078	1	0	0
T11	2782	0	0	0
T12	6956	0	0	0
T22	1708	0	0	0
T33	395823	0	0	0
T34	0	1	0	0
T42	0	8	0	0
T59	0	1	0	0
T66	0	7	0	0
T67	0	12	0	0
T71	0	1	0	0