Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12915864	7450	0	0
alert_regwen_rd_A	12915864	7313	0	0
cpu_regwen_rd_A	12915864	7315	0	0
sw_rst_ctrl_n_0_rd_A	12915864	12119	0	0
sw_rst_ctrl_n_1_rd_A	12915864	12037	0	0
sw_rst_ctrl_n_2_rd_A	12915864	12103	0	0
sw_rst_ctrl_n_3_rd_A	12915864	12261	0	0
sw_rst_ctrl_n_4_rd_A	12915864	12252	0	0
sw_rst_ctrl_n_5_rd_A	12915864	12189	0	0
sw_rst_ctrl_n_6_rd_A	12915864	11942	0	0
sw_rst_ctrl_n_7_rd_A	12915864	12019	0	0
sw_rst_regwen_0_rd_A	12915864	7573	0	0
sw_rst_regwen_1_rd_A	12915864	7758	0	0
sw_rst_regwen_2_rd_A	12915864	8045	0	0
sw_rst_regwen_3_rd_A	12915864	7494	0	0
sw_rst_regwen_4_rd_A	12915864	7672	0	0
sw_rst_regwen_5_rd_A	12915864	7679	0	0
sw_rst_regwen_6_rd_A	12915864	7697	0	0
sw_rst_regwen_7_rd_A	12915864	7550	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7450	0	0
T47	9406	2	0	0
T48	2973	256	0	0
T49	4621	530	0	0
T50	3923	12	0	0
T74	2619	4	0	0
T75	2617	25	0	0
T76	9995	373	0	0
T77	5201	19	0	0
T78	5496	248	0	0
T80	3722	50	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7313	0	0
T9	151724	236	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	0	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	215	0	0
T82	0	48	0	0
T86	0	46	0	0
T90	0	58	0	0
T93	0	293	0	0
T115	0	49	0	0
T116	0	69	0	0
T117	0	42	0	0
T118	0	72	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7315	0	0
T9	151724	192	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	0	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	211	0	0
T82	0	53	0	0
T86	0	46	0	0
T90	0	50	0	0
T93	0	298	0	0
T115	0	25	0	0
T116	0	79	0	0
T117	0	46	0	0
T118	0	72	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	12119	0	0
T1	2089	13	0	0
T2	5186	0	0	0
T3	36514	0	0	0
T4	53043	0	0	0
T5	2637	0	0	0
T6	3313	0	0	0
T7	2635	0	0	0
T8	41869	0	0	0
T9	151724	329	0	0
T10	4699	0	0	0
T12	0	66	0	0
T34	0	7	0	0
T68	0	348	0	0
T69	0	3	0	0
T71	0	17	0	0
T82	0	21	0	0
T119	0	17	0	0
T120	0	180	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	12037	0	0
T1	2089	15	0	0
T2	5186	0	0	0
T3	36514	0	0	0
T4	53043	0	0	0
T5	2637	0	0	0
T6	3313	0	0	0
T7	2635	0	0	0
T8	41869	0	0	0
T9	151724	416	0	0
T10	4699	0	0	0
T12	0	63	0	0
T34	0	10	0	0
T68	0	323	0	0
T69	0	7	0	0
T71	0	16	0	0
T82	0	26	0	0
T119	0	14	0	0
T120	0	155	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	12103	0	0
T9	151724	365	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	81	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	0	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	292	0	0
T69	0	14	0	0
T71	0	15	0	0
T82	0	58	0	0
T86	0	59	0	0
T119	0	10	0	0
T120	0	232	0	0
T121	0	136	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	12261	0	0
T1	2089	6	0	0
T2	5186	0	0	0
T3	36514	0	0	0
T4	53043	0	0	0
T5	2637	0	0	0
T6	3313	0	0	0
T7	2635	0	0	0
T8	41869	0	0	0
T9	151724	342	0	0
T10	4699	0	0	0
T12	0	64	0	0
T34	0	10	0	0
T68	0	292	0	0
T69	0	18	0	0
T71	0	10	0	0
T82	0	43	0	0
T119	0	13	0	0
T120	0	197	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	12252	0	0
T1	2089	12	0	0
T2	5186	0	0	0
T3	36514	0	0	0
T4	53043	0	0	0
T5	2637	0	0	0
T6	3313	0	0	0
T7	2635	0	0	0
T8	41869	0	0	0
T9	151724	394	0	0
T10	4699	0	0	0
T12	0	70	0	0
T34	0	5	0	0
T68	0	298	0	0
T69	0	18	0	0
T71	0	16	0	0
T82	0	29	0	0
T119	0	4	0	0
T120	0	207	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	12189	0	0
T1	2089	13	0	0
T2	5186	0	0	0
T3	36514	0	0	0
T4	53043	0	0	0
T5	2637	0	0	0
T6	3313	0	0	0
T7	2635	0	0	0
T8	41869	0	0	0
T9	151724	365	0	0
T10	4699	0	0	0
T12	0	47	0	0
T34	0	11	0	0
T68	0	247	0	0
T69	0	4	0	0
T71	0	13	0	0
T82	0	68	0	0
T119	0	10	0	0
T120	0	185	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	11942	0	0
T1	2089	5	0	0
T2	5186	0	0	0
T3	36514	0	0	0
T4	53043	0	0	0
T5	2637	0	0	0
T6	3313	0	0	0
T7	2635	0	0	0
T8	41869	0	0	0
T9	151724	392	0	0
T10	4699	0	0	0
T12	0	70	0	0
T34	0	14	0	0
T68	0	307	0	0
T69	0	14	0	0
T71	0	14	0	0
T82	0	34	0	0
T119	0	6	0	0
T120	0	184	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	12019	0	0
T1	2089	5	0	0
T2	5186	0	0	0
T3	36514	0	0	0
T4	53043	0	0	0
T5	2637	0	0	0
T6	3313	0	0	0
T7	2635	0	0	0
T8	41869	0	0	0
T9	151724	377	0	0
T10	4699	0	0	0
T12	0	67	0	0
T68	0	322	0	0
T69	0	11	0	0
T71	0	5	0	0
T82	0	17	0	0
T86	0	45	0	0
T119	0	11	0	0
T120	0	218	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7573	0	0
T9	151724	217	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	15	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	202	0	0
T69	0	7	0	0
T71	0	7	0	0
T82	0	34	0	0
T86	0	38	0	0
T90	0	53	0	0
T119	0	10	0	0
T120	0	29	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7758	0	0
T9	151724	248	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	0	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	216	0	0
T69	0	12	0	0
T71	0	2	0	0
T82	0	52	0	0
T86	0	58	0	0
T90	0	57	0	0
T119	0	5	0	0
T120	0	28	0	0
T122	0	25	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	8045	0	0
T9	151724	228	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	5	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	244	0	0
T69	0	12	0	0
T71	0	9	0	0
T82	0	50	0	0
T86	0	26	0	0
T90	0	46	0	0
T119	0	6	0	0
T120	0	26	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7494	0	0
T9	151724	171	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	6	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	234	0	0
T69	0	12	0	0
T71	0	8	0	0
T82	0	47	0	0
T86	0	54	0	0
T90	0	54	0	0
T119	0	13	0	0
T120	0	29	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7672	0	0
T9	151724	219	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	14	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	233	0	0
T69	0	4	0	0
T71	0	11	0	0
T82	0	23	0	0
T86	0	42	0	0
T90	0	53	0	0
T119	0	4	0	0
T120	0	30	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7679	0	0
T9	151724	203	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	4	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	227	0	0
T69	0	4	0	0
T71	0	13	0	0
T82	0	29	0	0
T86	0	49	0	0
T90	0	59	0	0
T119	0	5	0	0
T120	0	17	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7697	0	0
T9	151724	191	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	2	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	185	0	0
T69	0	5	0	0
T71	0	8	0	0
T82	0	49	0	0
T86	0	27	0	0
T90	0	43	0	0
T119	0	4	0	0
T120	0	33	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12915864	7550	0	0
T9	151724	199	0	0
T10	4699	0	0	0
T11	2537	0	0	0
T12	5447	0	0	0
T22	1666	0	0	0
T23	26006	0	0	0
T33	345867	0	0	0
T34	5489	4	0	0
T35	1875	0	0	0
T57	2421	0	0	0
T68	0	210	0	0
T69	0	3	0	0
T71	0	3	0	0
T82	0	32	0	0
T86	0	39	0	0
T90	0	67	0	0
T119	0	2	0	0
T120	0	33	0	0