Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T3,T9,T34
1	0	Covered	T3,T9,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56929631	9245	0	0
CascadeEffAonToRstPorAboveRise_A	56929631	9245	0	0
CascadeEffAonToRstPorIoAboveFall_A	54650604	9245	0	0
CascadeEffAonToRstPorIoAboveRise_A	54650604	9245	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27326524	9245	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27326524	9245	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13663050	9245	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13663050	9245	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27326471	9245	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27326471	9245	0	0
CascadeLcToLcAboveFall_A	56929631	22478	0	0
CascadeLcToLcAboveRise_A	56929631	22478	0	0
CascadeLcToLcAonAboveFall_A	1724781	22478	0	0
CascadeLcToLcAonAboveRise_A	1724781	22478	0	0
CascadeLcToLcShadowedAboveFall_A	56929631	22478	0	0
CascadeLcToLcShadowedAboveRise_A	56929631	22478	0	0
CascadePorToAonAboveFall_A	1724781	7395	0	0
CascadeSysToSysAboveFall_A	56929631	22478	0	0
CascadeSysToSysAboveRise_A	56929631	22478	0	0
ScanRstToAonRise_A	1724781	242	0	0
StablePorToAonRise_A	1724781	9245	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12154712	22478	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12154712	22478	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12154712	22478	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12154712	22478	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13663050	22478	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13663050	22478	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12154712	22478	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12154712	22478	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12154712	22478	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12154712	22478	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56929631	9245	0	0
T1	10293	1	0	0
T2	22091	2	0	0
T3	171795	26	0	0
T4	234306	27	0	0
T5	11169	1	0	0
T6	13885	1	0	0
T7	16112	1	0	0
T8	187910	27	0	0
T9	699614	74	0	0
T10	21164	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56929631	9245	0	0
T1	10293	1	0	0
T2	22091	2	0	0
T3	171795	26	0	0
T4	234306	27	0	0
T5	11169	1	0	0
T6	13885	1	0	0
T7	16112	1	0	0
T8	187910	27	0	0
T9	699614	74	0	0
T10	21164	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54650604	9245	0	0
T1	9880	1	0	0
T2	21206	2	0	0
T3	164929	26	0	0
T4	224938	27	0	0
T5	10721	1	0	0
T6	13330	1	0	0
T7	15467	1	0	0
T8	180383	27	0	0
T9	671607	74	0	0
T10	20319	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54650604	9245	0	0
T1	9880	1	0	0
T2	21206	2	0	0
T3	164929	26	0	0
T4	224938	27	0	0
T5	10721	1	0	0
T6	13330	1	0	0
T7	15467	1	0	0
T8	180383	27	0	0
T9	671607	74	0	0
T10	20319	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326524	9245	0	0
T1	4939	1	0	0
T2	10603	2	0	0
T3	82479	26	0	0
T4	112471	27	0	0
T5	5360	1	0	0
T6	6665	1	0	0
T7	7734	1	0	0
T8	90183	27	0	0
T9	335801	74	0	0
T10	10156	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326524	9245	0	0
T1	4939	1	0	0
T2	10603	2	0	0
T3	82479	26	0	0
T4	112471	27	0	0
T5	5360	1	0	0
T6	6665	1	0	0
T7	7734	1	0	0
T8	90183	27	0	0
T9	335801	74	0	0
T10	10156	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	9245	0	0
T1	2470	1	0	0
T2	5300	2	0	0
T3	41233	26	0	0
T4	56237	27	0	0
T5	2679	1	0	0
T6	3331	1	0	0
T7	3865	1	0	0
T8	45098	27	0	0
T9	167901	74	0	0
T10	5078	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	9245	0	0
T1	2470	1	0	0
T2	5300	2	0	0
T3	41233	26	0	0
T4	56237	27	0	0
T5	2679	1	0	0
T6	3331	1	0	0
T7	3865	1	0	0
T8	45098	27	0	0
T9	167901	74	0	0
T10	5078	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326471	9245	0	0
T1	4939	1	0	0
T2	10603	2	0	0
T3	82465	26	0	0
T4	112453	27	0	0
T5	5360	1	0	0
T6	6665	1	0	0
T7	7734	1	0	0
T8	90184	27	0	0
T9	335836	74	0	0
T10	10157	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27326471	9245	0	0
T1	4939	1	0	0
T2	10603	2	0	0
T3	82465	26	0	0
T4	112453	27	0	0
T5	5360	1	0	0
T6	6665	1	0	0
T7	7734	1	0	0
T8	90184	27	0	0
T9	335836	74	0	0
T10	10157	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56929631	22478	0	0
T1	10293	5	0	0
T2	22091	2	0	0
T3	171795	61	0	0
T4	234306	102	0	0
T5	11169	1	0	0
T6	13885	1	0	0
T7	16112	18	0	0
T8	187910	102	0	0
T9	699614	195	0	0
T10	21164	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56929631	22478	0	0
T1	10293	5	0	0
T2	22091	2	0	0
T3	171795	61	0	0
T4	234306	102	0	0
T5	11169	1	0	0
T6	13885	1	0	0
T7	16112	18	0	0
T8	187910	102	0	0
T9	699614	195	0	0
T10	21164	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	22478	0	0
T1	307	5	0	0
T2	662	2	0	0
T3	5230	61	0	0
T4	7043	102	0	0
T5	333	1	0	0
T6	415	1	0	0
T7	481	18	0	0
T8	5652	102	0	0
T9	21190	195	0	0
T10	633	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	22478	0	0
T1	307	5	0	0
T2	662	2	0	0
T3	5230	61	0	0
T4	7043	102	0	0
T5	333	1	0	0
T6	415	1	0	0
T7	481	18	0	0
T8	5652	102	0	0
T9	21190	195	0	0
T10	633	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56929631	22478	0	0
T1	10293	5	0	0
T2	22091	2	0	0
T3	171795	61	0	0
T4	234306	102	0	0
T5	11169	1	0	0
T6	13885	1	0	0
T7	16112	18	0	0
T8	187910	102	0	0
T9	699614	195	0	0
T10	21164	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56929631	22478	0	0
T1	10293	5	0	0
T2	22091	2	0	0
T3	171795	61	0	0
T4	234306	102	0	0
T5	11169	1	0	0
T6	13885	1	0	0
T7	16112	18	0	0
T8	187910	102	0	0
T9	699614	195	0	0
T10	21164	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	7395	0	0
T1	307	1	0	0
T2	662	21	0	0
T3	5230	14	0	0
T4	7043	27	0	0
T5	333	1	0	0
T6	415	1	0	0
T7	481	1	0	0
T8	5652	27	0	0
T9	21190	39	0	0
T10	633	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56929631	22478	0	0
T1	10293	5	0	0
T2	22091	2	0	0
T3	171795	61	0	0
T4	234306	102	0	0
T5	11169	1	0	0
T6	13885	1	0	0
T7	16112	18	0	0
T8	187910	102	0	0
T9	699614	195	0	0
T10	21164	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56929631	22478	0	0
T1	10293	5	0	0
T2	22091	2	0	0
T3	171795	61	0	0
T4	234306	102	0	0
T5	11169	1	0	0
T6	13885	1	0	0
T7	16112	18	0	0
T8	187910	102	0	0
T9	699614	195	0	0
T10	21164	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	242	0	0
T3	5230	3	0	0
T4	7043	0	0	0
T5	333	0	0	0
T6	415	0	0	0
T7	481	0	0	0
T8	5652	0	0	0
T9	21190	2	0	0
T10	633	0	0	0
T11	346	0	0	0
T22	212	0	0	0
T34	0	1	0	0
T66	0	6	0	0
T68	0	2	0	0
T73	0	2	0	0
T82	0	1	0	0
T83	0	3	0	0
T84	0	8	0	0
T85	0	5	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1724781	9245	0	0
T1	307	1	0	0
T2	662	2	0	0
T3	5230	26	0	0
T4	7043	27	0	0
T5	333	1	0	0
T6	415	1	0	0
T7	481	1	0	0
T8	5652	27	0	0
T9	21190	74	0	0
T10	633	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12154712	22478	0	0
T1	2089	5	0	0
T2	5186	2	0	0
T3	36514	61	0	0
T4	53043	102	0	0
T5	2637	1	0	0
T6	3313	1	0	0
T7	2635	18	0	0
T8	41869	102	0	0
T9	151724	195	0	0
T10	4699	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12154712	22478	0	0
T1	2089	5	0	0
T2	5186	2	0	0
T3	36514	61	0	0
T4	53043	102	0	0
T5	2637	1	0	0
T6	3313	1	0	0
T7	2635	18	0	0
T8	41869	102	0	0
T9	151724	195	0	0
T10	4699	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12154712	22478	0	0
T1	2089	5	0	0
T2	5186	2	0	0
T3	36514	61	0	0
T4	53043	102	0	0
T5	2637	1	0	0
T6	3313	1	0	0
T7	2635	18	0	0
T8	41869	102	0	0
T9	151724	195	0	0
T10	4699	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12154712	22478	0	0
T1	2089	5	0	0
T2	5186	2	0	0
T3	36514	61	0	0
T4	53043	102	0	0
T5	2637	1	0	0
T6	3313	1	0	0
T7	2635	18	0	0
T8	41869	102	0	0
T9	151724	195	0	0
T10	4699	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	22478	0	0
T1	2470	5	0	0
T2	5300	2	0	0
T3	41233	61	0	0
T4	56237	102	0	0
T5	2679	1	0	0
T6	3331	1	0	0
T7	3865	18	0	0
T8	45098	102	0	0
T9	167901	195	0	0
T10	5078	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13663050	22478	0	0
T1	2470	5	0	0
T2	5300	2	0	0
T3	41233	61	0	0
T4	56237	102	0	0
T5	2679	1	0	0
T6	3331	1	0	0
T7	3865	18	0	0
T8	45098	102	0	0
T9	167901	195	0	0
T10	5078	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12154712	22478	0	0
T1	2089	5	0	0
T2	5186	2	0	0
T3	36514	61	0	0
T4	53043	102	0	0
T5	2637	1	0	0
T6	3313	1	0	0
T7	2635	18	0	0
T8	41869	102	0	0
T9	151724	195	0	0
T10	4699	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12154712	22478	0	0
T1	2089	5	0	0
T2	5186	2	0	0
T3	36514	61	0	0
T4	53043	102	0	0
T5	2637	1	0	0
T6	3313	1	0	0
T7	2635	18	0	0
T8	41869	102	0	0
T9	151724	195	0	0
T10	4699	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12154712	22478	0	0
T1	2089	5	0	0
T2	5186	2	0	0
T3	36514	61	0	0
T4	53043	102	0	0
T5	2637	1	0	0
T6	3313	1	0	0
T7	2635	18	0	0
T8	41869	102	0	0
T9	151724	195	0	0
T10	4699	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12154712	22478	0	0
T1	2089	5	0	0
T2	5186	2	0	0
T3	36514	61	0	0
T4	53043	102	0	0
T5	2637	1	0	0
T6	3313	1	0	0
T7	2635	18	0	0
T8	41869	102	0	0
T9	151724	195	0	0
T10	4699	6	0	0