Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	666559	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

397552

1

T1

87

T3

1160

T4

1104

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	568914	1			T1	128		T2	1		T3	1738
values[0x0]	247152	1			T1	58		T3	702		T4	824
values[0x1]	248045	1			T1	80		T3	682		T4	876

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	558974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

505137

1

T1

106

T3

1462

T4

1447

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3932	1			T3	10		T5	12		T7	12
valid_sources[0x01]	3864	1			T3	12		T4	1		T6	1
valid_sources[0x02]	4316	1			T3	6		T4	13		T6	2
valid_sources[0x03]	3538	1			T3	16		T4	9		T5	1
valid_sources[0x04]	3289	1			T3	9		T5	10		T6	1
valid_sources[0x05]	3292	1			T3	8		T5	4		T6	2
valid_sources[0x06]	3650	1			T3	13		T5	7		T6	1
valid_sources[0x07]	3849	1			T3	16		T4	6		T5	3
valid_sources[0x08]	3408	1			T3	11		T4	13		T5	2
valid_sources[0x09]	3296	1			T3	13		T4	21		T7	15
valid_sources[0x0a]	4452	1			T3	11		T4	10		T5	5
valid_sources[0x0b]	3515	1			T3	5		T4	4		T5	5
valid_sources[0x0c]	4633	1			T3	18		T4	2		T5	8
valid_sources[0x0d]	4840	1			T3	3		T4	30		T5	2
valid_sources[0x0e]	3333	1			T3	8		T4	32		T7	15
valid_sources[0x0f]	4650	1			T3	17		T4	32		T5	2
valid_sources[0x10]	4268	1			T3	23		T4	4		T5	3
valid_sources[0x11]	3788	1			T2	1		T3	9		T5	2
valid_sources[0x12]	4584	1			T3	10		T5	2		T6	1
valid_sources[0x13]	5340	1			T3	17		T4	12		T5	2
valid_sources[0x14]	4166	1			T3	15		T4	20		T5	3
valid_sources[0x15]	7385	1			T3	10		T6	3		T7	7
valid_sources[0x16]	4241	1			T3	5		T4	42		T5	4
valid_sources[0x17]	6336	1			T3	12		T5	5		T6	2
valid_sources[0x18]	5497	1			T3	20		T4	28		T5	2
valid_sources[0x19]	3277	1			T3	6		T4	24		T5	1
valid_sources[0x1a]	4661	1			T3	16		T4	36		T5	3
valid_sources[0x1b]	5099	1			T3	10		T4	27		T5	8
valid_sources[0x1c]	4452	1			T3	6		T5	4		T6	1
valid_sources[0x1d]	4943	1			T3	26		T5	3		T7	10
valid_sources[0x1e]	3047	1			T3	15		T5	4		T6	2
valid_sources[0x1f]	3692	1			T3	14		T6	2		T7	15
valid_sources[0x20]	5370	1			T3	14		T5	6		T6	1
valid_sources[0x21]	4547	1			T3	5		T5	7		T6	1
valid_sources[0x22]	4613	1			T3	14		T4	7		T5	2
valid_sources[0x23]	4288	1			T3	16		T5	1		T7	10
valid_sources[0x24]	4769	1			T3	8		T5	1		T6	1
valid_sources[0x25]	4002	1			T3	9		T5	1		T6	2
valid_sources[0x26]	3753	1			T3	8		T4	7		T5	1
valid_sources[0x27]	3160	1			T3	21		T5	7		T7	6
valid_sources[0x28]	3872	1			T3	12		T5	2		T6	2
valid_sources[0x29]	3907	1			T3	18		T4	15		T5	8
valid_sources[0x2a]	4877	1			T3	7		T5	1		T7	11
valid_sources[0x2b]	4029	1			T3	5		T4	5		T5	4
valid_sources[0x2c]	4841	1			T3	14		T4	12		T5	9
valid_sources[0x2d]	4303	1			T3	16		T4	19		T5	4
valid_sources[0x2e]	4650	1			T3	15		T4	29		T5	6
valid_sources[0x2f]	3826	1			T3	6		T5	4		T6	1
valid_sources[0x30]	3295	1			T3	6		T4	4		T5	4
valid_sources[0x31]	3999	1			T3	7		T4	2		T5	1
valid_sources[0x32]	3588	1			T3	15		T5	6		T7	16
valid_sources[0x33]	4129	1			T3	5		T5	8		T6	3
valid_sources[0x34]	4906	1			T3	6		T4	15		T5	2
valid_sources[0x35]	3628	1			T3	9		T4	3		T5	3
valid_sources[0x36]	3492	1			T3	12		T5	4		T7	19
valid_sources[0x37]	4461	1			T3	23		T4	4		T5	1
valid_sources[0x38]	4147	1			T3	4		T4	28		T6	2
valid_sources[0x39]	2858	1			T3	12		T4	5		T5	1
valid_sources[0x3a]	4069	1			T3	14		T5	6		T7	12
valid_sources[0x3b]	4462	1			T3	7		T5	1		T7	9
valid_sources[0x3c]	4285	1			T3	9		T5	6		T7	13
valid_sources[0x3d]	3422	1			T3	20		T7	9		T8	13
valid_sources[0x3e]	4588	1			T3	3		T5	1		T6	1
valid_sources[0x3f]	3361	1			T3	14		T4	90		T5	11
valid_sources[0x40]	3716	1			T3	16		T4	19		T5	1
valid_sources[0x41]	4688	1			T3	4		T4	31		T5	3
valid_sources[0x42]	3232	1			T3	16		T4	12		T5	8
valid_sources[0x43]	3111	1			T3	13		T4	7		T5	1
valid_sources[0x44]	4698	1			T3	9		T5	4		T6	4
valid_sources[0x45]	3538	1			T3	8		T4	24		T5	6
valid_sources[0x46]	3619	1			T3	4		T4	9		T5	3
valid_sources[0x47]	4240	1			T3	14		T4	5		T5	7
valid_sources[0x48]	3480	1			T3	11		T5	7		T6	1
valid_sources[0x49]	6357	1			T3	12		T4	4		T5	8
valid_sources[0x4a]	3803	1			T3	18		T4	51		T5	2
valid_sources[0x4b]	4498	1			T3	23		T5	1		T7	11
valid_sources[0x4c]	3775	1			T3	17		T5	5		T6	1
valid_sources[0x4d]	4150	1			T3	13		T4	10		T5	1
valid_sources[0x4e]	3972	1			T3	12		T4	10		T5	3
valid_sources[0x4f]	4422	1			T3	20		T5	1		T7	18
valid_sources[0x50]	3743	1			T3	12		T4	8		T5	8
valid_sources[0x51]	4042	1			T3	10		T5	4		T7	18
valid_sources[0x52]	3527	1			T3	8		T4	36		T6	2
valid_sources[0x53]	4319	1			T3	8		T4	21		T5	5
valid_sources[0x54]	3194	1			T3	9		T5	11		T7	15
valid_sources[0x55]	3658	1			T3	8		T5	4		T6	1
valid_sources[0x56]	4864	1			T3	21		T5	1		T6	1
valid_sources[0x57]	3989	1			T3	18		T4	35		T5	5
valid_sources[0x58]	3440	1			T3	20		T4	30		T5	5
valid_sources[0x59]	3963	1			T3	4		T4	20		T6	2
valid_sources[0x5a]	4949	1			T3	14		T5	13		T6	1
valid_sources[0x5b]	4394	1			T3	5		T4	16		T5	6
valid_sources[0x5c]	4355	1			T3	11		T5	6		T6	1
valid_sources[0x5d]	4608	1			T3	5		T4	1		T5	7
valid_sources[0x5e]	4431	1			T3	8		T4	14		T6	1
valid_sources[0x5f]	2902	1			T3	11		T4	26		T5	3
valid_sources[0x60]	3602	1			T3	12		T7	18		T8	14
valid_sources[0x61]	4890	1			T3	14		T4	6		T5	6
valid_sources[0x62]	3234	1			T3	15		T5	3		T6	1
valid_sources[0x63]	3757	1			T3	16		T4	5		T5	9
valid_sources[0x64]	4208	1			T3	20		T4	12		T5	3
valid_sources[0x65]	4019	1			T3	7		T5	7		T6	1
valid_sources[0x66]	4219	1			T3	18		T4	9		T5	6
valid_sources[0x67]	3575	1			T3	15		T4	35		T5	4
valid_sources[0x68]	3249	1			T3	11		T4	53		T5	10
valid_sources[0x69]	3810	1			T3	8		T4	15		T5	3
valid_sources[0x6a]	3697	1			T3	18		T5	1		T6	1
valid_sources[0x6b]	4200	1			T3	10		T4	7		T7	12
valid_sources[0x6c]	3857	1			T3	17		T5	2		T6	1
valid_sources[0x6d]	3387	1			T3	9		T4	21		T7	12
valid_sources[0x6e]	3850	1			T3	7		T4	6		T5	5
valid_sources[0x6f]	3766	1			T3	4		T4	14		T5	5
valid_sources[0x70]	4910	1			T3	14		T4	8		T5	9
valid_sources[0x71]	3882	1			T3	15		T4	7		T5	2
valid_sources[0x72]	4442	1			T3	10		T4	24		T5	2
valid_sources[0x73]	4685	1			T3	24		T4	92		T5	2
valid_sources[0x74]	3509	1			T3	22		T4	24		T5	1
valid_sources[0x75]	4960	1			T3	9		T5	5		T6	2
valid_sources[0x76]	3615	1			T3	13		T4	6		T5	2
valid_sources[0x77]	3379	1			T3	14		T5	7		T7	11
valid_sources[0x78]	4007	1			T3	5		T5	1		T6	2
valid_sources[0x79]	5605	1			T3	8		T4	25		T5	8
valid_sources[0x7a]	3584	1			T3	12		T5	2		T6	1
valid_sources[0x7b]	5412	1			T3	22		T4	22		T5	5
valid_sources[0x7c]	3564	1			T3	10		T5	8		T7	10
valid_sources[0x7d]	3686	1			T3	9		T5	1		T7	7
valid_sources[0x7e]	5193	1			T3	9		T4	109		T5	7
valid_sources[0x7f]	4231	1			T3	16		T5	4		T6	2
valid_sources[0x80]	2987	1			T3	5		T5	3		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

266499

1

T1

61

T3

818

T4

681

values[0x0]

all_enables

biggest_size

85619

1

T1

16

T3

225

T4

280

values[0x1]

all_enables

biggest_size

45434

1

T1

10

T3

117

T4

143