Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T21
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T21,T29
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T21,T29
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T21,T29
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T21,T29
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T21,T29
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	15272062	15077	0	0
gen_assertions[0].RstEnOn_A	15272062	1209	0	0
gen_assertions[0].RstNOff_A	15272062	15077	0	0
gen_assertions[0].RstNOn_A	15272062	1209	0	0
gen_assertions[1].RstEnOff_A	61087654	13684	0	0
gen_assertions[1].RstEnOn_A	61087654	1176	0	0
gen_assertions[1].RstNOff_A	61087654	13684	0	0
gen_assertions[1].RstNOn_A	61087654	1176	0	0
gen_assertions[2].RstEnOff_A	30545038	13726	0	0
gen_assertions[2].RstEnOn_A	30545038	1161	0	0
gen_assertions[2].RstNOff_A	30545038	13726	0	0
gen_assertions[2].RstNOn_A	30545038	1161	0	0
gen_assertions[3].RstEnOff_A	30544745	13746	0	0
gen_assertions[3].RstEnOn_A	30544745	1184	0	0
gen_assertions[3].RstNOff_A	30544745	13746	0	0
gen_assertions[3].RstNOn_A	30544745	1184	0	0
gen_assertions[4].RstEnOff_A	1927857	23818	0	0
gen_assertions[4].RstEnOn_A	1927857	1226	0	0
gen_assertions[4].RstNOff_A	1927857	23818	0	0
gen_assertions[4].RstNOn_A	1927857	1226	0	0
gen_assertions[5].RstEnOff_A	15272062	15301	0	0
gen_assertions[5].RstEnOn_A	15272062	1286	0	0
gen_assertions[5].RstNOff_A	15272062	15301	0	0
gen_assertions[5].RstNOn_A	15272062	1286	0	0
gen_assertions[6].RstEnOff_A	15272062	15381	0	0
gen_assertions[6].RstEnOn_A	15272062	1376	0	0
gen_assertions[6].RstNOff_A	15272062	15381	0	0
gen_assertions[6].RstNOn_A	15272062	1376	0	0
gen_assertions[7].RstEnOff_A	15272062	15436	0	0
gen_assertions[7].RstEnOn_A	15272062	1422	0	0
gen_assertions[7].RstNOff_A	15272062	15436	0	0
gen_assertions[7].RstNOn_A	15272062	1422	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	15077	0	0
T1	3113	13	0	0
T2	4105	0	0	0
T3	44472	42	0	0
T4	29168	75	0	0
T5	11917	6	0	0
T6	4383	14	0	0
T7	45775	75	0	0
T8	29141	75	0	0
T9	36757	33	0	0
T10	2981	4	0	0
T11	0	27	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	1209	0	0
T1	3113	8	0	0
T2	4105	0	0	0
T3	44472	0	0	0
T4	29168	0	0	0
T5	11917	6	0	0
T6	4383	3	0	0
T7	45775	0	0	0
T8	29141	0	0	0
T9	36757	0	0	0
T10	2981	0	0	0
T21	0	24	0	0
T29	0	5	0	0
T33	0	4	0	0
T53	0	1	0	0
T68	0	2	0	0
T69	0	21	0	0
T71	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	15077	0	0
T1	3113	13	0	0
T2	4105	0	0	0
T3	44472	42	0	0
T4	29168	75	0	0
T5	11917	6	0	0
T6	4383	14	0	0
T7	45775	75	0	0
T8	29141	75	0	0
T9	36757	33	0	0
T10	2981	4	0	0
T11	0	27	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	1209	0	0
T1	3113	8	0	0
T2	4105	0	0	0
T3	44472	0	0	0
T4	29168	0	0	0
T5	11917	6	0	0
T6	4383	3	0	0
T7	45775	0	0	0
T8	29141	0	0	0
T9	36757	0	0	0
T10	2981	0	0	0
T21	0	24	0	0
T29	0	5	0	0
T33	0	4	0	0
T53	0	1	0	0
T68	0	2	0	0
T69	0	21	0	0
T71	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61087654	13684	0	0
T1	12457	13	0	0
T2	16421	0	0	0
T3	177865	37	0	0
T4	116646	65	0	0
T5	47670	6	0	0
T6	17533	12	0	0
T7	183072	65	0	0
T8	116571	68	0	0
T9	147039	32	0	0
T10	11933	5	0	0
T11	0	26	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61087654	1176	0	0
T1	12457	4	0	0
T2	16421	0	0	0
T3	177865	0	0	0
T4	116646	0	0	0
T5	47670	6	0	0
T6	17533	0	0	0
T7	183072	0	0	0
T8	116571	0	0	0
T9	147039	0	0	0
T10	11933	1	0	0
T21	0	20	0	0
T29	0	6	0	0
T48	0	6	0	0
T69	0	27	0	0
T94	0	25	0	0
T95	0	1	0	0
T96	0	20	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61087654	13684	0	0
T1	12457	13	0	0
T2	16421	0	0	0
T3	177865	37	0	0
T4	116646	65	0	0
T5	47670	6	0	0
T6	17533	12	0	0
T7	183072	65	0	0
T8	116571	68	0	0
T9	147039	32	0	0
T10	11933	5	0	0
T11	0	26	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61087654	1176	0	0
T1	12457	4	0	0
T2	16421	0	0	0
T3	177865	0	0	0
T4	116646	0	0	0
T5	47670	6	0	0
T6	17533	0	0	0
T7	183072	0	0	0
T8	116571	0	0	0
T9	147039	0	0	0
T10	11933	1	0	0
T21	0	20	0	0
T29	0	6	0	0
T48	0	6	0	0
T69	0	27	0	0
T94	0	25	0	0
T95	0	1	0	0
T96	0	20	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30545038	13726	0	0
T1	6228	13	0	0
T2	8211	0	0	0
T3	88939	37	0	0
T4	58323	65	0	0
T5	23834	6	0	0
T6	8766	12	0	0
T7	91545	65	0	0
T8	58272	68	0	0
T9	73521	32	0	0
T10	5963	5	0	0
T11	0	26	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30545038	1161	0	0
T5	23834	6	0	0
T6	8766	0	0	0
T7	91545	0	0	0
T8	58272	0	0	0
T9	73521	0	0	0
T10	5963	1	0	0
T11	36352	0	0	0
T21	246154	21	0	0
T29	16645	8	0	0
T33	12306	0	0	0
T48	0	5	0	0
T53	0	1	0	0
T69	0	18	0	0
T94	0	25	0	0
T95	0	3	0	0
T96	0	19	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30545038	13726	0	0
T1	6228	13	0	0
T2	8211	0	0	0
T3	88939	37	0	0
T4	58323	65	0	0
T5	23834	6	0	0
T6	8766	12	0	0
T7	91545	65	0	0
T8	58272	68	0	0
T9	73521	32	0	0
T10	5963	5	0	0
T11	0	26	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30545038	1161	0	0
T5	23834	6	0	0
T6	8766	0	0	0
T7	91545	0	0	0
T8	58272	0	0	0
T9	73521	0	0	0
T10	5963	1	0	0
T11	36352	0	0	0
T21	246154	21	0	0
T29	16645	8	0	0
T33	12306	0	0	0
T48	0	5	0	0
T53	0	1	0	0
T69	0	18	0	0
T94	0	25	0	0
T95	0	3	0	0
T96	0	19	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30544745	13746	0	0
T1	6228	13	0	0
T2	8211	0	0	0
T3	88937	37	0	0
T4	58342	65	0	0
T5	23834	9	0	0
T6	8767	12	0	0
T7	91547	65	0	0
T8	58269	68	0	0
T9	73519	32	0	0
T10	5966	4	0	0
T11	0	26	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30544745	1184	0	0
T5	23834	9	0	0
T6	8767	0	0	0
T7	91547	0	0	0
T8	58269	0	0	0
T9	73519	0	0	0
T10	5966	0	0	0
T11	36348	0	0	0
T21	246139	19	0	0
T29	16645	9	0	0
T33	12306	0	0	0
T48	0	9	0	0
T69	0	25	0	0
T94	0	26	0	0
T95	0	5	0	0
T96	0	23	0	0
T97	0	1	0	0
T98	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30544745	13746	0	0
T1	6228	13	0	0
T2	8211	0	0	0
T3	88937	37	0	0
T4	58342	65	0	0
T5	23834	9	0	0
T6	8767	12	0	0
T7	91547	65	0	0
T8	58269	68	0	0
T9	73519	32	0	0
T10	5966	4	0	0
T11	0	26	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30544745	1184	0	0
T5	23834	9	0	0
T6	8767	0	0	0
T7	91547	0	0	0
T8	58269	0	0	0
T9	73519	0	0	0
T10	5966	0	0	0
T11	36348	0	0	0
T21	246139	19	0	0
T29	16645	9	0	0
T33	12306	0	0	0
T48	0	9	0	0
T69	0	25	0	0
T94	0	26	0	0
T95	0	5	0	0
T96	0	23	0	0
T97	0	1	0	0
T98	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	23818	0	0
T1	388	14	0	0
T2	512	2	0	0
T3	5640	61	0	0
T4	3659	73	0	0
T5	1489	10	0	0
T6	547	15	0	0
T7	5736	86	0	0
T8	3657	76	0	0
T9	4656	49	0	0
T10	371	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	1226	0	0
T5	1489	9	0	0
T6	547	0	0	0
T7	5736	0	0	0
T8	3657	0	0	0
T9	4656	0	0	0
T10	371	0	0	0
T11	2313	0	0	0
T21	15782	18	0	0
T29	1039	9	0	0
T33	767	0	0	0
T48	0	8	0	0
T53	0	1	0	0
T69	0	21	0	0
T94	0	23	0	0
T95	0	5	0	0
T96	0	19	0	0
T98	0	9	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	23818	0	0
T1	388	14	0	0
T2	512	2	0	0
T3	5640	61	0	0
T4	3659	73	0	0
T5	1489	10	0	0
T6	547	15	0	0
T7	5736	86	0	0
T8	3657	76	0	0
T9	4656	49	0	0
T10	371	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	1226	0	0
T5	1489	9	0	0
T6	547	0	0	0
T7	5736	0	0	0
T8	3657	0	0	0
T9	4656	0	0	0
T10	371	0	0	0
T11	2313	0	0	0
T21	15782	18	0	0
T29	1039	9	0	0
T33	767	0	0	0
T48	0	8	0	0
T53	0	1	0	0
T69	0	21	0	0
T94	0	23	0	0
T95	0	5	0	0
T96	0	19	0	0
T98	0	9	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	15301	0	0
T1	3113	13	0	0
T2	4105	0	0	0
T3	44472	42	0	0
T4	29168	75	0	0
T5	11917	10	0	0
T6	4383	14	0	0
T7	45775	75	0	0
T8	29141	75	0	0
T9	36757	33	0	0
T10	2981	4	0	0
T11	0	27	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	1286	0	0
T5	11917	10	0	0
T6	4383	0	0	0
T7	45775	0	0	0
T8	29141	0	0	0
T9	36757	0	0	0
T10	2981	0	0	0
T11	18175	0	0	0
T21	123068	17	0	0
T29	8321	11	0	0
T33	6151	0	0	0
T48	0	10	0	0
T53	0	1	0	0
T69	0	23	0	0
T94	0	24	0	0
T95	0	6	0	0
T96	0	19	0	0
T97	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	15301	0	0
T1	3113	13	0	0
T2	4105	0	0	0
T3	44472	42	0	0
T4	29168	75	0	0
T5	11917	10	0	0
T6	4383	14	0	0
T7	45775	75	0	0
T8	29141	75	0	0
T9	36757	33	0	0
T10	2981	4	0	0
T11	0	27	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	1286	0	0
T5	11917	10	0	0
T6	4383	0	0	0
T7	45775	0	0	0
T8	29141	0	0	0
T9	36757	0	0	0
T10	2981	0	0	0
T11	18175	0	0	0
T21	123068	17	0	0
T29	8321	11	0	0
T33	6151	0	0	0
T48	0	10	0	0
T53	0	1	0	0
T69	0	23	0	0
T94	0	24	0	0
T95	0	6	0	0
T96	0	19	0	0
T97	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	15381	0	0
T1	3113	13	0	0
T2	4105	0	0	0
T3	44472	42	0	0
T4	29168	75	0	0
T5	11917	10	0	0
T6	4383	14	0	0
T7	45775	75	0	0
T8	29141	75	0	0
T9	36757	33	0	0
T10	2981	4	0	0
T11	0	27	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	1376	0	0
T5	11917	10	0	0
T6	4383	0	0	0
T7	45775	0	0	0
T8	29141	0	0	0
T9	36757	0	0	0
T10	2981	0	0	0
T11	18175	0	0	0
T21	123068	21	0	0
T29	8321	13	0	0
T33	6151	0	0	0
T48	0	11	0	0
T52	0	1	0	0
T53	0	1	0	0
T69	0	26	0	0
T94	0	29	0	0
T95	0	7	0	0
T96	0	25	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	15381	0	0
T1	3113	13	0	0
T2	4105	0	0	0
T3	44472	42	0	0
T4	29168	75	0	0
T5	11917	10	0	0
T6	4383	14	0	0
T7	45775	75	0	0
T8	29141	75	0	0
T9	36757	33	0	0
T10	2981	4	0	0
T11	0	27	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	1376	0	0
T5	11917	10	0	0
T6	4383	0	0	0
T7	45775	0	0	0
T8	29141	0	0	0
T9	36757	0	0	0
T10	2981	0	0	0
T11	18175	0	0	0
T21	123068	21	0	0
T29	8321	13	0	0
T33	6151	0	0	0
T48	0	11	0	0
T52	0	1	0	0
T53	0	1	0	0
T69	0	26	0	0
T94	0	29	0	0
T95	0	7	0	0
T96	0	25	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	15436	0	0
T1	3113	13	0	0
T2	4105	0	0	0
T3	44472	42	0	0
T4	29168	75	0	0
T5	11917	14	0	0
T6	4383	14	0	0
T7	45775	75	0	0
T8	29141	75	0	0
T9	36757	33	0	0
T10	2981	4	0	0
T11	0	27	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	1422	0	0
T5	11917	14	0	0
T6	4383	0	0	0
T7	45775	0	0	0
T8	29141	0	0	0
T9	36757	0	0	0
T10	2981	0	0	0
T11	18175	0	0	0
T21	123068	16	0	0
T29	8321	13	0	0
T33	6151	0	0	0
T48	0	11	0	0
T52	0	1	0	0
T69	0	22	0	0
T94	0	25	0	0
T95	0	9	0	0
T96	0	19	0	0
T97	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	15436	0	0
T1	3113	13	0	0
T2	4105	0	0	0
T3	44472	42	0	0
T4	29168	75	0	0
T5	11917	14	0	0
T6	4383	14	0	0
T7	45775	75	0	0
T8	29141	75	0	0
T9	36757	33	0	0
T10	2981	4	0	0
T11	0	27	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	1422	0	0
T5	11917	14	0	0
T6	4383	0	0	0
T7	45775	0	0	0
T8	29141	0	0	0
T9	36757	0	0	0
T10	2981	0	0	0
T11	18175	0	0	0
T21	123068	16	0	0
T29	8321	13	0	0
T33	6151	0	0	0
T48	0	11	0	0
T52	0	1	0	0
T69	0	22	0	0
T94	0	25	0	0
T95	0	9	0	0
T96	0	19	0	0
T97	0	1	0	0