Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	14504706	8449	0	0
alert_regwen_rd_A	14504706	8916	0	0
cpu_regwen_rd_A	14504706	8886	0	0
sw_rst_ctrl_n_0_rd_A	14504706	15022	0	0
sw_rst_ctrl_n_1_rd_A	14504706	14618	0	0
sw_rst_ctrl_n_2_rd_A	14504706	15229	0	0
sw_rst_ctrl_n_3_rd_A	14504706	14707	0	0
sw_rst_ctrl_n_4_rd_A	14504706	14788	0	0
sw_rst_ctrl_n_5_rd_A	14504706	14878	0	0
sw_rst_ctrl_n_6_rd_A	14504706	14948	0	0
sw_rst_ctrl_n_7_rd_A	14504706	14890	0	0
sw_rst_regwen_0_rd_A	14504706	9374	0	0
sw_rst_regwen_1_rd_A	14504706	9313	0	0
sw_rst_regwen_2_rd_A	14504706	9026	0	0
sw_rst_regwen_3_rd_A	14504706	9240	0	0
sw_rst_regwen_4_rd_A	14504706	9314	0	0
sw_rst_regwen_5_rd_A	14504706	9196	0	0
sw_rst_regwen_6_rd_A	14504706	9479	0	0
sw_rst_regwen_7_rd_A	14504706	9187	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	8449	0	0
T54	4493	137	0	0
T55	9125	427	0	0
T56	4223	18	0	0
T57	17906	3	0	0
T73	3827	137	0	0
T74	4151	433	0	0
T76	22300	4	0	0
T81	5939	514	0	0
T101	4972	35	0	0
T102	2471	4	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	8916	0	0
T3	38849	26	0	0
T4	25980	0	0	0
T5	11850	0	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	34	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T69	0	512	0	0
T92	0	56	0	0
T103	0	42	0	0
T105	0	40	0	0
T106	0	236	0	0
T112	0	74	0	0
T113	0	57	0	0
T115	0	10	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	8886	0	0
T3	38849	46	0	0
T4	25980	0	0	0
T5	11850	0	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	14	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T69	0	560	0	0
T92	0	67	0	0
T103	0	27	0	0
T105	0	47	0	0
T106	0	192	0	0
T112	0	59	0	0
T113	0	57	0	0
T115	0	13	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	15022	0	0
T3	38849	60	0	0
T4	25980	0	0	0
T5	11850	191	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	36	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	5	0	0
T69	0	802	0	0
T71	0	49	0	0
T92	0	66	0	0
T103	0	23	0	0
T124	0	6	0	0
T125	0	16	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	14618	0	0
T3	38849	38	0	0
T4	25980	0	0	0
T5	11850	164	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	19	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	10	0	0
T69	0	890	0	0
T71	0	20	0	0
T92	0	72	0	0
T103	0	24	0	0
T124	0	16	0	0
T125	0	14	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	15229	0	0
T3	38849	45	0	0
T4	25980	0	0	0
T5	11850	182	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	60	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	12	0	0
T69	0	867	0	0
T71	0	26	0	0
T92	0	64	0	0
T103	0	40	0	0
T124	0	17	0	0
T125	0	11	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	14707	0	0
T3	38849	29	0	0
T4	25980	0	0	0
T5	11850	177	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	19	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	8	0	0
T69	0	811	0	0
T71	0	49	0	0
T92	0	80	0	0
T103	0	21	0	0
T124	0	10	0	0
T125	0	5	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	14788	0	0
T3	38849	41	0	0
T4	25980	0	0	0
T5	11850	205	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	32	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	6	0	0
T69	0	826	0	0
T71	0	36	0	0
T92	0	59	0	0
T103	0	10	0	0
T124	0	14	0	0
T125	0	11	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	14878	0	0
T3	38849	37	0	0
T4	25980	0	0	0
T5	11850	192	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	20	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	14	0	0
T69	0	837	0	0
T71	0	19	0	0
T92	0	78	0	0
T103	0	21	0	0
T124	0	8	0	0
T125	0	14	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	14948	0	0
T3	38849	22	0	0
T4	25980	0	0	0
T5	11850	206	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	23	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	8	0	0
T69	0	859	0	0
T71	0	19	0	0
T92	0	81	0	0
T103	0	52	0	0
T124	0	5	0	0
T125	0	20	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	14890	0	0
T3	38849	26	0	0
T4	25980	0	0	0
T5	11850	167	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	23	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T69	0	841	0	0
T71	0	14	0	0
T92	0	56	0	0
T103	0	19	0	0
T105	0	38	0	0
T124	0	7	0	0
T125	0	3	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	9374	0	0
T3	38849	39	0	0
T4	25980	0	0	0
T5	11850	27	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	13	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	4	0	0
T69	0	555	0	0
T92	0	74	0	0
T103	0	47	0	0
T105	0	73	0	0
T112	0	40	0	0
T125	0	5	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	9313	0	0
T3	38849	43	0	0
T4	25980	0	0	0
T5	11850	48	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	10	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	7	0	0
T69	0	555	0	0
T92	0	56	0	0
T103	0	31	0	0
T105	0	66	0	0
T112	0	65	0	0
T125	0	16	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	9026	0	0
T3	38849	27	0	0
T4	25980	0	0	0
T5	11850	20	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	14	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T69	0	492	0	0
T92	0	71	0	0
T103	0	31	0	0
T105	0	44	0	0
T112	0	62	0	0
T125	0	1	0	0
T126	0	33	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	9240	0	0
T3	38849	48	0	0
T4	25980	0	0	0
T5	11850	11	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	30	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	9	0	0
T69	0	565	0	0
T92	0	62	0	0
T103	0	21	0	0
T105	0	59	0	0
T112	0	46	0	0
T125	0	3	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	9314	0	0
T3	38849	25	0	0
T4	25980	0	0	0
T5	11850	35	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	22	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T69	0	520	0	0
T92	0	82	0	0
T103	0	24	0	0
T105	0	46	0	0
T112	0	77	0	0
T125	0	7	0	0
T126	0	25	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	9196	0	0
T3	38849	20	0	0
T4	25980	0	0	0
T5	11850	37	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	48	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	10	0	0
T69	0	542	0	0
T92	0	72	0	0
T103	0	24	0	0
T105	0	62	0	0
T112	0	71	0	0
T125	0	12	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	9479	0	0
T3	38849	46	0	0
T4	25980	0	0	0
T5	11850	40	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	50	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	11	0	0
T69	0	538	0	0
T92	0	45	0	0
T103	0	53	0	0
T105	0	38	0	0
T112	0	60	0	0
T125	0	11	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14504706	9187	0	0
T3	38849	35	0	0
T4	25980	0	0	0
T5	11850	27	0	0
T6	3377	0	0	0
T7	42457	0	0	0
T8	26180	0	0	0
T9	31848	28	0	0
T10	2740	0	0	0
T11	14090	0	0	0
T21	98741	0	0	0
T52	0	4	0	0
T69	0	554	0	0
T92	0	59	0	0
T103	0	22	0	0
T105	0	41	0	0
T112	0	75	0	0
T125	0	1	0	0