Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	13690353	14054	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	13690353	129548	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	13690353	8267603	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	13690353	207011	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	13690353	14054	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	13690353	129548	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	13690353	8267603	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	13690353	207011	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	14054	0	0
T1	2375	13	0	0
T2	3990	0	0	0
T3	38849	42	0	0
T4	25980	75	0	0
T5	11850	0	0	0
T6	3377	14	0	0
T7	42457	75	0	0
T8	26180	75	0	0
T9	31848	33	0	0
T10	2740	4	0	0
T11	0	27	0	0
T21	0	202	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	129548	0	0
T1	2375	117	0	0
T2	3990	0	0	0
T3	38849	381	0	0
T4	25980	718	0	0
T5	11850	0	0	0
T6	3377	126	0	0
T7	42457	715	0	0
T8	26180	700	0	0
T9	31848	299	0	0
T10	2740	38	0	0
T11	0	245	0	0
T21	0	1851	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	8267603	0	0
T1	2375	1532	0	0
T2	3990	872	0	0
T3	38849	29934	0	0
T4	25980	8753	0	0
T5	11850	11259	0	0
T6	3377	2590	0	0
T7	42457	25179	0	0
T8	26180	8777	0	0
T9	31848	23764	0	0
T10	2740	1766	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	207011	0	0
T1	2375	202	0	0
T2	3990	0	0	0
T3	38849	615	0	0
T4	25980	1131	0	0
T5	11850	0	0	0
T6	3377	193	0	0
T7	42457	1102	0	0
T8	26180	1047	0	0
T9	31848	503	0	0
T10	2740	73	0	0
T11	0	415	0	0
T21	0	2959	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	14054	0	0
T1	2375	13	0	0
T2	3990	0	0	0
T3	38849	42	0	0
T4	25980	75	0	0
T5	11850	0	0	0
T6	3377	14	0	0
T7	42457	75	0	0
T8	26180	75	0	0
T9	31848	33	0	0
T10	2740	4	0	0
T11	0	27	0	0
T21	0	202	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	129548	0	0
T1	2375	117	0	0
T2	3990	0	0	0
T3	38849	381	0	0
T4	25980	718	0	0
T5	11850	0	0	0
T6	3377	126	0	0
T7	42457	715	0	0
T8	26180	700	0	0
T9	31848	299	0	0
T10	2740	38	0	0
T11	0	245	0	0
T21	0	1851	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	8267603	0	0
T1	2375	1532	0	0
T2	3990	872	0	0
T3	38849	29934	0	0
T4	25980	8753	0	0
T5	11850	11259	0	0
T6	3377	2590	0	0
T7	42457	25179	0	0
T8	26180	8777	0	0
T9	31848	23764	0	0
T10	2740	1766	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	207011	0	0
T1	2375	202	0	0
T2	3990	0	0	0
T3	38849	615	0	0
T4	25980	1131	0	0
T5	11850	0	0	0
T6	3377	193	0	0
T7	42457	1102	0	0
T8	26180	1047	0	0
T9	31848	503	0	0
T10	2740	73	0	0
T11	0	415	0	0
T21	0	2959	0	0