Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T3,T9,T10
1	0	Covered	T3,T9,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	63634786	9892	0	0
CascadeEffAonToRstPorAboveRise_A	63634786	9892	0	0
CascadeEffAonToRstPorIoAboveFall_A	61087654	9892	0	0
CascadeEffAonToRstPorIoAboveRise_A	61087654	9892	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	30545038	9892	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	30545038	9892	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	15272062	9892	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	15272062	9892	0	0
CascadeEffAonToRstPorUcbAboveFall_A	30544745	9892	0	0
CascadeEffAonToRstPorUcbAboveRise_A	30544745	9892	0	0
CascadeLcToLcAboveFall_A	63634786	23946	0	0
CascadeLcToLcAboveRise_A	63634786	23946	0	0
CascadeLcToLcAonAboveFall_A	1927857	23946	0	0
CascadeLcToLcAonAboveRise_A	1927857	23946	0	0
CascadeLcToLcShadowedAboveFall_A	63634786	23946	0	0
CascadeLcToLcShadowedAboveRise_A	63634786	23946	0	0
CascadePorToAonAboveFall_A	1927857	7926	0	0
CascadeSysToSysAboveFall_A	63634786	23946	0	0
CascadeSysToSysAboveRise_A	63634786	23946	0	0
ScanRstToAonRise_A	1927857	243	0	0
StablePorToAonRise_A	1927857	9892	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	13690353	23946	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	13690353	23946	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	13690353	23946	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	13690353	23946	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	15272062	23946	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	15272062	23946	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	13690353	23946	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	13690353	23946	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	13690353	23946	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	13690353	23946	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63634786	9892	0	0
T1	12977	1	0	0
T2	17106	2	0	0
T3	185295	20	0	0
T4	121559	27	0	0
T5	49656	1	0	0
T6	18265	1	0	0
T7	190696	27	0	0
T8	121404	27	0	0
T9	153172	16	0	0
T10	12431	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63634786	9892	0	0
T1	12977	1	0	0
T2	17106	2	0	0
T3	185295	20	0	0
T4	121559	27	0	0
T5	49656	1	0	0
T6	18265	1	0	0
T7	190696	27	0	0
T8	121404	27	0	0
T9	153172	16	0	0
T10	12431	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61087654	9892	0	0
T1	12457	1	0	0
T2	16421	2	0	0
T3	177865	20	0	0
T4	116646	27	0	0
T5	47670	1	0	0
T6	17533	1	0	0
T7	183072	27	0	0
T8	116571	27	0	0
T9	147039	16	0	0
T10	11933	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61087654	9892	0	0
T1	12457	1	0	0
T2	16421	2	0	0
T3	177865	20	0	0
T4	116646	27	0	0
T5	47670	1	0	0
T6	17533	1	0	0
T7	183072	27	0	0
T8	116571	27	0	0
T9	147039	16	0	0
T10	11933	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30545038	9892	0	0
T1	6228	1	0	0
T2	8211	2	0	0
T3	88939	20	0	0
T4	58323	27	0	0
T5	23834	1	0	0
T6	8766	1	0	0
T7	91545	27	0	0
T8	58272	27	0	0
T9	73521	16	0	0
T10	5963	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30545038	9892	0	0
T1	6228	1	0	0
T2	8211	2	0	0
T3	88939	20	0	0
T4	58323	27	0	0
T5	23834	1	0	0
T6	8766	1	0	0
T7	91545	27	0	0
T8	58272	27	0	0
T9	73521	16	0	0
T10	5963	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	9892	0	0
T1	3113	1	0	0
T2	4105	2	0	0
T3	44472	20	0	0
T4	29168	27	0	0
T5	11917	1	0	0
T6	4383	1	0	0
T7	45775	27	0	0
T8	29141	27	0	0
T9	36757	16	0	0
T10	2981	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	9892	0	0
T1	3113	1	0	0
T2	4105	2	0	0
T3	44472	20	0	0
T4	29168	27	0	0
T5	11917	1	0	0
T6	4383	1	0	0
T7	45775	27	0	0
T8	29141	27	0	0
T9	36757	16	0	0
T10	2981	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30544745	9892	0	0
T1	6228	1	0	0
T2	8211	2	0	0
T3	88937	20	0	0
T4	58342	27	0	0
T5	23834	1	0	0
T6	8767	1	0	0
T7	91547	27	0	0
T8	58269	27	0	0
T9	73519	16	0	0
T10	5966	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30544745	9892	0	0
T1	6228	1	0	0
T2	8211	2	0	0
T3	88937	20	0	0
T4	58342	27	0	0
T5	23834	1	0	0
T6	8767	1	0	0
T7	91547	27	0	0
T8	58269	27	0	0
T9	73519	16	0	0
T10	5966	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63634786	23946	0	0
T1	12977	14	0	0
T2	17106	2	0	0
T3	185295	62	0	0
T4	121559	102	0	0
T5	49656	1	0	0
T6	18265	15	0	0
T7	190696	102	0	0
T8	121404	102	0	0
T9	153172	49	0	0
T10	12431	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63634786	23946	0	0
T1	12977	14	0	0
T2	17106	2	0	0
T3	185295	62	0	0
T4	121559	102	0	0
T5	49656	1	0	0
T6	18265	15	0	0
T7	190696	102	0	0
T8	121404	102	0	0
T9	153172	49	0	0
T10	12431	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	23946	0	0
T1	388	14	0	0
T2	512	2	0	0
T3	5640	62	0	0
T4	3659	102	0	0
T5	1489	1	0	0
T6	547	15	0	0
T7	5736	102	0	0
T8	3657	102	0	0
T9	4656	49	0	0
T10	371	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	23946	0	0
T1	388	14	0	0
T2	512	2	0	0
T3	5640	62	0	0
T4	3659	102	0	0
T5	1489	1	0	0
T6	547	15	0	0
T7	5736	102	0	0
T8	3657	102	0	0
T9	4656	49	0	0
T10	371	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63634786	23946	0	0
T1	12977	14	0	0
T2	17106	2	0	0
T3	185295	62	0	0
T4	121559	102	0	0
T5	49656	1	0	0
T6	18265	15	0	0
T7	190696	102	0	0
T8	121404	102	0	0
T9	153172	49	0	0
T10	12431	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63634786	23946	0	0
T1	12977	14	0	0
T2	17106	2	0	0
T3	185295	62	0	0
T4	121559	102	0	0
T5	49656	1	0	0
T6	18265	15	0	0
T7	190696	102	0	0
T8	121404	102	0	0
T9	153172	49	0	0
T10	12431	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	7926	0	0
T1	388	1	0	0
T2	512	13	0	0
T3	5640	9	0	0
T4	3659	27	0	0
T5	1489	1	0	0
T6	547	1	0	0
T7	5736	27	0	0
T8	3657	27	0	0
T9	4656	11	0	0
T10	371	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63634786	23946	0	0
T1	12977	14	0	0
T2	17106	2	0	0
T3	185295	62	0	0
T4	121559	102	0	0
T5	49656	1	0	0
T6	18265	15	0	0
T7	190696	102	0	0
T8	121404	102	0	0
T9	153172	49	0	0
T10	12431	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63634786	23946	0	0
T1	12977	14	0	0
T2	17106	2	0	0
T3	185295	62	0	0
T4	121559	102	0	0
T5	49656	1	0	0
T6	18265	15	0	0
T7	190696	102	0	0
T8	121404	102	0	0
T9	153172	49	0	0
T10	12431	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	243	0	0
T3	5640	1	0	0
T4	3659	0	0	0
T5	1489	0	0	0
T6	547	0	0	0
T7	5736	0	0	0
T8	3657	0	0	0
T9	4656	0	0	0
T10	371	0	0	0
T11	2313	2	0	0
T21	15782	8	0	0
T44	0	1	0	0
T69	0	4	0	0
T92	0	2	0	0
T94	0	4	0	0
T96	0	5	0	0
T112	0	1	0	0
T127	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927857	9892	0	0
T1	388	1	0	0
T2	512	2	0	0
T3	5640	20	0	0
T4	3659	27	0	0
T5	1489	1	0	0
T6	547	1	0	0
T7	5736	27	0	0
T8	3657	27	0	0
T9	4656	16	0	0
T10	371	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	23946	0	0
T1	2375	14	0	0
T2	3990	2	0	0
T3	38849	62	0	0
T4	25980	102	0	0
T5	11850	1	0	0
T6	3377	15	0	0
T7	42457	102	0	0
T8	26180	102	0	0
T9	31848	49	0	0
T10	2740	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	23946	0	0
T1	2375	14	0	0
T2	3990	2	0	0
T3	38849	62	0	0
T4	25980	102	0	0
T5	11850	1	0	0
T6	3377	15	0	0
T7	42457	102	0	0
T8	26180	102	0	0
T9	31848	49	0	0
T10	2740	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	23946	0	0
T1	2375	14	0	0
T2	3990	2	0	0
T3	38849	62	0	0
T4	25980	102	0	0
T5	11850	1	0	0
T6	3377	15	0	0
T7	42457	102	0	0
T8	26180	102	0	0
T9	31848	49	0	0
T10	2740	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	23946	0	0
T1	2375	14	0	0
T2	3990	2	0	0
T3	38849	62	0	0
T4	25980	102	0	0
T5	11850	1	0	0
T6	3377	15	0	0
T7	42457	102	0	0
T8	26180	102	0	0
T9	31848	49	0	0
T10	2740	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	23946	0	0
T1	3113	14	0	0
T2	4105	2	0	0
T3	44472	62	0	0
T4	29168	102	0	0
T5	11917	1	0	0
T6	4383	15	0	0
T7	45775	102	0	0
T8	29141	102	0	0
T9	36757	49	0	0
T10	2981	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15272062	23946	0	0
T1	3113	14	0	0
T2	4105	2	0	0
T3	44472	62	0	0
T4	29168	102	0	0
T5	11917	1	0	0
T6	4383	15	0	0
T7	45775	102	0	0
T8	29141	102	0	0
T9	36757	49	0	0
T10	2981	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	23946	0	0
T1	2375	14	0	0
T2	3990	2	0	0
T3	38849	62	0	0
T4	25980	102	0	0
T5	11850	1	0	0
T6	3377	15	0	0
T7	42457	102	0	0
T8	26180	102	0	0
T9	31848	49	0	0
T10	2740	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	23946	0	0
T1	2375	14	0	0
T2	3990	2	0	0
T3	38849	62	0	0
T4	25980	102	0	0
T5	11850	1	0	0
T6	3377	15	0	0
T7	42457	102	0	0
T8	26180	102	0	0
T9	31848	49	0	0
T10	2740	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	23946	0	0
T1	2375	14	0	0
T2	3990	2	0	0
T3	38849	62	0	0
T4	25980	102	0	0
T5	11850	1	0	0
T6	3377	15	0	0
T7	42457	102	0	0
T8	26180	102	0	0
T9	31848	49	0	0
T10	2740	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13690353	23946	0	0
T1	2375	14	0	0
T2	3990	2	0	0
T3	38849	62	0	0
T4	25980	102	0	0
T5	11850	1	0	0
T6	3377	15	0	0
T7	42457	102	0	0
T8	26180	102	0	0
T9	31848	49	0	0
T10	2740	6	0	0