Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	614066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

370262

1

T1

135

T2

138

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	523455	1			T1	186		T2	186		T4	1587
values[0x0]	229748	1			T1	104		T2	84		T3	9
values[0x1]	231125	1			T1	89		T2	109		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	515250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

469078

1

T1

162

T2

184

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4058	1			T4	8		T5	6		T7	8
valid_sources[0x01]	3714	1			T4	4		T5	18		T7	10
valid_sources[0x02]	3665	1			T4	16		T5	7		T7	14
valid_sources[0x03]	3388	1			T4	13		T5	9		T7	21
valid_sources[0x04]	3737	1			T4	9		T5	14		T7	6
valid_sources[0x05]	3569	1			T4	7		T5	12		T7	14
valid_sources[0x06]	3973	1			T4	12		T5	16		T7	12
valid_sources[0x07]	6433	1			T4	11		T5	4		T7	24
valid_sources[0x08]	4138	1			T4	5		T5	13		T7	14
valid_sources[0x09]	3186	1			T4	11		T5	3		T7	12
valid_sources[0x0a]	3362	1			T4	5		T5	14		T7	10
valid_sources[0x0b]	3358	1			T4	9		T5	6		T7	10
valid_sources[0x0c]	4001	1			T4	15		T5	8		T7	15
valid_sources[0x0d]	3666	1			T4	5		T5	4		T7	6
valid_sources[0x0e]	3601	1			T4	5		T5	8		T7	11
valid_sources[0x0f]	4308	1			T4	9		T5	5		T7	11
valid_sources[0x10]	4845	1			T4	5		T5	11		T7	9
valid_sources[0x11]	3878	1			T4	12		T5	8		T7	14
valid_sources[0x12]	3724	1			T4	17		T5	6		T7	17
valid_sources[0x13]	3288	1			T4	12		T5	7		T7	11
valid_sources[0x14]	4206	1			T4	20		T5	7		T7	8
valid_sources[0x15]	4189	1			T4	11		T5	4		T7	16
valid_sources[0x16]	3754	1			T4	7		T5	5		T7	19
valid_sources[0x17]	3591	1			T4	5		T5	4		T7	20
valid_sources[0x18]	3449	1			T4	12		T5	15		T7	7
valid_sources[0x19]	5203	1			T4	11		T5	10		T7	15
valid_sources[0x1a]	4895	1			T4	17		T5	11		T7	23
valid_sources[0x1b]	4227	1			T4	11		T5	6		T7	11
valid_sources[0x1c]	3707	1			T4	5		T5	9		T7	26
valid_sources[0x1d]	3981	1			T4	10		T5	5		T7	9
valid_sources[0x1e]	3573	1			T4	5		T5	11		T7	14
valid_sources[0x1f]	3338	1			T4	4		T5	4		T7	28
valid_sources[0x20]	3141	1			T4	7		T5	15		T7	12
valid_sources[0x21]	3767	1			T4	10		T5	7		T7	25
valid_sources[0x22]	3276	1			T4	7		T5	19		T7	3
valid_sources[0x23]	3887	1			T4	12		T5	6		T7	21
valid_sources[0x24]	3361	1			T4	10		T5	10		T7	8
valid_sources[0x25]	2859	1			T3	2		T4	4		T5	9
valid_sources[0x26]	3712	1			T4	13		T5	7		T7	12
valid_sources[0x27]	3640	1			T1	379		T4	6		T5	2
valid_sources[0x28]	3273	1			T4	10		T5	13		T7	14
valid_sources[0x29]	4482	1			T4	9		T5	7		T7	32
valid_sources[0x2a]	3913	1			T4	12		T5	22		T7	18
valid_sources[0x2b]	6755	1			T4	20		T5	8		T7	7
valid_sources[0x2c]	3429	1			T4	10		T5	9		T7	18
valid_sources[0x2d]	3970	1			T4	14		T5	6		T7	15
valid_sources[0x2e]	3108	1			T4	5		T5	6		T7	11
valid_sources[0x2f]	3040	1			T3	1		T4	25		T5	12
valid_sources[0x30]	6744	1			T4	20		T5	18		T7	6
valid_sources[0x31]	3373	1			T4	5		T5	2		T7	2
valid_sources[0x32]	3228	1			T4	5		T5	4		T7	8
valid_sources[0x33]	3292	1			T4	9		T5	7		T7	26
valid_sources[0x34]	4006	1			T4	16		T5	7		T7	20
valid_sources[0x35]	4615	1			T4	9		T5	15		T7	26
valid_sources[0x36]	4950	1			T4	12		T5	10		T7	13
valid_sources[0x37]	3038	1			T4	11		T5	6		T7	6
valid_sources[0x38]	3699	1			T4	15		T5	1		T7	9
valid_sources[0x39]	4032	1			T4	4		T5	8		T7	11
valid_sources[0x3a]	3548	1			T4	12		T5	10		T7	13
valid_sources[0x3b]	3895	1			T4	3		T5	8		T7	10
valid_sources[0x3c]	4511	1			T4	14		T5	9		T7	22
valid_sources[0x3d]	4534	1			T4	8		T5	8		T7	7
valid_sources[0x3e]	4589	1			T4	2		T5	12		T7	12
valid_sources[0x3f]	3704	1			T4	5		T5	9		T7	11
valid_sources[0x40]	4318	1			T4	7		T5	5		T7	7
valid_sources[0x41]	5095	1			T4	11		T5	10		T7	16
valid_sources[0x42]	4219	1			T4	13		T5	18		T7	15
valid_sources[0x43]	2851	1			T4	10		T5	15		T7	12
valid_sources[0x44]	4003	1			T4	5		T5	14		T7	9
valid_sources[0x45]	2701	1			T4	7		T5	13		T7	9
valid_sources[0x46]	3870	1			T4	9		T5	10		T7	11
valid_sources[0x47]	6488	1			T4	4		T5	6		T7	14
valid_sources[0x48]	3293	1			T3	1		T4	24		T5	13
valid_sources[0x49]	3058	1			T4	11		T5	5		T7	18
valid_sources[0x4a]	4082	1			T4	10		T5	15		T7	8
valid_sources[0x4b]	3168	1			T4	11		T5	1		T7	6
valid_sources[0x4c]	3675	1			T4	4		T5	3		T7	9
valid_sources[0x4d]	4590	1			T4	11		T5	8		T7	18
valid_sources[0x4e]	3220	1			T4	12		T5	6		T7	10
valid_sources[0x4f]	3051	1			T4	10		T5	4		T7	26
valid_sources[0x50]	6202	1			T4	17		T5	13		T7	13
valid_sources[0x51]	3988	1			T4	13		T5	9		T7	8
valid_sources[0x52]	4264	1			T4	12		T5	10		T7	23
valid_sources[0x53]	4282	1			T4	9		T5	12		T7	20
valid_sources[0x54]	2944	1			T4	10		T5	1		T7	7
valid_sources[0x55]	3577	1			T4	22		T5	11		T7	8
valid_sources[0x56]	4411	1			T4	9		T5	6		T7	15
valid_sources[0x57]	3225	1			T3	7		T4	19		T5	6
valid_sources[0x58]	3476	1			T4	19		T5	15		T7	16
valid_sources[0x59]	3268	1			T4	15		T5	7		T7	21
valid_sources[0x5a]	3143	1			T4	11		T5	11		T7	16
valid_sources[0x5b]	3423	1			T3	1		T4	16		T5	1
valid_sources[0x5c]	3826	1			T4	26		T5	7		T7	11
valid_sources[0x5d]	3787	1			T4	13		T5	6		T7	14
valid_sources[0x5e]	3649	1			T4	10		T5	6		T7	9
valid_sources[0x5f]	3332	1			T4	14		T5	6		T7	9
valid_sources[0x60]	3600	1			T4	10		T5	19		T7	12
valid_sources[0x61]	4073	1			T4	3		T5	11		T7	7
valid_sources[0x62]	3339	1			T4	16		T5	9		T7	11
valid_sources[0x63]	3610	1			T4	16		T5	8		T7	19
valid_sources[0x64]	4578	1			T4	17		T5	11		T7	22
valid_sources[0x65]	4152	1			T4	8		T5	2		T7	4
valid_sources[0x66]	7452	1			T4	11		T5	11		T7	21
valid_sources[0x67]	3449	1			T4	7		T5	8		T7	17
valid_sources[0x68]	3945	1			T4	11		T5	4		T7	9
valid_sources[0x69]	4647	1			T4	10		T5	6		T7	11
valid_sources[0x6a]	3531	1			T4	7		T5	15		T7	12
valid_sources[0x6b]	6856	1			T4	4		T5	8		T7	13
valid_sources[0x6c]	3313	1			T4	6		T5	19		T7	6
valid_sources[0x6d]	3123	1			T4	7		T5	5		T7	19
valid_sources[0x6e]	2732	1			T4	18		T5	12		T7	2
valid_sources[0x6f]	4420	1			T4	10		T5	9		T7	20
valid_sources[0x70]	3386	1			T4	7		T5	4		T7	24
valid_sources[0x71]	3409	1			T4	15		T5	10		T7	10
valid_sources[0x72]	3214	1			T4	10		T5	5		T7	8
valid_sources[0x73]	3324	1			T4	4		T5	6		T7	15
valid_sources[0x74]	3625	1			T4	5		T5	9		T7	17
valid_sources[0x75]	3593	1			T4	10		T5	17		T7	8
valid_sources[0x76]	4500	1			T4	12		T5	12		T7	13
valid_sources[0x77]	4329	1			T4	11		T5	9		T7	18
valid_sources[0x78]	2979	1			T4	21		T5	10		T7	17
valid_sources[0x79]	4650	1			T4	6		T5	7		T7	15
valid_sources[0x7a]	3996	1			T4	5		T5	5		T7	5
valid_sources[0x7b]	4348	1			T4	20		T5	17		T7	9
valid_sources[0x7c]	3430	1			T4	8		T5	4		T7	9
valid_sources[0x7d]	4767	1			T4	13		T5	3		T7	9
valid_sources[0x7e]	3116	1			T4	2		T5	11		T7	17
valid_sources[0x7f]	3692	1			T4	9		T5	12		T7	14
valid_sources[0x80]	3145	1			T4	6		T5	5		T7	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

245958

1

T1

95

T2

94

T4

767

values[0x0]

all_enables

biggest_size

80764

1

T1

28

T2

25

T3

6

values[0x1]

all_enables

biggest_size

43540

1

T1

12

T2

19

T3

4