Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T21,T62
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T21,T62
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T21
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T21
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T21,T62
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T21,T25
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T21,T62
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T21
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12644149	14045	0	0
gen_assertions[0].RstEnOn_A	12644149	1091	0	0
gen_assertions[0].RstNOff_A	12644149	14045	0	0
gen_assertions[0].RstNOn_A	12644149	1091	0	0
gen_assertions[1].RstEnOff_A	50576605	12778	0	0
gen_assertions[1].RstEnOn_A	50576605	1075	0	0
gen_assertions[1].RstNOff_A	50576605	12778	0	0
gen_assertions[1].RstNOn_A	50576605	1075	0	0
gen_assertions[2].RstEnOff_A	25289064	12838	0	0
gen_assertions[2].RstEnOn_A	25289064	1062	0	0
gen_assertions[2].RstNOff_A	25289064	12838	0	0
gen_assertions[2].RstNOn_A	25289064	1062	0	0
gen_assertions[3].RstEnOff_A	25289265	12871	0	0
gen_assertions[3].RstEnOn_A	25289265	1094	0	0
gen_assertions[3].RstNOff_A	25289265	12871	0	0
gen_assertions[3].RstNOn_A	25289265	1094	0	0
gen_assertions[4].RstEnOff_A	1597051	21428	0	0
gen_assertions[4].RstEnOn_A	1597051	1118	0	0
gen_assertions[4].RstNOff_A	1597051	21428	0	0
gen_assertions[4].RstNOn_A	1597051	1118	0	0
gen_assertions[5].RstEnOff_A	12644149	14304	0	0
gen_assertions[5].RstEnOn_A	12644149	1201	0	0
gen_assertions[5].RstNOff_A	12644149	14304	0	0
gen_assertions[5].RstNOn_A	12644149	1201	0	0
gen_assertions[6].RstEnOff_A	12644149	14342	0	0
gen_assertions[6].RstEnOn_A	12644149	1233	0	0
gen_assertions[6].RstNOff_A	12644149	14342	0	0
gen_assertions[6].RstNOn_A	12644149	1233	0	0
gen_assertions[7].RstEnOff_A	12644149	14371	0	0
gen_assertions[7].RstEnOn_A	12644149	1264	0	0
gen_assertions[7].RstNOff_A	12644149	14371	0	0
gen_assertions[7].RstNOn_A	12644149	1264	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	14045	0	0
T1	2652	4	0	0
T2	4585	4	0	0
T3	1511	0	0	0
T4	22478	23	0	0
T5	31286	34	0	0
T6	5832	0	0	0
T7	45217	75	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	4	0	0
T12	0	4	0	0
T13	0	25	0	0
T21	0	5	0	0
T23	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	1091	0	0
T12	7552	4	0	0
T13	32960	0	0	0
T14	2074	0	0	0
T21	3045	5	0	0
T22	5831	0	0	0
T23	2264	0	0	0
T24	3639	0	0	0
T25	6226	0	0	0
T56	0	6	0	0
T61	0	1	0	0
T62	119549	7	0	0
T82	5969	0	0	0
T83	0	6	0	0
T84	0	32	0	0
T85	0	15	0	0
T86	0	3	0	0
T87	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	14045	0	0
T1	2652	4	0	0
T2	4585	4	0	0
T3	1511	0	0	0
T4	22478	23	0	0
T5	31286	34	0	0
T6	5832	0	0	0
T7	45217	75	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	4	0	0
T12	0	4	0	0
T13	0	25	0	0
T21	0	5	0	0
T23	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	1091	0	0
T12	7552	4	0	0
T13	32960	0	0	0
T14	2074	0	0	0
T21	3045	5	0	0
T22	5831	0	0	0
T23	2264	0	0	0
T24	3639	0	0	0
T25	6226	0	0	0
T56	0	6	0	0
T61	0	1	0	0
T62	119549	7	0	0
T82	5969	0	0	0
T83	0	6	0	0
T84	0	32	0	0
T85	0	15	0	0
T86	0	3	0	0
T87	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50576605	12778	0	0
T1	10610	4	0	0
T2	18346	4	0	0
T3	6049	0	0	0
T4	89921	20	0	0
T5	125133	28	0	0
T6	23333	0	0	0
T7	180826	63	0	0
T8	18558	0	0	0
T9	15205	0	0	0
T10	17343	4	0	0
T12	0	4	0	0
T13	0	22	0	0
T21	0	6	0	0
T23	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50576605	1075	0	0
T12	30214	4	0	0
T13	131825	0	0	0
T14	8301	0	0	0
T21	12184	6	0	0
T22	23345	0	0	0
T23	9061	0	0	0
T24	14558	0	0	0
T25	24903	0	0	0
T56	0	4	0	0
T62	478202	8	0	0
T82	23886	0	0	0
T83	0	5	0	0
T84	0	34	0	0
T85	0	13	0	0
T86	0	3	0	0
T88	0	3	0	0
T89	0	30	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50576605	12778	0	0
T1	10610	4	0	0
T2	18346	4	0	0
T3	6049	0	0	0
T4	89921	20	0	0
T5	125133	28	0	0
T6	23333	0	0	0
T7	180826	63	0	0
T8	18558	0	0	0
T9	15205	0	0	0
T10	17343	4	0	0
T12	0	4	0	0
T13	0	22	0	0
T21	0	6	0	0
T23	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50576605	1075	0	0
T12	30214	4	0	0
T13	131825	0	0	0
T14	8301	0	0	0
T21	12184	6	0	0
T22	23345	0	0	0
T23	9061	0	0	0
T24	14558	0	0	0
T25	24903	0	0	0
T56	0	4	0	0
T62	478202	8	0	0
T82	23886	0	0	0
T83	0	5	0	0
T84	0	34	0	0
T85	0	13	0	0
T86	0	3	0	0
T88	0	3	0	0
T89	0	30	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289064	12838	0	0
T1	5306	5	0	0
T2	9171	4	0	0
T3	3024	0	0	0
T4	44960	20	0	0
T5	62567	28	0	0
T6	11665	0	0	0
T7	90405	63	0	0
T8	9279	0	0	0
T9	7603	0	0	0
T10	8671	4	0	0
T12	0	3	0	0
T13	0	22	0	0
T21	0	7	0	0
T23	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289064	1062	0	0
T1	5306	1	0	0
T2	9171	0	0	0
T3	3024	0	0	0
T4	44960	0	0	0
T5	62567	0	0	0
T6	11665	0	0	0
T7	90405	0	0	0
T8	9279	0	0	0
T9	7603	0	0	0
T10	8671	0	0	0
T12	0	3	0	0
T21	0	7	0	0
T56	0	6	0	0
T62	0	8	0	0
T83	0	6	0	0
T84	0	31	0	0
T85	0	13	0	0
T86	0	4	0	0
T88	0	3	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289064	12838	0	0
T1	5306	5	0	0
T2	9171	4	0	0
T3	3024	0	0	0
T4	44960	20	0	0
T5	62567	28	0	0
T6	11665	0	0	0
T7	90405	63	0	0
T8	9279	0	0	0
T9	7603	0	0	0
T10	8671	4	0	0
T12	0	3	0	0
T13	0	22	0	0
T21	0	7	0	0
T23	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289064	1062	0	0
T1	5306	1	0	0
T2	9171	0	0	0
T3	3024	0	0	0
T4	44960	0	0	0
T5	62567	0	0	0
T6	11665	0	0	0
T7	90405	0	0	0
T8	9279	0	0	0
T9	7603	0	0	0
T10	8671	0	0	0
T12	0	3	0	0
T21	0	7	0	0
T56	0	6	0	0
T62	0	8	0	0
T83	0	6	0	0
T84	0	31	0	0
T85	0	13	0	0
T86	0	4	0	0
T88	0	3	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289265	12871	0	0
T1	5303	4	0	0
T2	9173	5	0	0
T3	3024	0	0	0
T4	44962	20	0	0
T5	62565	28	0	0
T6	11662	0	0	0
T7	90405	63	0	0
T8	9279	0	0	0
T9	7602	0	0	0
T10	8669	4	0	0
T12	0	7	0	0
T13	0	22	0	0
T21	0	8	0	0
T23	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289265	1094	0	0
T2	9173	1	0	0
T3	3024	0	0	0
T4	44962	0	0	0
T5	62565	0	0	0
T6	11662	0	0	0
T7	90405	0	0	0
T8	9279	0	0	0
T9	7602	0	0	0
T10	8669	0	0	0
T11	10035	0	0	0
T12	0	7	0	0
T21	0	8	0	0
T25	0	1	0	0
T56	0	7	0	0
T61	0	1	0	0
T62	0	7	0	0
T83	0	7	0	0
T84	0	31	0	0
T85	0	14	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289265	12871	0	0
T1	5303	4	0	0
T2	9173	5	0	0
T3	3024	0	0	0
T4	44962	20	0	0
T5	62565	28	0	0
T6	11662	0	0	0
T7	90405	63	0	0
T8	9279	0	0	0
T9	7602	0	0	0
T10	8669	4	0	0
T12	0	7	0	0
T13	0	22	0	0
T21	0	8	0	0
T23	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289265	1094	0	0
T2	9173	1	0	0
T3	3024	0	0	0
T4	44962	0	0	0
T5	62565	0	0	0
T6	11662	0	0	0
T7	90405	0	0	0
T8	9279	0	0	0
T9	7602	0	0	0
T10	8669	0	0	0
T11	10035	0	0	0
T12	0	7	0	0
T21	0	8	0	0
T25	0	1	0	0
T56	0	7	0	0
T61	0	1	0	0
T62	0	7	0	0
T83	0	7	0	0
T84	0	31	0	0
T85	0	14	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	21428	0	0
T1	331	6	0	0
T2	571	6	0	0
T3	188	1	0	0
T4	2835	48	0	0
T5	4003	47	0	0
T6	731	3	0	0
T7	5664	92	0	0
T8	578	2	0	0
T9	474	2	0	0
T10	541	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	1118	0	0
T12	942	8	0	0
T13	4164	0	0	0
T14	258	0	0	0
T21	379	9	0	0
T22	731	0	0	0
T23	281	0	0	0
T24	453	0	0	0
T25	776	0	0	0
T56	0	8	0	0
T61	0	1	0	0
T62	15222	7	0	0
T82	748	0	0	0
T83	0	7	0	0
T84	0	31	0	0
T85	0	15	0	0
T86	0	8	0	0
T88	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	21428	0	0
T1	331	6	0	0
T2	571	6	0	0
T3	188	1	0	0
T4	2835	48	0	0
T5	4003	47	0	0
T6	731	3	0	0
T7	5664	92	0	0
T8	578	2	0	0
T9	474	2	0	0
T10	541	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	1118	0	0
T12	942	8	0	0
T13	4164	0	0	0
T14	258	0	0	0
T21	379	9	0	0
T22	731	0	0	0
T23	281	0	0	0
T24	453	0	0	0
T25	776	0	0	0
T56	0	8	0	0
T61	0	1	0	0
T62	15222	7	0	0
T82	748	0	0	0
T83	0	7	0	0
T84	0	31	0	0
T85	0	15	0	0
T86	0	8	0	0
T88	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	14304	0	0
T1	2652	4	0	0
T2	4585	4	0	0
T3	1511	0	0	0
T4	22478	23	0	0
T5	31286	34	0	0
T6	5832	0	0	0
T7	45217	75	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	4	0	0
T12	0	9	0	0
T13	0	25	0	0
T21	0	8	0	0
T23	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	1201	0	0
T12	7552	9	0	0
T13	32960	0	0	0
T14	2074	0	0	0
T21	3045	8	0	0
T22	5831	0	0	0
T23	2264	0	0	0
T24	3639	0	0	0
T25	6226	1	0	0
T56	0	8	0	0
T62	119549	9	0	0
T82	5969	0	0	0
T83	0	5	0	0
T84	0	31	0	0
T85	0	14	0	0
T86	0	8	0	0
T88	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	14304	0	0
T1	2652	4	0	0
T2	4585	4	0	0
T3	1511	0	0	0
T4	22478	23	0	0
T5	31286	34	0	0
T6	5832	0	0	0
T7	45217	75	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	4	0	0
T12	0	9	0	0
T13	0	25	0	0
T21	0	8	0	0
T23	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	1201	0	0
T12	7552	9	0	0
T13	32960	0	0	0
T14	2074	0	0	0
T21	3045	8	0	0
T22	5831	0	0	0
T23	2264	0	0	0
T24	3639	0	0	0
T25	6226	1	0	0
T56	0	8	0	0
T62	119549	9	0	0
T82	5969	0	0	0
T83	0	5	0	0
T84	0	31	0	0
T85	0	14	0	0
T86	0	8	0	0
T88	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	14342	0	0
T1	2652	4	0	0
T2	4585	4	0	0
T3	1511	0	0	0
T4	22478	23	0	0
T5	31286	34	0	0
T6	5832	0	0	0
T7	45217	75	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	4	0	0
T12	0	11	0	0
T13	0	25	0	0
T21	0	11	0	0
T23	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	1233	0	0
T12	7552	11	0	0
T13	32960	0	0	0
T14	2074	0	0	0
T21	3045	11	0	0
T22	5831	0	0	0
T23	2264	0	0	0
T24	3639	0	0	0
T25	6226	0	0	0
T56	0	12	0	0
T61	0	1	0	0
T62	119549	6	0	0
T82	5969	0	0	0
T83	0	6	0	0
T84	0	29	0	0
T85	0	14	0	0
T86	0	9	0	0
T88	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	14342	0	0
T1	2652	4	0	0
T2	4585	4	0	0
T3	1511	0	0	0
T4	22478	23	0	0
T5	31286	34	0	0
T6	5832	0	0	0
T7	45217	75	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	4	0	0
T12	0	11	0	0
T13	0	25	0	0
T21	0	11	0	0
T23	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	1233	0	0
T12	7552	11	0	0
T13	32960	0	0	0
T14	2074	0	0	0
T21	3045	11	0	0
T22	5831	0	0	0
T23	2264	0	0	0
T24	3639	0	0	0
T25	6226	0	0	0
T56	0	12	0	0
T61	0	1	0	0
T62	119549	6	0	0
T82	5969	0	0	0
T83	0	6	0	0
T84	0	29	0	0
T85	0	14	0	0
T86	0	9	0	0
T88	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	14371	0	0
T1	2652	4	0	0
T2	4585	5	0	0
T3	1511	0	0	0
T4	22478	23	0	0
T5	31286	34	0	0
T6	5832	0	0	0
T7	45217	75	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	4	0	0
T12	0	10	0	0
T13	0	25	0	0
T21	0	12	0	0
T23	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	1264	0	0
T2	4585	1	0	0
T3	1511	0	0	0
T4	22478	0	0	0
T5	31286	0	0	0
T6	5832	0	0	0
T7	45217	0	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	0	0	0
T11	5016	0	0	0
T12	0	10	0	0
T21	0	12	0	0
T56	0	13	0	0
T62	0	8	0	0
T83	0	3	0	0
T84	0	31	0	0
T85	0	9	0	0
T86	0	10	0	0
T88	0	8	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	14371	0	0
T1	2652	4	0	0
T2	4585	5	0	0
T3	1511	0	0	0
T4	22478	23	0	0
T5	31286	34	0	0
T6	5832	0	0	0
T7	45217	75	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	4	0	0
T12	0	10	0	0
T13	0	25	0	0
T21	0	12	0	0
T23	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	1264	0	0
T2	4585	1	0	0
T3	1511	0	0	0
T4	22478	0	0	0
T5	31286	0	0	0
T6	5832	0	0	0
T7	45217	0	0	0
T8	4638	0	0	0
T9	3801	0	0	0
T10	4334	0	0	0
T11	5016	0	0	0
T12	0	10	0	0
T21	0	12	0	0
T56	0	13	0	0
T62	0	8	0	0
T83	0	3	0	0
T84	0	31	0	0
T85	0	9	0	0
T86	0	10	0	0
T88	0	8	0	0