Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11991791	9345	0	0
alert_regwen_rd_A	11991791	5291	0	0
cpu_regwen_rd_A	11991791	5594	0	0
sw_rst_ctrl_n_0_rd_A	11991791	10390	0	0
sw_rst_ctrl_n_1_rd_A	11991791	10228	0	0
sw_rst_ctrl_n_2_rd_A	11991791	10261	0	0
sw_rst_ctrl_n_3_rd_A	11991791	10302	0	0
sw_rst_ctrl_n_4_rd_A	11991791	10285	0	0
sw_rst_ctrl_n_5_rd_A	11991791	10060	0	0
sw_rst_ctrl_n_6_rd_A	11991791	10218	0	0
sw_rst_ctrl_n_7_rd_A	11991791	10264	0	0
sw_rst_regwen_0_rd_A	11991791	6220	0	0
sw_rst_regwen_1_rd_A	11991791	6187	0	0
sw_rst_regwen_2_rd_A	11991791	6041	0	0
sw_rst_regwen_3_rd_A	11991791	5935	0	0
sw_rst_regwen_4_rd_A	11991791	5817	0	0
sw_rst_regwen_5_rd_A	11991791	6187	0	0
sw_rst_regwen_6_rd_A	11991791	6112	0	0
sw_rst_regwen_7_rd_A	11991791	6151	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	9345	0	0
T59	16626	2	0	0
T60	4635	12	0	0
T63	12286	582	0	0
T64	5606	184	0	0
T65	2412	175	0	0
T70	4371	82	0	0
T91	7053	233	0	0
T92	3941	494	0	0
T93	3021	103	0	0
T95	19806	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	5291	0	0
T5	27910	26	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	49	0	0
T14	2008	0	0	0
T43	0	424	0	0
T100	0	518	0	0
T101	0	64	0	0
T102	0	226	0	0
T104	0	53	0	0
T122	0	76	0	0
T123	0	35	0	0
T124	0	68	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	5594	0	0
T5	27910	6	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	29	0	0
T14	2008	0	0	0
T43	0	462	0	0
T100	0	569	0	0
T101	0	86	0	0
T102	0	279	0	0
T104	0	72	0	0
T122	0	71	0	0
T123	0	72	0	0
T124	0	71	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	10390	0	0
T5	27910	41	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	62	0	0
T14	2008	0	0	0
T25	0	10	0	0
T43	0	561	0	0
T47	0	179	0	0
T61	0	11	0	0
T87	0	15	0	0
T99	0	44	0	0
T125	0	16	0	0
T126	0	23	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	10228	0	0
T5	27910	30	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	28	0	0
T14	2008	0	0	0
T25	0	13	0	0
T43	0	540	0	0
T47	0	172	0	0
T61	0	7	0	0
T87	0	8	0	0
T99	0	33	0	0
T125	0	8	0	0
T126	0	12	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	10261	0	0
T5	27910	25	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	45	0	0
T14	2008	0	0	0
T25	0	12	0	0
T43	0	563	0	0
T47	0	169	0	0
T61	0	22	0	0
T87	0	14	0	0
T99	0	33	0	0
T125	0	1	0	0
T126	0	21	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	10302	0	0
T5	27910	20	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	28	0	0
T14	2008	0	0	0
T25	0	20	0	0
T43	0	608	0	0
T47	0	160	0	0
T61	0	12	0	0
T87	0	15	0	0
T99	0	50	0	0
T125	0	5	0	0
T126	0	9	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	10285	0	0
T5	27910	18	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	55	0	0
T14	2008	0	0	0
T25	0	8	0	0
T43	0	547	0	0
T47	0	177	0	0
T61	0	19	0	0
T87	0	21	0	0
T99	0	50	0	0
T125	0	14	0	0
T126	0	5	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	10060	0	0
T5	27910	45	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	26	0	0
T14	2008	0	0	0
T25	0	19	0	0
T43	0	569	0	0
T47	0	185	0	0
T61	0	19	0	0
T87	0	16	0	0
T99	0	36	0	0
T125	0	17	0	0
T126	0	15	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	10218	0	0
T5	27910	15	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	23	0	0
T14	2008	0	0	0
T25	0	6	0	0
T43	0	529	0	0
T47	0	202	0	0
T61	0	11	0	0
T87	0	18	0	0
T99	0	53	0	0
T125	0	15	0	0
T126	0	4	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	10264	0	0
T5	27910	20	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	9	0	0
T14	2008	0	0	0
T25	0	8	0	0
T43	0	513	0	0
T47	0	178	0	0
T61	0	24	0	0
T87	0	9	0	0
T99	0	46	0	0
T125	0	5	0	0
T126	0	18	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	6220	0	0
T5	27910	15	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	30	0	0
T14	2008	0	0	0
T25	0	11	0	0
T43	0	463	0	0
T47	0	22	0	0
T61	0	9	0	0
T87	0	13	0	0
T100	0	565	0	0
T125	0	2	0	0
T126	0	13	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	6187	0	0
T5	27910	32	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	29	0	0
T14	2008	0	0	0
T25	0	15	0	0
T43	0	464	0	0
T47	0	23	0	0
T61	0	7	0	0
T87	0	4	0	0
T100	0	568	0	0
T125	0	14	0	0
T126	0	12	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	6041	0	0
T5	27910	29	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	45	0	0
T14	2008	0	0	0
T25	0	7	0	0
T43	0	437	0	0
T47	0	35	0	0
T61	0	5	0	0
T87	0	7	0	0
T100	0	632	0	0
T125	0	4	0	0
T126	0	1	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	5935	0	0
T5	27910	40	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	35	0	0
T14	2008	0	0	0
T25	0	9	0	0
T43	0	407	0	0
T47	0	16	0	0
T61	0	12	0	0
T87	0	5	0	0
T100	0	529	0	0
T126	0	1	0	0
T127	0	32	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	5817	0	0
T5	27910	22	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	27	0	0
T14	2008	0	0	0
T25	0	5	0	0
T43	0	409	0	0
T47	0	13	0	0
T61	0	6	0	0
T87	0	7	0	0
T100	0	597	0	0
T125	0	6	0	0
T126	0	5	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	6187	0	0
T5	27910	12	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	43	0	0
T14	2008	0	0	0
T25	0	12	0	0
T43	0	420	0	0
T47	0	24	0	0
T61	0	8	0	0
T87	0	4	0	0
T100	0	562	0	0
T126	0	6	0	0
T127	0	34	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	6112	0	0
T5	27910	23	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	33	0	0
T14	2008	0	0	0
T25	0	4	0	0
T43	0	467	0	0
T47	0	36	0	0
T61	0	1	0	0
T87	0	3	0	0
T100	0	552	0	0
T125	0	8	0	0
T126	0	5	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11991791	6151	0	0
T5	27910	23	0	0
T6	5673	0	0	0
T7	42031	0	0	0
T8	4548	0	0	0
T9	3686	0	0	0
T10	4046	0	0	0
T11	4975	0	0	0
T12	7486	0	0	0
T13	28851	28	0	0
T14	2008	0	0	0
T25	0	12	0	0
T43	0	454	0	0
T47	0	41	0	0
T61	0	2	0	0
T87	0	5	0	0
T100	0	588	0	0
T125	0	1	0	0
T126	0	13	0	0