Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52685194	8499	0	0
CascadeEffAonToRstPorAboveRise_A	52685194	8499	0	0
CascadeEffAonToRstPorIoAboveFall_A	50576605	8499	0	0
CascadeEffAonToRstPorIoAboveRise_A	50576605	8499	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25289064	8499	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25289064	8499	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12644149	8499	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12644149	8499	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25289265	8499	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25289265	8499	0	0
CascadeLcToLcAboveFall_A	52685194	21643	0	0
CascadeLcToLcAboveRise_A	52685194	21643	0	0
CascadeLcToLcAonAboveFall_A	1597051	21643	0	0
CascadeLcToLcAonAboveRise_A	1597051	21643	0	0
CascadeLcToLcShadowedAboveFall_A	52685194	21643	0	0
CascadeLcToLcShadowedAboveRise_A	52685194	21643	0	0
CascadePorToAonAboveFall_A	1597051	6788	0	0
CascadeSysToSysAboveFall_A	52685194	21643	0	0
CascadeSysToSysAboveRise_A	52685194	21643	0	0
ScanRstToAonRise_A	1597051	210	0	0
StablePorToAonRise_A	1597051	8499	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11177150	21643	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11177150	21643	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11177150	21643	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11177150	21643	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12644149	21643	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12644149	21643	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11177150	21643	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11177150	21643	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11177150	21643	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11177150	21643	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52685194	8499	0	0
T1	11053	2	0	0
T2	19112	2	0	0
T3	6302	1	0	0
T4	93644	25	0	0
T5	130349	13	0	0
T6	24318	8	0	0
T7	188333	27	0	0
T8	19332	2	0	0
T9	15839	2	0	0
T10	18068	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52685194	8499	0	0
T1	11053	2	0	0
T2	19112	2	0	0
T3	6302	1	0	0
T4	93644	25	0	0
T5	130349	13	0	0
T6	24318	8	0	0
T7	188333	27	0	0
T8	19332	2	0	0
T9	15839	2	0	0
T10	18068	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50576605	8499	0	0
T1	10610	2	0	0
T2	18346	2	0	0
T3	6049	1	0	0
T4	89921	25	0	0
T5	125133	13	0	0
T6	23333	8	0	0
T7	180826	27	0	0
T8	18558	2	0	0
T9	15205	2	0	0
T10	17343	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50576605	8499	0	0
T1	10610	2	0	0
T2	18346	2	0	0
T3	6049	1	0	0
T4	89921	25	0	0
T5	125133	13	0	0
T6	23333	8	0	0
T7	180826	27	0	0
T8	18558	2	0	0
T9	15205	2	0	0
T10	17343	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289064	8499	0	0
T1	5306	2	0	0
T2	9171	2	0	0
T3	3024	1	0	0
T4	44960	25	0	0
T5	62567	13	0	0
T6	11665	8	0	0
T7	90405	27	0	0
T8	9279	2	0	0
T9	7603	2	0	0
T10	8671	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289064	8499	0	0
T1	5306	2	0	0
T2	9171	2	0	0
T3	3024	1	0	0
T4	44960	25	0	0
T5	62567	13	0	0
T6	11665	8	0	0
T7	90405	27	0	0
T8	9279	2	0	0
T9	7603	2	0	0
T10	8671	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	8499	0	0
T1	2652	2	0	0
T2	4585	2	0	0
T3	1511	1	0	0
T4	22478	25	0	0
T5	31286	13	0	0
T6	5832	8	0	0
T7	45217	27	0	0
T8	4638	2	0	0
T9	3801	2	0	0
T10	4334	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	8499	0	0
T1	2652	2	0	0
T2	4585	2	0	0
T3	1511	1	0	0
T4	22478	25	0	0
T5	31286	13	0	0
T6	5832	8	0	0
T7	45217	27	0	0
T8	4638	2	0	0
T9	3801	2	0	0
T10	4334	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289265	8499	0	0
T1	5303	2	0	0
T2	9173	2	0	0
T3	3024	1	0	0
T4	44962	25	0	0
T5	62565	13	0	0
T6	11662	8	0	0
T7	90405	27	0	0
T8	9279	2	0	0
T9	7602	2	0	0
T10	8669	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25289265	8499	0	0
T1	5303	2	0	0
T2	9173	2	0	0
T3	3024	1	0	0
T4	44962	25	0	0
T5	62565	13	0	0
T6	11662	8	0	0
T7	90405	27	0	0
T8	9279	2	0	0
T9	7602	2	0	0
T10	8669	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52685194	21643	0	0
T1	11053	6	0	0
T2	19112	6	0	0
T3	6302	1	0	0
T4	93644	48	0	0
T5	130349	47	0	0
T6	24318	8	0	0
T7	188333	102	0	0
T8	19332	2	0	0
T9	15839	2	0	0
T10	18068	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52685194	21643	0	0
T1	11053	6	0	0
T2	19112	6	0	0
T3	6302	1	0	0
T4	93644	48	0	0
T5	130349	47	0	0
T6	24318	8	0	0
T7	188333	102	0	0
T8	19332	2	0	0
T9	15839	2	0	0
T10	18068	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	21643	0	0
T1	331	6	0	0
T2	571	6	0	0
T3	188	1	0	0
T4	2835	48	0	0
T5	4003	47	0	0
T6	731	8	0	0
T7	5664	102	0	0
T8	578	2	0	0
T9	474	2	0	0
T10	541	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	21643	0	0
T1	331	6	0	0
T2	571	6	0	0
T3	188	1	0	0
T4	2835	48	0	0
T5	4003	47	0	0
T6	731	8	0	0
T7	5664	102	0	0
T8	578	2	0	0
T9	474	2	0	0
T10	541	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52685194	21643	0	0
T1	11053	6	0	0
T2	19112	6	0	0
T3	6302	1	0	0
T4	93644	48	0	0
T5	130349	47	0	0
T6	24318	8	0	0
T7	188333	102	0	0
T8	19332	2	0	0
T9	15839	2	0	0
T10	18068	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52685194	21643	0	0
T1	11053	6	0	0
T2	19112	6	0	0
T3	6302	1	0	0
T4	93644	48	0	0
T5	130349	47	0	0
T6	24318	8	0	0
T7	188333	102	0	0
T8	19332	2	0	0
T9	15839	2	0	0
T10	18068	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	6788	0	0
T1	331	1	0	0
T2	571	1	0	0
T3	188	1	0	0
T4	2835	12	0	0
T5	4003	6	0	0
T6	731	8	0	0
T7	5664	27	0	0
T8	578	20	0	0
T9	474	9	0	0
T10	541	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52685194	21643	0	0
T1	11053	6	0	0
T2	19112	6	0	0
T3	6302	1	0	0
T4	93644	48	0	0
T5	130349	47	0	0
T6	24318	8	0	0
T7	188333	102	0	0
T8	19332	2	0	0
T9	15839	2	0	0
T10	18068	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52685194	21643	0	0
T1	11053	6	0	0
T2	19112	6	0	0
T3	6302	1	0	0
T4	93644	48	0	0
T5	130349	47	0	0
T6	24318	8	0	0
T7	188333	102	0	0
T8	19332	2	0	0
T9	15839	2	0	0
T10	18068	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	210	0	0
T15	608	0	0	0
T43	0	7	0	0
T45	0	10	0	0
T56	992	0	0	0
T61	756	1	0	0
T62	15222	3	0	0
T69	214	0	0	0
T83	19563	7	0	0
T84	20121	6	0	0
T85	0	2	0	0
T89	0	11	0	0
T90	0	9	0	0
T96	3815	1	0	0
T98	733	0	0	0
T99	572	0	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1597051	8499	0	0
T1	331	2	0	0
T2	571	2	0	0
T3	188	1	0	0
T4	2835	25	0	0
T5	4003	13	0	0
T6	731	8	0	0
T7	5664	27	0	0
T8	578	2	0	0
T9	474	2	0	0
T10	541	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11177150	21643	0	0
T1	2413	6	0	0
T2	4349	6	0	0
T3	1493	1	0	0
T4	17905	48	0	0
T5	27910	47	0	0
T6	5673	8	0	0
T7	42031	102	0	0
T8	4548	2	0	0
T9	3686	2	0	0
T10	4046	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11177150	21643	0	0
T1	2413	6	0	0
T2	4349	6	0	0
T3	1493	1	0	0
T4	17905	48	0	0
T5	27910	47	0	0
T6	5673	8	0	0
T7	42031	102	0	0
T8	4548	2	0	0
T9	3686	2	0	0
T10	4046	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11177150	21643	0	0
T1	2413	6	0	0
T2	4349	6	0	0
T3	1493	1	0	0
T4	17905	48	0	0
T5	27910	47	0	0
T6	5673	8	0	0
T7	42031	102	0	0
T8	4548	2	0	0
T9	3686	2	0	0
T10	4046	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11177150	21643	0	0
T1	2413	6	0	0
T2	4349	6	0	0
T3	1493	1	0	0
T4	17905	48	0	0
T5	27910	47	0	0
T6	5673	8	0	0
T7	42031	102	0	0
T8	4548	2	0	0
T9	3686	2	0	0
T10	4046	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	21643	0	0
T1	2652	6	0	0
T2	4585	6	0	0
T3	1511	1	0	0
T4	22478	48	0	0
T5	31286	47	0	0
T6	5832	8	0	0
T7	45217	102	0	0
T8	4638	2	0	0
T9	3801	2	0	0
T10	4334	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644149	21643	0	0
T1	2652	6	0	0
T2	4585	6	0	0
T3	1511	1	0	0
T4	22478	48	0	0
T5	31286	47	0	0
T6	5832	8	0	0
T7	45217	102	0	0
T8	4638	2	0	0
T9	3801	2	0	0
T10	4334	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11177150	21643	0	0
T1	2413	6	0	0
T2	4349	6	0	0
T3	1493	1	0	0
T4	17905	48	0	0
T5	27910	47	0	0
T6	5673	8	0	0
T7	42031	102	0	0
T8	4548	2	0	0
T9	3686	2	0	0
T10	4046	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11177150	21643	0	0
T1	2413	6	0	0
T2	4349	6	0	0
T3	1493	1	0	0
T4	17905	48	0	0
T5	27910	47	0	0
T6	5673	8	0	0
T7	42031	102	0	0
T8	4548	2	0	0
T9	3686	2	0	0
T10	4046	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11177150	21643	0	0
T1	2413	6	0	0
T2	4349	6	0	0
T3	1493	1	0	0
T4	17905	48	0	0
T5	27910	47	0	0
T6	5673	8	0	0
T7	42031	102	0	0
T8	4548	2	0	0
T9	3686	2	0	0
T10	4046	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11177150	21643	0	0
T1	2413	6	0	0
T2	4349	6	0	0
T3	1493	1	0	0
T4	17905	48	0	0
T5	27910	47	0	0
T6	5673	8	0	0
T7	42031	102	0	0
T8	4548	2	0	0
T9	3686	2	0	0
T10	4046	6	0	0