Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	627532	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

379061

1

T1

2894

T2

299

T3

899

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	535924	1			T1	4206		T2	443		T3	1334
values[0x0]	235253	1			T1	1825		T2	208		T3	494
values[0x1]	235416	1			T1	1749		T2	189		T3	463

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	527162	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

479431

1

T1

3655

T2

369

T3

1107

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4361	1			T1	55		T4	1		T5	17
valid_sources[0x01]	4038	1			T1	11		T5	15		T9	4
valid_sources[0x02]	3763	1			T1	13		T5	21		T9	3
valid_sources[0x03]	4600	1			T1	42		T5	17		T13	1
valid_sources[0x04]	4192	1			T1	66		T4	4		T5	11
valid_sources[0x05]	3627	1			T1	19		T5	5		T9	5
valid_sources[0x06]	3925	1			T1	18		T5	18		T9	6
valid_sources[0x07]	3543	1			T1	14		T5	4		T9	1
valid_sources[0x08]	4018	1			T1	32		T5	30		T9	1
valid_sources[0x09]	3871	1			T1	31		T5	1		T9	5
valid_sources[0x0a]	7494	1			T1	48		T5	5		T9	5
valid_sources[0x0b]	2948	1			T1	35		T5	12		T9	1
valid_sources[0x0c]	3117	1			T1	33		T5	6		T9	3
valid_sources[0x0d]	4089	1			T1	25		T5	6		T9	3
valid_sources[0x0e]	3173	1			T1	19		T5	9		T9	3
valid_sources[0x0f]	5477	1			T1	54		T3	155		T5	8
valid_sources[0x10]	5292	1			T1	28		T5	4		T9	3
valid_sources[0x11]	3507	1			T1	32		T9	3		T13	1
valid_sources[0x12]	4716	1			T1	41		T5	3		T9	3
valid_sources[0x13]	4557	1			T1	28		T5	13		T9	6
valid_sources[0x14]	3689	1			T1	28		T5	28		T9	1
valid_sources[0x15]	4345	1			T1	78		T9	2		T12	2
valid_sources[0x16]	2933	1			T1	49		T4	2		T5	15
valid_sources[0x17]	3508	1			T1	42		T5	4		T9	4
valid_sources[0x18]	3638	1			T1	22		T9	1		T12	1
valid_sources[0x19]	3376	1			T1	48		T9	7		T57	32
valid_sources[0x1a]	4921	1			T1	10		T3	11		T5	17
valid_sources[0x1b]	4148	1			T1	14		T3	112		T5	2
valid_sources[0x1c]	4279	1			T1	27		T9	3		T11	1
valid_sources[0x1d]	4450	1			T1	47		T5	4		T9	2
valid_sources[0x1e]	3875	1			T1	19		T4	14		T5	17
valid_sources[0x1f]	7747	1			T1	53		T4	1		T5	7
valid_sources[0x20]	6443	1			T1	38		T9	2		T25	1
valid_sources[0x21]	4729	1			T1	28		T9	1		T13	3
valid_sources[0x22]	3574	1			T1	9		T5	16		T25	1
valid_sources[0x23]	4943	1			T1	35		T9	4		T56	3
valid_sources[0x24]	3350	1			T1	57		T4	15		T5	75
valid_sources[0x25]	2802	1			T1	18		T9	3		T57	12
valid_sources[0x26]	3172	1			T1	3		T4	4		T5	30
valid_sources[0x27]	4618	1			T1	25		T3	70		T5	17
valid_sources[0x28]	5449	1			T1	26		T5	37		T9	2
valid_sources[0x29]	3193	1			T1	27		T5	5		T11	1
valid_sources[0x2a]	3737	1			T1	15		T5	11		T9	5
valid_sources[0x2b]	3178	1			T1	12		T5	17		T9	2
valid_sources[0x2c]	3724	1			T1	31		T5	14		T9	1
valid_sources[0x2d]	3284	1			T1	50		T4	1		T5	11
valid_sources[0x2e]	5322	1			T1	31		T5	1		T9	9
valid_sources[0x2f]	4147	1			T1	56		T5	55		T9	6
valid_sources[0x30]	3129	1			T1	1		T5	19		T9	1
valid_sources[0x31]	3443	1			T1	39		T5	17		T9	1
valid_sources[0x32]	4626	1			T1	9		T9	2		T11	1
valid_sources[0x33]	5632	1			T1	25		T5	3		T9	5
valid_sources[0x34]	3407	1			T1	8		T9	3		T12	3
valid_sources[0x35]	4786	1			T1	18		T9	8		T25	3
valid_sources[0x36]	2961	1			T1	43		T4	1		T5	7
valid_sources[0x37]	3177	1			T1	60		T5	32		T9	2
valid_sources[0x38]	2877	1			T1	39		T11	2		T57	4
valid_sources[0x39]	4153	1			T1	49		T5	16		T9	3
valid_sources[0x3a]	3115	1			T1	24		T5	34		T9	9
valid_sources[0x3b]	3794	1			T1	15		T9	4		T11	1
valid_sources[0x3c]	3486	1			T1	79		T9	6		T57	9
valid_sources[0x3d]	3150	1			T1	30		T5	7		T9	4
valid_sources[0x3e]	3237	1			T1	51		T9	10		T11	1
valid_sources[0x3f]	2966	1			T1	69		T9	2		T11	1
valid_sources[0x40]	3296	1			T1	17		T5	34		T9	6
valid_sources[0x41]	3562	1			T1	41		T9	8		T11	1
valid_sources[0x42]	3143	1			T1	23		T4	2		T5	13
valid_sources[0x43]	2900	1			T1	35		T9	3		T25	1
valid_sources[0x44]	4276	1			T1	28		T4	3		T9	5
valid_sources[0x45]	3644	1			T1	13		T5	6		T9	6
valid_sources[0x46]	4068	1			T1	53		T9	2		T12	2
valid_sources[0x47]	3000	1			T1	74		T5	11		T9	1
valid_sources[0x48]	3243	1			T1	23		T9	3		T11	2
valid_sources[0x49]	4384	1			T1	23		T4	6		T5	11
valid_sources[0x4a]	3766	1			T1	43		T9	2		T12	6
valid_sources[0x4b]	5222	1			T1	14		T3	424		T5	14
valid_sources[0x4c]	3017	1			T1	28		T5	36		T9	4
valid_sources[0x4d]	7269	1			T1	29		T5	9		T11	2
valid_sources[0x4e]	3339	1			T1	17		T5	18		T9	3
valid_sources[0x4f]	4071	1			T1	63		T5	6		T9	3
valid_sources[0x50]	4484	1			T1	24		T5	3		T9	4
valid_sources[0x51]	3503	1			T1	45		T5	19		T9	5
valid_sources[0x52]	4929	1			T1	32		T56	238		T57	8
valid_sources[0x53]	3344	1			T1	26		T5	9		T9	1
valid_sources[0x54]	4157	1			T1	25		T5	14		T9	2
valid_sources[0x55]	4496	1			T1	30		T3	113		T5	15
valid_sources[0x56]	3019	1			T1	25		T5	37		T9	1
valid_sources[0x57]	3403	1			T1	17		T5	7		T11	2
valid_sources[0x58]	4148	1			T1	32		T5	12		T9	9
valid_sources[0x59]	2851	1			T1	30		T4	15		T5	16
valid_sources[0x5a]	3738	1			T1	22		T5	20		T9	1
valid_sources[0x5b]	4383	1			T1	7		T5	19		T9	2
valid_sources[0x5c]	3879	1			T1	29		T5	27		T9	1
valid_sources[0x5d]	3168	1			T1	34		T5	23		T11	2
valid_sources[0x5e]	3298	1			T1	55		T5	29		T9	1
valid_sources[0x5f]	2851	1			T1	29		T9	3		T11	1
valid_sources[0x60]	4091	1			T1	21		T4	62		T5	7
valid_sources[0x61]	4649	1			T1	24		T5	9		T12	3
valid_sources[0x62]	3463	1			T1	32		T5	3		T11	1
valid_sources[0x63]	4979	1			T1	29		T5	1		T9	1
valid_sources[0x64]	3587	1			T1	23		T4	2		T5	4
valid_sources[0x65]	6384	1			T1	33		T5	11		T9	1
valid_sources[0x66]	4571	1			T1	19		T2	840		T3	197
valid_sources[0x67]	2860	1			T1	21		T5	10		T9	4
valid_sources[0x68]	3919	1			T1	42		T5	13		T9	3
valid_sources[0x69]	3785	1			T1	35		T5	21		T9	8
valid_sources[0x6a]	3641	1			T1	39		T3	197		T5	13
valid_sources[0x6b]	3511	1			T1	17		T5	25		T9	1
valid_sources[0x6c]	3026	1			T1	48		T5	49		T9	5
valid_sources[0x6d]	3463	1			T1	45		T9	3		T12	3
valid_sources[0x6e]	3042	1			T1	15		T5	34		T6	212
valid_sources[0x6f]	2913	1			T1	59		T5	32		T11	2
valid_sources[0x70]	3622	1			T1	26		T5	6		T9	6
valid_sources[0x71]	3075	1			T1	17		T5	6		T9	3
valid_sources[0x72]	3456	1			T1	74		T9	6		T25	2
valid_sources[0x73]	4073	1			T1	51		T5	16		T9	5
valid_sources[0x74]	3352	1			T1	15		T5	11		T9	1
valid_sources[0x75]	3557	1			T1	25		T9	3		T12	1
valid_sources[0x76]	3730	1			T1	27		T5	12		T9	1
valid_sources[0x77]	3961	1			T1	14		T5	2		T9	2
valid_sources[0x78]	4236	1			T1	13		T4	6		T5	17
valid_sources[0x79]	3270	1			T1	17		T5	1		T57	25
valid_sources[0x7a]	3986	1			T1	29		T5	34		T9	2
valid_sources[0x7b]	3410	1			T1	40		T5	3		T9	3
valid_sources[0x7c]	5010	1			T1	21		T5	14		T11	1
valid_sources[0x7d]	4011	1			T1	11		T9	5		T13	1
valid_sources[0x7e]	4086	1			T1	25		T5	7		T9	2
valid_sources[0x7f]	3801	1			T1	30		T5	21		T11	2
valid_sources[0x80]	3155	1			T1	16		T9	6		T57	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

252456

1

T1

1978

T2

206

T3

642

values[0x0]

all_enables

biggest_size

82505

1

T1

625

T2

55

T3

174

values[0x1]

all_enables

biggest_size

44100

1

T1

291

T2

38

T3

83