Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T9
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12898623	14330	0	0
gen_assertions[0].RstEnOn_A	12898623	1148	0	0
gen_assertions[0].RstNOff_A	12898623	14330	0	0
gen_assertions[0].RstNOn_A	12898623	1148	0	0
gen_assertions[1].RstEnOff_A	51593772	13078	0	0
gen_assertions[1].RstEnOn_A	51593772	1110	0	0
gen_assertions[1].RstNOff_A	51593772	13078	0	0
gen_assertions[1].RstNOn_A	51593772	1110	0	0
gen_assertions[2].RstEnOff_A	25797675	13120	0	0
gen_assertions[2].RstEnOn_A	25797675	1100	0	0
gen_assertions[2].RstNOff_A	25797675	13120	0	0
gen_assertions[2].RstNOn_A	25797675	1100	0	0
gen_assertions[3].RstEnOff_A	25797793	13179	0	0
gen_assertions[3].RstEnOn_A	25797793	1162	0	0
gen_assertions[3].RstNOff_A	25797793	13179	0	0
gen_assertions[3].RstNOn_A	25797793	1162	0	0
gen_assertions[4].RstEnOff_A	1628529	21734	0	0
gen_assertions[4].RstEnOn_A	1628529	1195	0	0
gen_assertions[4].RstNOff_A	1628529	21734	0	0
gen_assertions[4].RstNOn_A	1628529	1195	0	0
gen_assertions[5].RstEnOff_A	12898623	14560	0	0
gen_assertions[5].RstEnOn_A	12898623	1242	0	0
gen_assertions[5].RstNOff_A	12898623	14560	0	0
gen_assertions[5].RstNOn_A	12898623	1242	0	0
gen_assertions[6].RstEnOff_A	12898623	14647	0	0
gen_assertions[6].RstEnOn_A	12898623	1323	0	0
gen_assertions[6].RstNOff_A	12898623	14647	0	0
gen_assertions[6].RstNOn_A	12898623	1323	0	0
gen_assertions[7].RstEnOff_A	12898623	14693	0	0
gen_assertions[7].RstEnOn_A	12898623	1383	0	0
gen_assertions[7].RstNOff_A	12898623	14693	0	0
gen_assertions[7].RstNOn_A	12898623	1383	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	14330	0	0
T1	59502	112	0	0
T2	7123	3	0	0
T3	30144	24	0	0
T4	2479	4	0	0
T5	45343	75	0	0
T6	3427	4	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	3	0	0
T10	2246	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T13	0	7	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	1148	0	0
T1	59502	22	0	0
T2	7123	3	0	0
T3	30144	0	0	0
T4	2479	0	0	0
T5	45343	0	0	0
T6	3427	0	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	3	0	0
T10	2246	0	0	0
T11	0	1	0	0
T12	0	6	0	0
T13	0	1	0	0
T23	0	8	0	0
T48	0	3	0	0
T56	0	31	0	0
T107	0	8	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	14330	0	0
T1	59502	112	0	0
T2	7123	3	0	0
T3	30144	24	0	0
T4	2479	4	0	0
T5	45343	75	0	0
T6	3427	4	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	3	0	0
T10	2246	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T13	0	7	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	1148	0	0
T1	59502	22	0	0
T2	7123	3	0	0
T3	30144	0	0	0
T4	2479	0	0	0
T5	45343	0	0	0
T6	3427	0	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	3	0	0
T10	2246	0	0	0
T11	0	1	0	0
T12	0	6	0	0
T13	0	1	0	0
T23	0	8	0	0
T48	0	3	0	0
T56	0	31	0	0
T107	0	8	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51593772	13078	0	0
T1	237967	96	0	0
T2	28495	5	0	0
T3	120585	23	0	0
T4	9920	4	0	0
T5	181391	69	0	0
T6	13713	4	0	0
T7	23454	0	0	0
T8	17108	0	0	0
T9	11668	2	0	0
T10	8988	0	0	0
T11	0	9	0	0
T12	0	13	0	0
T13	0	7	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51593772	1110	0	0
T1	237967	20	0	0
T2	28495	5	0	0
T3	120585	0	0	0
T4	9920	0	0	0
T5	181391	0	0	0
T6	13713	0	0	0
T7	23454	0	0	0
T8	17108	0	0	0
T9	11668	2	0	0
T10	8988	0	0	0
T12	0	3	0	0
T13	0	1	0	0
T23	0	7	0	0
T48	0	3	0	0
T50	0	6	0	0
T56	0	28	0	0
T107	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51593772	13078	0	0
T1	237967	96	0	0
T2	28495	5	0	0
T3	120585	23	0	0
T4	9920	4	0	0
T5	181391	69	0	0
T6	13713	4	0	0
T7	23454	0	0	0
T8	17108	0	0	0
T9	11668	2	0	0
T10	8988	0	0	0
T11	0	9	0	0
T12	0	13	0	0
T13	0	7	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51593772	1110	0	0
T1	237967	20	0	0
T2	28495	5	0	0
T3	120585	0	0	0
T4	9920	0	0	0
T5	181391	0	0	0
T6	13713	0	0	0
T7	23454	0	0	0
T8	17108	0	0	0
T9	11668	2	0	0
T10	8988	0	0	0
T12	0	3	0	0
T13	0	1	0	0
T23	0	7	0	0
T48	0	3	0	0
T50	0	6	0	0
T56	0	28	0	0
T107	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797675	13120	0	0
T1	118968	93	0	0
T2	14247	3	0	0
T3	60287	23	0	0
T4	4959	4	0	0
T5	90695	69	0	0
T6	6856	4	0	0
T7	11717	0	0	0
T8	8554	0	0	0
T9	5833	4	0	0
T10	4494	0	0	0
T11	0	9	0	0
T12	0	13	0	0
T13	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797675	1100	0	0
T1	118968	18	0	0
T2	14247	3	0	0
T3	60287	0	0	0
T4	4959	0	0	0
T5	90695	0	0	0
T6	6856	0	0	0
T7	11717	0	0	0
T8	8554	0	0	0
T9	5833	4	0	0
T10	4494	0	0	0
T12	0	1	0	0
T23	0	9	0	0
T48	0	4	0	0
T53	0	1	0	0
T55	0	12	0	0
T56	0	34	0	0
T108	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797675	13120	0	0
T1	118968	93	0	0
T2	14247	3	0	0
T3	60287	23	0	0
T4	4959	4	0	0
T5	90695	69	0	0
T6	6856	4	0	0
T7	11717	0	0	0
T8	8554	0	0	0
T9	5833	4	0	0
T10	4494	0	0	0
T11	0	9	0	0
T12	0	13	0	0
T13	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797675	1100	0	0
T1	118968	18	0	0
T2	14247	3	0	0
T3	60287	0	0	0
T4	4959	0	0	0
T5	90695	0	0	0
T6	6856	0	0	0
T7	11717	0	0	0
T8	8554	0	0	0
T9	5833	4	0	0
T10	4494	0	0	0
T12	0	1	0	0
T23	0	9	0	0
T48	0	4	0	0
T53	0	1	0	0
T55	0	12	0	0
T56	0	34	0	0
T108	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797793	13179	0	0
T1	118984	96	0	0
T2	14247	7	0	0
T3	60280	23	0	0
T4	4957	4	0	0
T5	90702	69	0	0
T6	6857	4	0	0
T7	11724	0	0	0
T8	8554	0	0	0
T9	5834	6	0	0
T10	4494	0	0	0
T11	0	9	0	0
T12	0	13	0	0
T13	0	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797793	1162	0	0
T1	118984	21	0	0
T2	14247	7	0	0
T3	60280	0	0	0
T4	4957	0	0	0
T5	90702	0	0	0
T6	6857	0	0	0
T7	11724	0	0	0
T8	8554	0	0	0
T9	5834	6	0	0
T10	4494	0	0	0
T23	0	8	0	0
T37	0	9	0	0
T42	0	7	0	0
T48	0	6	0	0
T55	0	11	0	0
T56	0	29	0	0
T109	0	10	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797793	13179	0	0
T1	118984	96	0	0
T2	14247	7	0	0
T3	60280	23	0	0
T4	4957	4	0	0
T5	90702	69	0	0
T6	6857	4	0	0
T7	11724	0	0	0
T8	8554	0	0	0
T9	5834	6	0	0
T10	4494	0	0	0
T11	0	9	0	0
T12	0	13	0	0
T13	0	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797793	1162	0	0
T1	118984	21	0	0
T2	14247	7	0	0
T3	60280	0	0	0
T4	4957	0	0	0
T5	90702	0	0	0
T6	6857	0	0	0
T7	11724	0	0	0
T8	8554	0	0	0
T9	5834	6	0	0
T10	4494	0	0	0
T23	0	8	0	0
T37	0	9	0	0
T42	0	7	0	0
T48	0	6	0	0
T55	0	11	0	0
T56	0	29	0	0
T109	0	10	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	21734	0	0
T1	7611	152	0	0
T2	889	9	0	0
T3	3795	43	0	0
T4	308	5	0	0
T5	5683	90	0	0
T6	428	5	0	0
T7	734	3	0	0
T8	533	2	0	0
T9	363	6	0	0
T10	279	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	1195	0	0
T1	7611	21	0	0
T2	889	8	0	0
T3	3795	0	0	0
T4	308	0	0	0
T5	5683	0	0	0
T6	428	0	0	0
T7	734	0	0	0
T8	533	0	0	0
T9	363	5	0	0
T10	279	0	0	0
T23	0	8	0	0
T37	0	10	0	0
T42	0	7	0	0
T48	0	7	0	0
T53	0	1	0	0
T55	0	9	0	0
T56	0	31	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	21734	0	0
T1	7611	152	0	0
T2	889	9	0	0
T3	3795	43	0	0
T4	308	5	0	0
T5	5683	90	0	0
T6	428	5	0	0
T7	734	3	0	0
T8	533	2	0	0
T9	363	6	0	0
T10	279	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	1195	0	0
T1	7611	21	0	0
T2	889	8	0	0
T3	3795	0	0	0
T4	308	0	0	0
T5	5683	0	0	0
T6	428	0	0	0
T7	734	0	0	0
T8	533	0	0	0
T9	363	5	0	0
T10	279	0	0	0
T23	0	8	0	0
T37	0	10	0	0
T42	0	7	0	0
T48	0	7	0	0
T53	0	1	0	0
T55	0	9	0	0
T56	0	31	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	14560	0	0
T1	59502	113	0	0
T2	7123	8	0	0
T3	30144	24	0	0
T4	2479	4	0	0
T5	45343	75	0	0
T6	3427	4	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	8	0	0
T10	2246	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T13	0	7	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	1242	0	0
T1	59502	23	0	0
T2	7123	8	0	0
T3	30144	0	0	0
T4	2479	0	0	0
T5	45343	0	0	0
T6	3427	0	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	8	0	0
T10	2246	0	0	0
T23	0	6	0	0
T37	0	11	0	0
T42	0	9	0	0
T48	0	7	0	0
T55	0	10	0	0
T56	0	31	0	0
T109	0	10	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	14560	0	0
T1	59502	113	0	0
T2	7123	8	0	0
T3	30144	24	0	0
T4	2479	4	0	0
T5	45343	75	0	0
T6	3427	4	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	8	0	0
T10	2246	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T13	0	7	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	1242	0	0
T1	59502	23	0	0
T2	7123	8	0	0
T3	30144	0	0	0
T4	2479	0	0	0
T5	45343	0	0	0
T6	3427	0	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	8	0	0
T10	2246	0	0	0
T23	0	6	0	0
T37	0	11	0	0
T42	0	9	0	0
T48	0	7	0	0
T55	0	10	0	0
T56	0	31	0	0
T109	0	10	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	14647	0	0
T1	59502	110	0	0
T2	7123	9	0	0
T3	30144	24	0	0
T4	2479	4	0	0
T5	45343	75	0	0
T6	3427	4	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	9	0	0
T10	2246	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T13	0	7	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	1323	0	0
T1	59502	20	0	0
T2	7123	9	0	0
T3	30144	0	0	0
T4	2479	0	0	0
T5	45343	0	0	0
T6	3427	0	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	9	0	0
T10	2246	0	0	0
T23	0	5	0	0
T37	0	11	0	0
T48	0	8	0	0
T53	0	1	0	0
T55	0	8	0	0
T56	0	36	0	0
T108	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	14647	0	0
T1	59502	110	0	0
T2	7123	9	0	0
T3	30144	24	0	0
T4	2479	4	0	0
T5	45343	75	0	0
T6	3427	4	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	9	0	0
T10	2246	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T13	0	7	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	1323	0	0
T1	59502	20	0	0
T2	7123	9	0	0
T3	30144	0	0	0
T4	2479	0	0	0
T5	45343	0	0	0
T6	3427	0	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	9	0	0
T10	2246	0	0	0
T23	0	5	0	0
T37	0	11	0	0
T48	0	8	0	0
T53	0	1	0	0
T55	0	8	0	0
T56	0	36	0	0
T108	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	14693	0	0
T1	59502	112	0	0
T2	7123	11	0	0
T3	30144	24	0	0
T4	2479	4	0	0
T5	45343	75	0	0
T6	3427	4	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	9	0	0
T10	2246	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T13	0	7	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	1383	0	0
T1	59502	23	0	0
T2	7123	11	0	0
T3	30144	0	0	0
T4	2479	0	0	0
T5	45343	0	0	0
T6	3427	0	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	9	0	0
T10	2246	0	0	0
T23	0	9	0	0
T37	0	12	0	0
T42	0	11	0	0
T48	0	10	0	0
T55	0	10	0	0
T56	0	27	0	0
T109	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	14693	0	0
T1	59502	112	0	0
T2	7123	11	0	0
T3	30144	24	0	0
T4	2479	4	0	0
T5	45343	75	0	0
T6	3427	4	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	9	0	0
T10	2246	0	0	0
T11	0	9	0	0
T12	0	14	0	0
T13	0	7	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	1383	0	0
T1	59502	23	0	0
T2	7123	11	0	0
T3	30144	0	0	0
T4	2479	0	0	0
T5	45343	0	0	0
T6	3427	0	0	0
T7	5866	0	0	0
T8	4277	0	0	0
T9	2916	9	0	0
T10	2246	0	0	0
T23	0	9	0	0
T37	0	12	0	0
T42	0	11	0	0
T48	0	10	0	0
T55	0	10	0	0
T56	0	27	0	0
T109	0	13	0	0