Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12236623	7983	0	0
alert_regwen_rd_A	12236623	6474	0	0
cpu_regwen_rd_A	12236623	6453	0	0
sw_rst_ctrl_n_0_rd_A	12236623	11073	0	0
sw_rst_ctrl_n_1_rd_A	12236623	11276	0	0
sw_rst_ctrl_n_2_rd_A	12236623	10640	0	0
sw_rst_ctrl_n_3_rd_A	12236623	10912	0	0
sw_rst_ctrl_n_4_rd_A	12236623	10689	0	0
sw_rst_ctrl_n_5_rd_A	12236623	11203	0	0
sw_rst_ctrl_n_6_rd_A	12236623	10724	0	0
sw_rst_ctrl_n_7_rd_A	12236623	10926	0	0
sw_rst_regwen_0_rd_A	12236623	6834	0	0
sw_rst_regwen_1_rd_A	12236623	7013	0	0
sw_rst_regwen_2_rd_A	12236623	7031	0	0
sw_rst_regwen_3_rd_A	12236623	6919	0	0
sw_rst_regwen_4_rd_A	12236623	6809	0	0
sw_rst_regwen_5_rd_A	12236623	6870	0	0
sw_rst_regwen_6_rd_A	12236623	6625	0	0
sw_rst_regwen_7_rd_A	12236623	7070	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	7983	0	0
T65	17992	1	0	0
T66	4287	87	0	0
T67	3808	334	0	0
T68	2716	9	0	0
T83	5769	202	0	0
T84	5208	301	0	0
T85	12932	3	0	0
T86	10236	1	0	0
T88	11949	1	0	0
T91	4039	73	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	6474	0	0
T27	42244	0	0	0
T45	53353	0	0	0
T111	129157	137	0	0
T112	17523	0	0	0
T113	41041	47	0	0
T114	156061	0	0	0
T115	0	38	0	0
T117	0	219	0	0
T120	0	409	0	0
T134	0	294	0	0
T135	0	120	0	0
T136	0	49	0	0
T137	0	65	0	0
T138	0	34	0	0
T139	3598	0	0	0
T140	5461	0	0	0
T141	3955	0	0	0
T142	2914	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	6453	0	0
T27	42244	0	0	0
T45	53353	0	0	0
T111	129157	106	0	0
T112	17523	0	0	0
T113	41041	68	0	0
T114	156061	0	0	0
T115	0	42	0	0
T117	0	223	0	0
T120	0	322	0	0
T134	0	262	0	0
T135	0	139	0	0
T136	0	43	0	0
T137	0	45	0	0
T138	0	39	0	0
T139	3598	0	0	0
T140	5461	0	0	0
T141	3955	0	0	0
T142	2914	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	11073	0	0
T11	3232	17	0	0
T12	2185	0	0	0
T13	2437	0	0	0
T14	4797	0	0	0
T22	5332	0	0	0
T23	11283	0	0	0
T24	1335	0	0	0
T25	3395	0	0	0
T48	0	156	0	0
T53	0	15	0	0
T56	102247	0	0	0
T107	2600	0	0	0
T111	0	226	0	0
T113	0	33	0	0
T115	0	408	0	0
T117	0	353	0	0
T139	0	36	0	0
T143	0	152	0	0
T144	0	21	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	11276	0	0
T11	3232	32	0	0
T12	2185	0	0	0
T13	2437	0	0	0
T14	4797	0	0	0
T22	5332	0	0	0
T23	11283	0	0	0
T24	1335	0	0	0
T25	3395	0	0	0
T48	0	113	0	0
T53	0	17	0	0
T56	102247	0	0	0
T107	2600	0	0	0
T111	0	205	0	0
T113	0	61	0	0
T115	0	348	0	0
T117	0	382	0	0
T139	0	28	0	0
T143	0	143	0	0
T144	0	26	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	10640	0	0
T11	3232	38	0	0
T12	2185	0	0	0
T13	2437	0	0	0
T14	4797	0	0	0
T22	5332	0	0	0
T23	11283	0	0	0
T24	1335	0	0	0
T25	3395	0	0	0
T48	0	135	0	0
T53	0	18	0	0
T56	102247	0	0	0
T107	2600	0	0	0
T111	0	203	0	0
T113	0	63	0	0
T115	0	405	0	0
T117	0	389	0	0
T139	0	17	0	0
T143	0	142	0	0
T144	0	18	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	10912	0	0
T11	3232	16	0	0
T12	2185	0	0	0
T13	2437	0	0	0
T14	4797	0	0	0
T22	5332	0	0	0
T23	11283	0	0	0
T24	1335	0	0	0
T25	3395	0	0	0
T48	0	176	0	0
T53	0	18	0	0
T56	102247	0	0	0
T107	2600	0	0	0
T111	0	187	0	0
T113	0	42	0	0
T115	0	362	0	0
T117	0	415	0	0
T139	0	11	0	0
T143	0	152	0	0
T144	0	39	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	10689	0	0
T11	3232	11	0	0
T12	2185	0	0	0
T13	2437	0	0	0
T14	4797	0	0	0
T22	5332	0	0	0
T23	11283	0	0	0
T24	1335	0	0	0
T25	3395	0	0	0
T48	0	130	0	0
T53	0	12	0	0
T56	102247	0	0	0
T107	2600	0	0	0
T111	0	204	0	0
T113	0	50	0	0
T115	0	383	0	0
T117	0	406	0	0
T139	0	18	0	0
T143	0	160	0	0
T144	0	27	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	11203	0	0
T11	3232	4	0	0
T12	2185	0	0	0
T13	2437	0	0	0
T14	4797	0	0	0
T22	5332	0	0	0
T23	11283	0	0	0
T24	1335	0	0	0
T25	3395	0	0	0
T48	0	163	0	0
T53	0	22	0	0
T56	102247	0	0	0
T107	2600	0	0	0
T111	0	225	0	0
T113	0	60	0	0
T115	0	390	0	0
T117	0	430	0	0
T139	0	51	0	0
T143	0	152	0	0
T144	0	26	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	10724	0	0
T11	3232	17	0	0
T12	2185	0	0	0
T13	2437	0	0	0
T14	4797	0	0	0
T22	5332	0	0	0
T23	11283	0	0	0
T24	1335	0	0	0
T25	3395	0	0	0
T48	0	196	0	0
T53	0	7	0	0
T56	102247	0	0	0
T107	2600	0	0	0
T111	0	215	0	0
T113	0	31	0	0
T115	0	386	0	0
T117	0	355	0	0
T139	0	18	0	0
T143	0	131	0	0
T144	0	22	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	10926	0	0
T11	3232	36	0	0
T12	2185	0	0	0
T13	2437	0	0	0
T14	4797	0	0	0
T22	5332	0	0	0
T23	11283	0	0	0
T24	1335	0	0	0
T25	3395	0	0	0
T48	0	157	0	0
T53	0	11	0	0
T56	102247	0	0	0
T107	2600	0	0	0
T111	0	171	0	0
T113	0	35	0	0
T115	0	423	0	0
T117	0	356	0	0
T139	0	15	0	0
T143	0	167	0	0
T144	0	28	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	6834	0	0
T48	9769	27	0	0
T49	4245	0	0	0
T50	2443	0	0	0
T51	1647	0	0	0
T52	2643	0	0	0
T53	5890	5	0	0
T54	5687	0	0	0
T55	40930	0	0	0
T74	0	7	0	0
T75	0	38	0	0
T106	5080	0	0	0
T108	4480	0	0	0
T111	0	96	0	0
T113	0	63	0	0
T115	0	48	0	0
T117	0	231	0	0
T143	0	22	0	0
T145	0	23	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	7013	0	0
T48	9769	21	0	0
T49	4245	0	0	0
T50	2443	0	0	0
T51	1647	0	0	0
T52	2643	0	0	0
T53	5890	8	0	0
T54	5687	0	0	0
T55	40930	0	0	0
T74	0	2	0	0
T75	0	19	0	0
T106	5080	0	0	0
T108	4480	0	0	0
T111	0	126	0	0
T113	0	45	0	0
T115	0	43	0	0
T117	0	249	0	0
T143	0	38	0	0
T145	0	16	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	7031	0	0
T48	9769	18	0	0
T49	4245	0	0	0
T50	2443	0	0	0
T51	1647	0	0	0
T52	2643	0	0	0
T53	5890	3	0	0
T54	5687	0	0	0
T55	40930	0	0	0
T74	0	9	0	0
T75	0	37	0	0
T106	5080	0	0	0
T108	4480	0	0	0
T111	0	100	0	0
T113	0	41	0	0
T115	0	40	0	0
T117	0	224	0	0
T143	0	37	0	0
T145	0	10	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	6919	0	0
T48	9769	37	0	0
T49	4245	0	0	0
T50	2443	0	0	0
T51	1647	0	0	0
T52	2643	0	0	0
T53	5890	4	0	0
T54	5687	0	0	0
T55	40930	0	0	0
T74	0	5	0	0
T75	0	30	0	0
T106	5080	0	0	0
T108	4480	0	0	0
T111	0	112	0	0
T113	0	63	0	0
T115	0	47	0	0
T117	0	174	0	0
T143	0	45	0	0
T145	0	29	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	6809	0	0
T48	9769	26	0	0
T49	4245	0	0	0
T50	2443	0	0	0
T51	1647	0	0	0
T52	2643	0	0	0
T53	5890	7	0	0
T54	5687	0	0	0
T55	40930	0	0	0
T74	0	6	0	0
T75	0	33	0	0
T106	5080	0	0	0
T108	4480	0	0	0
T111	0	106	0	0
T113	0	60	0	0
T115	0	36	0	0
T117	0	205	0	0
T143	0	23	0	0
T145	0	25	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	6870	0	0
T48	9769	37	0	0
T49	4245	0	0	0
T50	2443	0	0	0
T51	1647	0	0	0
T52	2643	0	0	0
T53	5890	9	0	0
T54	5687	0	0	0
T55	40930	0	0	0
T74	0	12	0	0
T75	0	34	0	0
T106	5080	0	0	0
T108	4480	0	0	0
T111	0	141	0	0
T113	0	27	0	0
T115	0	44	0	0
T117	0	207	0	0
T143	0	28	0	0
T145	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	6625	0	0
T48	9769	25	0	0
T49	4245	0	0	0
T50	2443	0	0	0
T51	1647	0	0	0
T52	2643	0	0	0
T53	5890	7	0	0
T54	5687	0	0	0
T55	40930	0	0	0
T74	0	11	0	0
T75	0	28	0	0
T106	5080	0	0	0
T108	4480	0	0	0
T111	0	67	0	0
T113	0	58	0	0
T115	0	30	0	0
T117	0	244	0	0
T143	0	36	0	0
T145	0	8	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12236623	7070	0	0
T48	9769	43	0	0
T49	4245	0	0	0
T50	2443	0	0	0
T51	1647	0	0	0
T52	2643	0	0	0
T53	5890	8	0	0
T54	5687	0	0	0
T55	40930	0	0	0
T74	0	9	0	0
T75	0	36	0	0
T106	5080	0	0	0
T108	4480	0	0	0
T111	0	118	0	0
T113	0	35	0	0
T115	0	36	0	0
T117	0	225	0	0
T143	0	29	0	0
T145	0	13	0	0