Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T56
1	0	Covered	T1,T3,T23

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53745326	8373	0	0
CascadeEffAonToRstPorAboveRise_A	53745326	8373	0	0
CascadeEffAonToRstPorIoAboveFall_A	51593772	8373	0	0
CascadeEffAonToRstPorIoAboveRise_A	51593772	8373	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25797675	8373	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25797675	8373	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12898623	8373	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12898623	8373	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25797793	8373	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25797793	8373	0	0
CascadeLcToLcAboveFall_A	53745326	21736	0	0
CascadeLcToLcAboveRise_A	53745326	21736	0	0
CascadeLcToLcAonAboveFall_A	1628529	21736	0	0
CascadeLcToLcAonAboveRise_A	1628529	21736	0	0
CascadeLcToLcShadowedAboveFall_A	53745326	21736	0	0
CascadeLcToLcShadowedAboveRise_A	53745326	21736	0	0
CascadePorToAonAboveFall_A	1628529	6650	0	0
CascadeSysToSysAboveFall_A	53745326	21736	0	0
CascadeSysToSysAboveRise_A	53745326	21736	0	0
ScanRstToAonRise_A	1628529	225	0	0
StablePorToAonRise_A	1628529	8373	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11394841	21736	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11394841	21736	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11394841	21736	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11394841	21736	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12898623	21736	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12898623	21736	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11394841	21736	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11394841	21736	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11394841	21736	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11394841	21736	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53745326	8373	0	0
T1	247919	48	0	0
T2	29684	1	0	0
T3	125601	19	0	0
T4	10328	2	0	0
T5	188934	27	0	0
T6	14291	2	0	0
T7	24426	8	0	0
T8	17822	2	0	0
T9	12156	1	0	0
T10	9363	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53745326	8373	0	0
T1	247919	48	0	0
T2	29684	1	0	0
T3	125601	19	0	0
T4	10328	2	0	0
T5	188934	27	0	0
T6	14291	2	0	0
T7	24426	8	0	0
T8	17822	2	0	0
T9	12156	1	0	0
T10	9363	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51593772	8373	0	0
T1	237967	48	0	0
T2	28495	1	0	0
T3	120585	19	0	0
T4	9920	2	0	0
T5	181391	27	0	0
T6	13713	2	0	0
T7	23454	8	0	0
T8	17108	2	0	0
T9	11668	1	0	0
T10	8988	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51593772	8373	0	0
T1	237967	48	0	0
T2	28495	1	0	0
T3	120585	19	0	0
T4	9920	2	0	0
T5	181391	27	0	0
T6	13713	2	0	0
T7	23454	8	0	0
T8	17108	2	0	0
T9	11668	1	0	0
T10	8988	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797675	8373	0	0
T1	118968	48	0	0
T2	14247	1	0	0
T3	60287	19	0	0
T4	4959	2	0	0
T5	90695	27	0	0
T6	6856	2	0	0
T7	11717	8	0	0
T8	8554	2	0	0
T9	5833	1	0	0
T10	4494	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797675	8373	0	0
T1	118968	48	0	0
T2	14247	1	0	0
T3	60287	19	0	0
T4	4959	2	0	0
T5	90695	27	0	0
T6	6856	2	0	0
T7	11717	8	0	0
T8	8554	2	0	0
T9	5833	1	0	0
T10	4494	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	8373	0	0
T1	59502	48	0	0
T2	7123	1	0	0
T3	30144	19	0	0
T4	2479	2	0	0
T5	45343	27	0	0
T6	3427	2	0	0
T7	5866	8	0	0
T8	4277	2	0	0
T9	2916	1	0	0
T10	2246	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	8373	0	0
T1	59502	48	0	0
T2	7123	1	0	0
T3	30144	19	0	0
T4	2479	2	0	0
T5	45343	27	0	0
T6	3427	2	0	0
T7	5866	8	0	0
T8	4277	2	0	0
T9	2916	1	0	0
T10	2246	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797793	8373	0	0
T1	118984	48	0	0
T2	14247	1	0	0
T3	60280	19	0	0
T4	4957	2	0	0
T5	90702	27	0	0
T6	6857	2	0	0
T7	11724	8	0	0
T8	8554	2	0	0
T9	5834	1	0	0
T10	4494	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25797793	8373	0	0
T1	118984	48	0	0
T2	14247	1	0	0
T3	60280	19	0	0
T4	4957	2	0	0
T5	90702	27	0	0
T6	6857	2	0	0
T7	11724	8	0	0
T8	8554	2	0	0
T9	5834	1	0	0
T10	4494	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53745326	21736	0	0
T1	247919	138	0	0
T2	29684	1	0	0
T3	125601	43	0	0
T4	10328	6	0	0
T5	188934	102	0	0
T6	14291	6	0	0
T7	24426	8	0	0
T8	17822	2	0	0
T9	12156	1	0	0
T10	9363	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53745326	21736	0	0
T1	247919	138	0	0
T2	29684	1	0	0
T3	125601	43	0	0
T4	10328	6	0	0
T5	188934	102	0	0
T6	14291	6	0	0
T7	24426	8	0	0
T8	17822	2	0	0
T9	12156	1	0	0
T10	9363	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	21736	0	0
T1	7611	138	0	0
T2	889	1	0	0
T3	3795	43	0	0
T4	308	6	0	0
T5	5683	102	0	0
T6	428	6	0	0
T7	734	8	0	0
T8	533	2	0	0
T9	363	1	0	0
T10	279	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	21736	0	0
T1	7611	138	0	0
T2	889	1	0	0
T3	3795	43	0	0
T4	308	6	0	0
T5	5683	102	0	0
T6	428	6	0	0
T7	734	8	0	0
T8	533	2	0	0
T9	363	1	0	0
T10	279	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53745326	21736	0	0
T1	247919	138	0	0
T2	29684	1	0	0
T3	125601	43	0	0
T4	10328	6	0	0
T5	188934	102	0	0
T6	14291	6	0	0
T7	24426	8	0	0
T8	17822	2	0	0
T9	12156	1	0	0
T10	9363	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53745326	21736	0	0
T1	247919	138	0	0
T2	29684	1	0	0
T3	125601	43	0	0
T4	10328	6	0	0
T5	188934	102	0	0
T6	14291	6	0	0
T7	24426	8	0	0
T8	17822	2	0	0
T9	12156	1	0	0
T10	9363	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	6650	0	0
T1	7611	23	0	0
T2	889	1	0	0
T3	3795	10	0	0
T4	308	1	0	0
T5	5683	27	0	0
T6	428	1	0	0
T7	734	8	0	0
T8	533	12	0	0
T9	363	1	0	0
T10	279	4	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53745326	21736	0	0
T1	247919	138	0	0
T2	29684	1	0	0
T3	125601	43	0	0
T4	10328	6	0	0
T5	188934	102	0	0
T6	14291	6	0	0
T7	24426	8	0	0
T8	17822	2	0	0
T9	12156	1	0	0
T10	9363	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53745326	21736	0	0
T1	247919	138	0	0
T2	29684	1	0	0
T3	125601	43	0	0
T4	10328	6	0	0
T5	188934	102	0	0
T6	14291	6	0	0
T7	24426	8	0	0
T8	17822	2	0	0
T9	12156	1	0	0
T10	9363	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	225	0	0
T1	7611	4	0	0
T2	889	0	0	0
T3	3795	1	0	0
T4	308	0	0	0
T5	5683	0	0	0
T6	428	0	0	0
T7	734	0	0	0
T8	533	0	0	0
T9	363	0	0	0
T10	279	0	0	0
T55	0	3	0	0
T56	0	4	0	0
T110	0	1	0	0
T111	0	3	0	0
T112	0	3	0	0
T114	0	8	0	0
T115	0	2	0	0
T116	0	4	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628529	8373	0	0
T1	7611	48	0	0
T2	889	1	0	0
T3	3795	19	0	0
T4	308	2	0	0
T5	5683	27	0	0
T6	428	2	0	0
T7	734	8	0	0
T8	533	2	0	0
T9	363	1	0	0
T10	279	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11394841	21736	0	0
T1	48146	138	0	0
T2	7033	1	0	0
T3	26177	43	0	0
T4	2284	6	0	0
T5	42244	102	0	0
T6	3330	6	0	0
T7	5124	8	0	0
T8	4210	2	0	0
T9	2850	1	0	0
T10	2156	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11394841	21736	0	0
T1	48146	138	0	0
T2	7033	1	0	0
T3	26177	43	0	0
T4	2284	6	0	0
T5	42244	102	0	0
T6	3330	6	0	0
T7	5124	8	0	0
T8	4210	2	0	0
T9	2850	1	0	0
T10	2156	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11394841	21736	0	0
T1	48146	138	0	0
T2	7033	1	0	0
T3	26177	43	0	0
T4	2284	6	0	0
T5	42244	102	0	0
T6	3330	6	0	0
T7	5124	8	0	0
T8	4210	2	0	0
T9	2850	1	0	0
T10	2156	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11394841	21736	0	0
T1	48146	138	0	0
T2	7033	1	0	0
T3	26177	43	0	0
T4	2284	6	0	0
T5	42244	102	0	0
T6	3330	6	0	0
T7	5124	8	0	0
T8	4210	2	0	0
T9	2850	1	0	0
T10	2156	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	21736	0	0
T1	59502	138	0	0
T2	7123	1	0	0
T3	30144	43	0	0
T4	2479	6	0	0
T5	45343	102	0	0
T6	3427	6	0	0
T7	5866	8	0	0
T8	4277	2	0	0
T9	2916	1	0	0
T10	2246	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12898623	21736	0	0
T1	59502	138	0	0
T2	7123	1	0	0
T3	30144	43	0	0
T4	2479	6	0	0
T5	45343	102	0	0
T6	3427	6	0	0
T7	5866	8	0	0
T8	4277	2	0	0
T9	2916	1	0	0
T10	2246	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11394841	21736	0	0
T1	48146	138	0	0
T2	7033	1	0	0
T3	26177	43	0	0
T4	2284	6	0	0
T5	42244	102	0	0
T6	3330	6	0	0
T7	5124	8	0	0
T8	4210	2	0	0
T9	2850	1	0	0
T10	2156	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11394841	21736	0	0
T1	48146	138	0	0
T2	7033	1	0	0
T3	26177	43	0	0
T4	2284	6	0	0
T5	42244	102	0	0
T6	3330	6	0	0
T7	5124	8	0	0
T8	4210	2	0	0
T9	2850	1	0	0
T10	2156	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11394841	21736	0	0
T1	48146	138	0	0
T2	7033	1	0	0
T3	26177	43	0	0
T4	2284	6	0	0
T5	42244	102	0	0
T6	3330	6	0	0
T7	5124	8	0	0
T8	4210	2	0	0
T9	2850	1	0	0
T10	2156	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11394841	21736	0	0
T1	48146	138	0	0
T2	7033	1	0	0
T3	26177	43	0	0
T4	2284	6	0	0
T5	42244	102	0	0
T6	3330	6	0	0
T7	5124	8	0	0
T8	4210	2	0	0
T9	2850	1	0	0
T10	2156	2	0	0