Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	586923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

353082

1

T1

2

T3

2202

T4

372

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	500070	1			T3	3349		T4	523		T5	1500
values[0x0]	219363	1			T1	2		T3	1337		T4	243
values[0x1]	220572	1			T1	5		T3	1347		T4	234

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	492707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

447298

1

T1

2

T3

2822

T4

465

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3691	1			T3	25		T4	3		T5	48
valid_sources[0x01]	3298	1			T3	19		T4	3		T5	3
valid_sources[0x02]	6999	1			T3	19		T4	5		T5	21
valid_sources[0x03]	3484	1			T3	10		T4	9		T5	28
valid_sources[0x04]	3221	1			T3	30		T4	1		T5	7
valid_sources[0x05]	2942	1			T3	26		T4	2		T5	18
valid_sources[0x06]	4060	1			T3	15		T4	5		T5	24
valid_sources[0x07]	3084	1			T3	22		T4	7		T5	20
valid_sources[0x08]	3381	1			T3	31		T4	5		T5	3
valid_sources[0x09]	3309	1			T3	10		T4	4		T5	12
valid_sources[0x0a]	4333	1			T3	24		T4	2		T5	10
valid_sources[0x0b]	3070	1			T3	37		T4	3		T5	3
valid_sources[0x0c]	4396	1			T3	33		T4	4		T5	13
valid_sources[0x0d]	3339	1			T3	22		T4	5		T5	16
valid_sources[0x0e]	3445	1			T3	18		T5	7		T11	10
valid_sources[0x0f]	6559	1			T3	43		T4	3		T5	8
valid_sources[0x10]	4453	1			T3	19		T4	3		T5	6
valid_sources[0x11]	3589	1			T3	13		T4	4		T5	11
valid_sources[0x12]	4112	1			T3	57		T4	8		T5	21
valid_sources[0x13]	3107	1			T3	21		T4	3		T5	12
valid_sources[0x14]	3695	1			T3	14		T4	9		T5	29
valid_sources[0x15]	4010	1			T3	25		T4	3		T5	10
valid_sources[0x16]	3510	1			T1	1		T3	18		T4	1
valid_sources[0x17]	3018	1			T3	31		T4	3		T5	17
valid_sources[0x18]	3745	1			T3	18		T4	6		T5	10
valid_sources[0x19]	3229	1			T3	31		T4	3		T5	14
valid_sources[0x1a]	3187	1			T3	5		T4	3		T5	19
valid_sources[0x1b]	3325	1			T3	12		T4	6		T5	10
valid_sources[0x1c]	3283	1			T3	19		T4	5		T5	8
valid_sources[0x1d]	3260	1			T3	27		T4	6		T5	33
valid_sources[0x1e]	3835	1			T3	42		T4	2		T5	8
valid_sources[0x1f]	4119	1			T3	34		T4	5		T5	10
valid_sources[0x20]	3354	1			T3	24		T4	4		T5	7
valid_sources[0x21]	3865	1			T3	41		T4	6		T5	24
valid_sources[0x22]	4200	1			T3	25		T4	4		T5	17
valid_sources[0x23]	3196	1			T3	23		T4	1		T6	1
valid_sources[0x24]	3170	1			T3	28		T4	10		T5	6
valid_sources[0x25]	4045	1			T3	32		T4	3		T5	16
valid_sources[0x26]	3580	1			T3	28		T4	2		T5	12
valid_sources[0x27]	3824	1			T3	11		T4	10		T5	1
valid_sources[0x28]	3438	1			T3	4		T4	1		T5	22
valid_sources[0x29]	3075	1			T3	38		T4	6		T5	21
valid_sources[0x2a]	3572	1			T3	22		T4	2		T5	13
valid_sources[0x2b]	3683	1			T3	22		T4	2		T5	11
valid_sources[0x2c]	3230	1			T3	31		T4	3		T5	18
valid_sources[0x2d]	3078	1			T3	13		T4	5		T5	22
valid_sources[0x2e]	3348	1			T3	35		T4	2		T5	17
valid_sources[0x2f]	3338	1			T3	15		T4	4		T5	17
valid_sources[0x30]	3333	1			T3	20		T4	2		T5	10
valid_sources[0x31]	3341	1			T3	26		T4	4		T5	8
valid_sources[0x32]	4049	1			T3	22		T4	8		T5	3
valid_sources[0x33]	2909	1			T3	23		T4	3		T5	11
valid_sources[0x34]	6514	1			T3	14		T4	6		T5	3
valid_sources[0x35]	3649	1			T3	14		T4	5		T5	6
valid_sources[0x36]	3397	1			T3	13		T4	5		T5	16
valid_sources[0x37]	4626	1			T3	31		T4	1		T5	18
valid_sources[0x38]	3016	1			T3	20		T4	1		T5	10
valid_sources[0x39]	4419	1			T3	12		T4	1		T5	30
valid_sources[0x3a]	3014	1			T3	63		T4	5		T5	23
valid_sources[0x3b]	3699	1			T3	9		T4	2		T5	11
valid_sources[0x3c]	3037	1			T3	11		T4	4		T5	29
valid_sources[0x3d]	4012	1			T3	31		T4	2		T5	15
valid_sources[0x3e]	3819	1			T3	25		T4	3		T5	3
valid_sources[0x3f]	6808	1			T3	23		T4	4		T5	33
valid_sources[0x40]	4335	1			T3	35		T4	1		T5	12
valid_sources[0x41]	3462	1			T3	9		T4	5		T5	10
valid_sources[0x42]	3223	1			T3	55		T4	5		T5	14
valid_sources[0x43]	2840	1			T1	2		T3	27		T4	4
valid_sources[0x44]	3670	1			T3	23		T4	2		T5	16
valid_sources[0x45]	3327	1			T3	14		T4	4		T5	13
valid_sources[0x46]	3330	1			T3	13		T4	11		T5	24
valid_sources[0x47]	3150	1			T3	19		T4	7		T5	10
valid_sources[0x48]	4260	1			T3	28		T4	4		T5	20
valid_sources[0x49]	2847	1			T3	9		T4	2		T5	7
valid_sources[0x4a]	3283	1			T3	19		T4	4		T5	9
valid_sources[0x4b]	6714	1			T3	21		T4	3		T5	8
valid_sources[0x4c]	3133	1			T3	22		T4	5		T5	9
valid_sources[0x4d]	3371	1			T3	12		T4	3		T5	44
valid_sources[0x4e]	3411	1			T3	24		T5	13		T8	1
valid_sources[0x4f]	3218	1			T3	22		T4	3		T5	9
valid_sources[0x50]	3954	1			T3	12		T4	2		T5	21
valid_sources[0x51]	3059	1			T3	28		T4	4		T5	14
valid_sources[0x52]	2997	1			T3	51		T4	6		T5	15
valid_sources[0x53]	3588	1			T3	19		T4	1		T5	21
valid_sources[0x54]	3499	1			T3	15		T5	12		T6	3
valid_sources[0x55]	3468	1			T3	38		T4	4		T5	23
valid_sources[0x56]	6757	1			T3	35		T4	5		T6	2
valid_sources[0x57]	3302	1			T3	25		T4	4		T5	13
valid_sources[0x58]	3364	1			T3	51		T4	4		T5	5
valid_sources[0x59]	3433	1			T3	13		T4	4		T5	11
valid_sources[0x5a]	3532	1			T1	1		T3	14		T4	7
valid_sources[0x5b]	3044	1			T3	39		T4	3		T5	14
valid_sources[0x5c]	3061	1			T3	14		T4	4		T5	8
valid_sources[0x5d]	3918	1			T3	6		T4	8		T5	3
valid_sources[0x5e]	3225	1			T3	45		T4	6		T5	24
valid_sources[0x5f]	3430	1			T3	47		T4	7		T5	11
valid_sources[0x60]	3080	1			T3	46		T4	7		T6	1
valid_sources[0x61]	3835	1			T3	24		T4	3		T5	13
valid_sources[0x62]	3289	1			T3	25		T4	7		T5	5
valid_sources[0x63]	3219	1			T3	16		T4	3		T5	9
valid_sources[0x64]	3450	1			T3	14		T4	4		T5	32
valid_sources[0x65]	3891	1			T3	15		T4	2		T5	6
valid_sources[0x66]	3237	1			T3	17		T4	3		T5	17
valid_sources[0x67]	3117	1			T3	33		T4	5		T5	9
valid_sources[0x68]	4228	1			T3	16		T5	4		T7	2
valid_sources[0x69]	3309	1			T3	9		T4	5		T5	21
valid_sources[0x6a]	4246	1			T3	1		T4	5		T5	13
valid_sources[0x6b]	3547	1			T3	13		T4	6		T5	4
valid_sources[0x6c]	3786	1			T3	15		T4	4		T5	7
valid_sources[0x6d]	3710	1			T3	14		T4	1		T5	10
valid_sources[0x6e]	3507	1			T3	22		T4	6		T5	4
valid_sources[0x6f]	3064	1			T3	9		T4	6		T5	19
valid_sources[0x70]	3257	1			T3	12		T4	4		T5	17
valid_sources[0x71]	3107	1			T3	37		T4	7		T5	2
valid_sources[0x72]	3654	1			T3	29		T4	1		T5	2
valid_sources[0x73]	3464	1			T3	16		T4	4		T5	10
valid_sources[0x74]	3841	1			T3	24		T4	6		T5	15
valid_sources[0x75]	2962	1			T3	27		T4	2		T5	6
valid_sources[0x76]	3173	1			T3	15		T4	3		T5	16
valid_sources[0x77]	3516	1			T3	31		T4	6		T5	20
valid_sources[0x78]	3457	1			T3	11		T4	3		T5	9
valid_sources[0x79]	3571	1			T3	13		T4	8		T5	10
valid_sources[0x7a]	5947	1			T3	26		T4	6		T5	22
valid_sources[0x7b]	4189	1			T3	6		T4	5		T5	7
valid_sources[0x7c]	6605	1			T3	11		T4	2		T5	24
valid_sources[0x7d]	3169	1			T3	27		T4	4		T5	1
valid_sources[0x7e]	4597	1			T3	22		T4	3		T5	12
valid_sources[0x7f]	3211	1			T3	71		T4	8		T5	3
valid_sources[0x80]	3082	1			T1	1		T3	30		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

234882

1

T3

1534

T4

252

T5

672

values[0x0]

all_enables

biggest_size

76798

1

T1

1

T3

435

T4

87

values[0x1]

all_enables

biggest_size

41402

1

T1

1

T3

233

T4

33