Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T2,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T2,T3,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12906044	13425	0	0
gen_assertions[0].RstEnOn_A	12906044	1035	0	0
gen_assertions[0].RstNOff_A	12906044	13425	0	0
gen_assertions[0].RstNOn_A	12906044	1035	0	0
gen_assertions[1].RstEnOff_A	51624079	12221	0	0
gen_assertions[1].RstEnOn_A	51624079	1007	0	0
gen_assertions[1].RstNOff_A	51624079	12221	0	0
gen_assertions[1].RstNOn_A	51624079	1007	0	0
gen_assertions[2].RstEnOff_A	25813013	12275	0	0
gen_assertions[2].RstEnOn_A	25813013	1010	0	0
gen_assertions[2].RstNOff_A	25813013	12275	0	0
gen_assertions[2].RstNOn_A	25813013	1010	0	0
gen_assertions[3].RstEnOff_A	25812948	12307	0	0
gen_assertions[3].RstEnOn_A	25812948	1034	0	0
gen_assertions[3].RstNOff_A	25812948	12307	0	0
gen_assertions[3].RstNOn_A	25812948	1034	0	0
gen_assertions[4].RstEnOff_A	1628738	20868	0	0
gen_assertions[4].RstEnOn_A	1628738	1091	0	0
gen_assertions[4].RstNOff_A	1628738	20868	0	0
gen_assertions[4].RstNOn_A	1628738	1091	0	0
gen_assertions[5].RstEnOff_A	12906044	13690	0	0
gen_assertions[5].RstEnOn_A	12906044	1157	0	0
gen_assertions[5].RstNOff_A	12906044	13690	0	0
gen_assertions[5].RstNOn_A	12906044	1157	0	0
gen_assertions[6].RstEnOff_A	12906044	13737	0	0
gen_assertions[6].RstEnOn_A	12906044	1200	0	0
gen_assertions[6].RstNOff_A	12906044	13737	0	0
gen_assertions[6].RstNOn_A	12906044	1200	0	0
gen_assertions[7].RstEnOff_A	12906044	13762	0	0
gen_assertions[7].RstEnOn_A	12906044	1232	0	0
gen_assertions[7].RstNOff_A	12906044	13762	0	0
gen_assertions[7].RstNOn_A	12906044	1232	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	13425	0	0
T3	46909	80	0	0
T4	10318	5	0	0
T5	29205	75	0	0
T6	2552	4	0	0
T7	388698	324	0	0
T8	3280	14	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	75	0	0
T12	4558	13	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	1035	0	0
T3	46909	7	0	0
T4	10318	5	0	0
T5	29205	0	0	0
T6	2552	0	0	0
T7	388698	22	0	0
T8	3280	7	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	0	0	0
T12	4558	1	0	0
T26	0	2	0	0
T27	0	4	0	0
T28	0	1	0	0
T38	0	19	0	0
T105	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	13425	0	0
T3	46909	80	0	0
T4	10318	5	0	0
T5	29205	75	0	0
T6	2552	4	0	0
T7	388698	324	0	0
T8	3280	14	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	75	0	0
T12	4558	13	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	1035	0	0
T3	46909	7	0	0
T4	10318	5	0	0
T5	29205	0	0	0
T6	2552	0	0	0
T7	388698	22	0	0
T8	3280	7	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	0	0	0
T12	4558	1	0	0
T26	0	2	0	0
T27	0	4	0	0
T28	0	1	0	0
T38	0	19	0	0
T105	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51624079	12221	0	0
T3	187643	71	0	0
T4	41271	8	0	0
T5	116805	66	0	0
T6	10216	3	0	0
T7	155468	285	0	0
T8	13123	12	0	0
T9	23282	0	0	0
T10	8769	0	0	0
T11	226233	68	0	0
T12	18237	11	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51624079	1007	0	0
T3	187643	9	0	0
T4	41271	8	0	0
T5	116805	0	0	0
T6	10216	0	0	0
T7	155468	16	0	0
T8	13123	4	0	0
T9	23282	0	0	0
T10	8769	0	0	0
T11	226233	0	0	0
T12	18237	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T38	0	14	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51624079	12221	0	0
T3	187643	71	0	0
T4	41271	8	0	0
T5	116805	66	0	0
T6	10216	3	0	0
T7	155468	285	0	0
T8	13123	12	0	0
T9	23282	0	0	0
T10	8769	0	0	0
T11	226233	68	0	0
T12	18237	11	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51624079	1007	0	0
T3	187643	9	0	0
T4	41271	8	0	0
T5	116805	0	0	0
T6	10216	0	0	0
T7	155468	16	0	0
T8	13123	4	0	0
T9	23282	0	0	0
T10	8769	0	0	0
T11	226233	0	0	0
T12	18237	0	0	0
T26	0	3	0	0
T27	0	3	0	0
T38	0	14	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25813013	12275	0	0
T3	93828	68	0	0
T4	20636	9	0	0
T5	58408	66	0	0
T6	5108	3	0	0
T7	777401	285	0	0
T8	6562	12	0	0
T9	11635	0	0	0
T10	4384	0	0	0
T11	113100	68	0	0
T12	9118	11	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25813013	1010	0	0
T3	93828	5	0	0
T4	20636	9	0	0
T5	58408	0	0	0
T6	5108	0	0	0
T7	777401	18	0	0
T8	6562	0	0	0
T9	11635	0	0	0
T10	4384	0	0	0
T11	113100	0	0	0
T12	9118	0	0	0
T26	0	3	0	0
T27	0	5	0	0
T38	0	15	0	0
T64	0	9	0	0
T105	0	1	0	0
T109	0	11	0	0
T110	0	16	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25813013	12275	0	0
T3	93828	68	0	0
T4	20636	9	0	0
T5	58408	66	0	0
T6	5108	3	0	0
T7	777401	285	0	0
T8	6562	12	0	0
T9	11635	0	0	0
T10	4384	0	0	0
T11	113100	68	0	0
T12	9118	11	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25813013	1010	0	0
T3	93828	5	0	0
T4	20636	9	0	0
T5	58408	0	0	0
T6	5108	0	0	0
T7	777401	18	0	0
T8	6562	0	0	0
T9	11635	0	0	0
T10	4384	0	0	0
T11	113100	0	0	0
T12	9118	0	0	0
T26	0	3	0	0
T27	0	5	0	0
T38	0	15	0	0
T64	0	9	0	0
T105	0	1	0	0
T109	0	11	0	0
T110	0	16	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25812948	12307	0	0
T3	93807	71	0	0
T4	20637	10	0	0
T5	58418	66	0	0
T6	5106	3	0	0
T7	777423	287	0	0
T8	6563	12	0	0
T9	11643	0	0	0
T10	4384	0	0	0
T11	113113	68	0	0
T12	9118	11	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25812948	1034	0	0
T3	93807	8	0	0
T4	20637	10	0	0
T5	58418	0	0	0
T6	5106	0	0	0
T7	777423	19	0	0
T8	6563	0	0	0
T9	11643	0	0	0
T10	4384	0	0	0
T11	113113	0	0	0
T12	9118	0	0	0
T26	0	5	0	0
T27	0	6	0	0
T38	0	15	0	0
T64	0	9	0	0
T105	0	1	0	0
T109	0	11	0	0
T110	0	20	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25812948	12307	0	0
T3	93807	71	0	0
T4	20637	10	0	0
T5	58418	66	0	0
T6	5106	3	0	0
T7	777423	287	0	0
T8	6563	12	0	0
T9	11643	0	0	0
T10	4384	0	0	0
T11	113113	68	0	0
T12	9118	11	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25812948	1034	0	0
T3	93807	8	0	0
T4	20637	10	0	0
T5	58418	0	0	0
T6	5106	0	0	0
T7	777423	19	0	0
T8	6563	0	0	0
T9	11643	0	0	0
T10	4384	0	0	0
T11	113113	0	0	0
T12	9118	0	0	0
T26	0	5	0	0
T27	0	6	0	0
T38	0	15	0	0
T64	0	9	0	0
T105	0	1	0	0
T109	0	11	0	0
T110	0	20	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	20868	0	0
T1	164	1	0	0
T2	733	3	0	0
T3	5995	117	0	0
T4	1289	12	0	0
T5	3666	75	0	0
T6	317	4	0	0
T7	49235	478	0	0
T8	408	14	0	0
T9	729	3	0	0
T10	272	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	1091	0	0
T3	5995	8	0	0
T4	1289	11	0	0
T5	3666	0	0	0
T6	317	0	0	0
T7	49235	19	0	0
T8	408	0	0	0
T9	729	0	0	0
T10	272	0	0	0
T11	7084	0	0	0
T12	570	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T38	0	15	0	0
T47	0	1	0	0
T107	0	1	0	0
T109	0	13	0	0
T110	0	18	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	20868	0	0
T1	164	1	0	0
T2	733	3	0	0
T3	5995	117	0	0
T4	1289	12	0	0
T5	3666	75	0	0
T6	317	4	0	0
T7	49235	478	0	0
T8	408	14	0	0
T9	729	3	0	0
T10	272	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1628738	1091	0	0
T3	5995	8	0	0
T4	1289	11	0	0
T5	3666	0	0	0
T6	317	0	0	0
T7	49235	19	0	0
T8	408	0	0	0
T9	729	0	0	0
T10	272	0	0	0
T11	7084	0	0	0
T12	570	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T38	0	15	0	0
T47	0	1	0	0
T107	0	1	0	0
T109	0	13	0	0
T110	0	18	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	13690	0	0
T3	46909	78	0	0
T4	10318	11	0	0
T5	29205	75	0	0
T6	2552	4	0	0
T7	388698	323	0	0
T8	3280	14	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	75	0	0
T12	4558	13	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	1157	0	0
T3	46909	6	0	0
T4	10318	11	0	0
T5	29205	0	0	0
T6	2552	0	0	0
T7	388698	22	0	0
T8	3280	0	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	0	0	0
T12	4558	0	0	0
T26	0	8	0	0
T27	0	8	0	0
T38	0	17	0	0
T105	0	1	0	0
T109	0	12	0	0
T110	0	18	0	0
T111	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	13690	0	0
T3	46909	78	0	0
T4	10318	11	0	0
T5	29205	75	0	0
T6	2552	4	0	0
T7	388698	323	0	0
T8	3280	14	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	75	0	0
T12	4558	13	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	1157	0	0
T3	46909	6	0	0
T4	10318	11	0	0
T5	29205	0	0	0
T6	2552	0	0	0
T7	388698	22	0	0
T8	3280	0	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	0	0	0
T12	4558	0	0	0
T26	0	8	0	0
T27	0	8	0	0
T38	0	17	0	0
T105	0	1	0	0
T109	0	12	0	0
T110	0	18	0	0
T111	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	13737	0	0
T3	46909	78	0	0
T4	10318	10	0	0
T5	29205	75	0	0
T6	2552	4	0	0
T7	388698	321	0	0
T8	3280	14	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	75	0	0
T12	4558	13	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	1200	0	0
T3	46909	5	0	0
T4	10318	10	0	0
T5	29205	0	0	0
T6	2552	0	0	0
T7	388698	18	0	0
T8	3280	0	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	0	0	0
T12	4558	0	0	0
T26	0	8	0	0
T27	0	8	0	0
T38	0	15	0	0
T64	0	14	0	0
T109	0	12	0	0
T110	0	17	0	0
T112	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	13737	0	0
T3	46909	78	0	0
T4	10318	10	0	0
T5	29205	75	0	0
T6	2552	4	0	0
T7	388698	321	0	0
T8	3280	14	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	75	0	0
T12	4558	13	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	1200	0	0
T3	46909	5	0	0
T4	10318	10	0	0
T5	29205	0	0	0
T6	2552	0	0	0
T7	388698	18	0	0
T8	3280	0	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	0	0	0
T12	4558	0	0	0
T26	0	8	0	0
T27	0	8	0	0
T38	0	15	0	0
T64	0	14	0	0
T109	0	12	0	0
T110	0	17	0	0
T112	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	13762	0	0
T3	46909	76	0	0
T4	10318	12	0	0
T5	29205	75	0	0
T6	2552	4	0	0
T7	388698	324	0	0
T8	3280	14	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	75	0	0
T12	4558	13	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	1232	0	0
T3	46909	4	0	0
T4	10318	12	0	0
T5	29205	0	0	0
T6	2552	0	0	0
T7	388698	20	0	0
T8	3280	0	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	0	0	0
T12	4558	0	0	0
T26	0	9	0	0
T27	0	9	0	0
T38	0	14	0	0
T106	0	1	0	0
T107	0	1	0	0
T109	0	15	0	0
T110	0	17	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	13762	0	0
T3	46909	76	0	0
T4	10318	12	0	0
T5	29205	75	0	0
T6	2552	4	0	0
T7	388698	324	0	0
T8	3280	14	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	75	0	0
T12	4558	13	0	0
T13	0	4	0	0
T14	0	7	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12906044	1232	0	0
T3	46909	4	0	0
T4	10318	12	0	0
T5	29205	0	0	0
T6	2552	0	0	0
T7	388698	20	0	0
T8	3280	0	0	0
T9	5818	0	0	0
T10	2191	0	0	0
T11	56556	0	0	0
T12	4558	0	0	0
T26	0	9	0	0
T27	0	9	0	0
T38	0	14	0	0
T106	0	1	0	0
T107	0	1	0	0
T109	0	15	0	0
T110	0	17	0	0