Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12259072	8310	0	0
alert_regwen_rd_A	12259072	5273	0	0
cpu_regwen_rd_A	12259072	5317	0	0
sw_rst_ctrl_n_0_rd_A	12259072	10530	0	0
sw_rst_ctrl_n_1_rd_A	12259072	10699	0	0
sw_rst_ctrl_n_2_rd_A	12259072	10759	0	0
sw_rst_ctrl_n_3_rd_A	12259072	11381	0	0
sw_rst_ctrl_n_4_rd_A	12259072	10659	0	0
sw_rst_ctrl_n_5_rd_A	12259072	10558	0	0
sw_rst_ctrl_n_6_rd_A	12259072	10394	0	0
sw_rst_ctrl_n_7_rd_A	12259072	10865	0	0
sw_rst_regwen_0_rd_A	12259072	5833	0	0
sw_rst_regwen_1_rd_A	12259072	5900	0	0
sw_rst_regwen_2_rd_A	12259072	5793	0	0
sw_rst_regwen_3_rd_A	12259072	5791	0	0
sw_rst_regwen_4_rd_A	12259072	5850	0	0
sw_rst_regwen_5_rd_A	12259072	5795	0	0
sw_rst_regwen_6_rd_A	12259072	5664	0	0
sw_rst_regwen_7_rd_A	12259072	5933	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	8310	0	0
T67	2676	6	0	0
T70	22610	2	0	0
T71	4640	28	0	0
T72	2491	227	0	0
T73	5137	237	0	0
T87	11927	450	0	0
T90	2482	27	0	0
T91	2947	7	0	0
T95	10130	550	0	0
T114	3647	44	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5273	0	0
T7	348007	500	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T13	3599	0	0	0
T14	2570	0	0	0
T24	1481	0	0	0
T25	38392	0	0	0
T38	0	184	0	0
T117	0	89	0	0
T122	0	226	0	0
T137	0	15	0	0
T138	0	61	0	0
T139	0	77	0	0
T140	0	47	0	0
T141	0	231	0	0
T142	0	370	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5317	0	0
T7	348007	565	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T13	3599	0	0	0
T14	2570	0	0	0
T24	1481	0	0	0
T25	38392	0	0	0
T38	0	215	0	0
T117	0	90	0	0
T122	0	205	0	0
T137	0	25	0	0
T138	0	68	0	0
T139	0	64	0	0
T140	0	66	0	0
T141	0	215	0	0
T142	0	420	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	10530	0	0
T4	10226	112	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	826	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	156	0	0
T28	0	12	0	0
T38	0	375	0	0
T47	0	4	0	0
T105	0	17	0	0
T107	0	10	0	0
T109	0	138	0	0
T111	0	15	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	10699	0	0
T4	10226	143	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	725	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	139	0	0
T28	0	12	0	0
T38	0	374	0	0
T47	0	2	0	0
T105	0	16	0	0
T107	0	10	0	0
T109	0	168	0	0
T111	0	20	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	10759	0	0
T4	10226	114	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	830	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	132	0	0
T28	0	21	0	0
T38	0	415	0	0
T47	0	5	0	0
T105	0	17	0	0
T107	0	15	0	0
T109	0	127	0	0
T111	0	23	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	11381	0	0
T4	10226	133	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	801	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	177	0	0
T28	0	19	0	0
T38	0	418	0	0
T66	0	24	0	0
T105	0	11	0	0
T107	0	19	0	0
T109	0	150	0	0
T111	0	17	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	10659	0	0
T4	10226	113	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	724	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	145	0	0
T28	0	12	0	0
T38	0	359	0	0
T47	0	4	0	0
T105	0	10	0	0
T107	0	10	0	0
T109	0	156	0	0
T111	0	11	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	10558	0	0
T4	10226	139	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	852	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	139	0	0
T28	0	25	0	0
T38	0	413	0	0
T47	0	1	0	0
T105	0	17	0	0
T107	0	15	0	0
T109	0	102	0	0
T111	0	10	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	10394	0	0
T4	10226	87	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	690	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	155	0	0
T28	0	17	0	0
T38	0	426	0	0
T47	0	9	0	0
T105	0	15	0	0
T107	0	10	0	0
T109	0	140	0	0
T111	0	20	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	10865	0	0
T4	10226	109	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	787	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	141	0	0
T28	0	11	0	0
T38	0	404	0	0
T66	0	10	0	0
T105	0	18	0	0
T107	0	13	0	0
T109	0	118	0	0
T111	0	13	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5833	0	0
T4	10226	23	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	438	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	16	0	0
T38	0	193	0	0
T47	0	4	0	0
T66	0	8	0	0
T105	0	11	0	0
T107	0	9	0	0
T109	0	17	0	0
T111	0	3	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5900	0	0
T4	10226	21	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	504	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	31	0	0
T38	0	203	0	0
T47	0	3	0	0
T66	0	7	0	0
T105	0	8	0	0
T107	0	6	0	0
T109	0	20	0	0
T111	0	10	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5793	0	0
T4	10226	4	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	505	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	33	0	0
T38	0	191	0	0
T47	0	1	0	0
T66	0	11	0	0
T105	0	7	0	0
T107	0	12	0	0
T109	0	22	0	0
T111	0	8	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5791	0	0
T4	10226	25	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	474	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	25	0	0
T38	0	183	0	0
T47	0	3	0	0
T66	0	10	0	0
T105	0	4	0	0
T107	0	10	0	0
T109	0	46	0	0
T111	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5850	0	0
T4	10226	11	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	509	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	32	0	0
T38	0	192	0	0
T47	0	1	0	0
T66	0	5	0	0
T105	0	11	0	0
T107	0	8	0	0
T109	0	4	0	0
T111	0	5	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5795	0	0
T4	10226	19	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	551	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	21	0	0
T38	0	194	0	0
T47	0	11	0	0
T66	0	9	0	0
T105	0	11	0	0
T107	0	3	0	0
T109	0	20	0	0
T111	0	1	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5664	0	0
T4	10226	25	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	502	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	22	0	0
T38	0	187	0	0
T66	0	6	0	0
T105	0	10	0	0
T107	0	9	0	0
T109	0	11	0	0
T111	0	9	0	0
T143	0	12	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12259072	5933	0	0
T4	10226	28	0	0
T5	26056	0	0	0
T6	2218	0	0	0
T7	348007	543	0	0
T8	2254	0	0	0
T9	5466	0	0	0
T10	2101	0	0	0
T11	53512	0	0	0
T12	3605	0	0	0
T24	1481	0	0	0
T26	0	35	0	0
T38	0	226	0	0
T66	0	11	0	0
T105	0	11	0	0
T107	0	11	0	0
T109	0	14	0	0
T111	0	8	0	0
T143	0	7	0	0